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53
B. E. (Computer Science Engg.) Vth Semester
Examination, December-2002
COMPUTER ORGANISATION
Paper-CSE-303 C

9
8. Time allowed: 3 hours Maximum Marks: 100
(a) Discuss advantages of interleaved memory. 6 Explain
(b) . writing operation in associative memory. 6 A virtual
1. (a) Draw a combinational circuit that accepts a 3-bit number
(c) memory has a page size of 1 K words. There are 8 and generates an alp binary number equal to square of
pages and 4 blocks. The associative memory page table
ilp number. 8
contains:
(b) Implement following boolean fn. with NAND gates.
Make a list of all virtual addresses (in decimal) that Use inverters to complement ilps.
will cause a page fault if used by CPU. 8
F (x, y, z) = L (0, 2, 4, 5). 7
Block -..
Page
o 3
1 1
4 2
6 o
(c) JK flip flop can be converted to a D~ flip flop. True or
not? Justify.' 5

2. (a) Draw a block diagram for add micro-operation when

implemented in a serial computer.

Include two shift registers, one full-adder and a

flip flop to store the carry. Assume that initially carry
 flip flop is cleared. 10
(b) Show that an n-bit binary counter connected to an
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3. (a) Show how a 9-bit miclO operation field in a (%+C*D) +G.

microinstruction ,can be divided into subfields to 10.
x= C)
specify 46 micro-operations. How many micro- (D*E-F+ A
operations can be specified in one microinstruction?
7 6. (a) Draw a flow chart for addition and subtraction of
, (b) A microprogram control unit contains 1024 words of floating point numbers and explain,
100 bits each. If only 120 different bit combinations 10
(b) Explain the algorithm of BCD addition and
..••.
are used, how many bits can be saved by using a subtraction.
nanomemory ? What would be size of micromemory 10
7. (a) 'Define the following memory device characteristics:
and nanomemory ? 7
(c) Under what conditions would it be more feasible to use (i) Access Time
a hard-wired control than a microprogrammed control (ii) Access mode
unit? 6
(iii) Cycle time
4. (a) Explain the interrupt cycle through a flow chart. 10 (b)
(iv) Alterability. 1
What is Von-NeumannModel and stored program 0
principle ? 10 (b) The access time of a Cache memory is 100 ns and that
of main memory 1000 ns. It is estimated that 80% of
5. (a) What is addressing mode? Explain the following types of
the memory requests are for read and remaining 20%
addressing modes :
for write. The hit ratio for read accesses only is 0.9 . A
(i) Immediate
write through procedure is used.
(ii) Register indirect
(iii) Relative addressing mode.
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