Linear Integrated Circuits

UNIT I
INTRODUCTION TO OPERATIONAL AMPLIFIERS

What do you mean by IC?
IC Integrated Circuits. It is a complete Electronic Circuit in which
both passive and active components are fabricated on a single chip of
silicon. They are used in the computer, Automobile and many more
industries where they permit miniaturization and superior performance
not possible with discrete components. ICs are now being used in all
types of electronic equipments because of long, trouble free service they
provide. In addition, they are economical because they are mass
produced.
Types of ICs:
Integrated circuits can be classified based on many properties.
(i) Based on Mode of operation
(a) Digital I.C.
Digital ICs are complete functioning logic networks that are
equivalents of basic transistor logic circuit. They are used to form circuits
such as gates, counters, multiplexers, Demultiplexers, shift registers and
others. Since a digital IC is a complete predesigned package, it usually
requires nothing more than a power supply, input and output. These
circuits are primarily concerned with only two levels of voltage (or
current): High and Low. Therefore accurate control of operating region
characteristics is not required in digital circuits.
(b) Analog IC (Linear IC)
Linear ICs are equivalents of discrete transistor networks, such as
amplifiers, filters, frequency multipliers, and modulators that often require
VEL TECH Dr. RR & Dr. SR TECHNICAL UNIVERSITY
1
additional external components for a satisfactory operation. For example,
external resistors are necessary to control the voltage gain and the
frequency response of an Op-amp. In linear circuits the output electrical
signals vary in proportion to the input signals applied or the physical
quantities they represent. Since the electrical signals are analogous to the
physical quantities, linear circuits are also referred to as Analog Circuits.
(ii) Based on Fabrication
(a) Monolithic I.C.
It is a process in which all transistors and passive elements are
fabricated on a single piece of semi conductor material. Monolithic is a
Greek-based word meaning One Ston. The Monolithic process makes
low-cost mass production of ICs possible. Also Monolithic ICs exhibit good
thermal stability because all the components are integrated on the same
chip very close to each other.
(b) Hybrid I.C.
Here the passive components (such as resistors & capacitors) and the
interconnections between them are formed on an insulating substrate.
The substrate is used as a chassis for the integrated components. Active
components such as transistors and diodes as well as monolithic ICs are
then connected to form a complete circuit
(iii) Based on Integration level
SSI Small Scale Integration < (10-100) gates /
cm
2
MSI Medium Scale Integration < (100 1000) gates / cm
2
LSI Large Scale Integration < (1000 10000)
gates / cm
2
VLSI Very Large Scale Integration > 10000 gates / cm
2
About Digital I.C:
Digital ICs are complete functioning logic networks that are
equivalents of Basic transistor logic circuits. These ICs are primarily
concerned with only Digital circuits which have only two level of voltage:
`high and Low. Digital ICs are used to form circuits such as gates,
counters, multiplexers and others.
About Linear I.C:
Linear I.C. are equivalents of discrete transistor networks, such as
2
amplifiers, filters and modulators that often require additional external
components for satisfactory operation. In these linear circuits the output
electrical signals vary in proportion to the input signals applied or the
physical quantities they represent. Since the electrical signals are
analogous to the physical quantities, Linear circuits are also referred to as
Analog circuits.
Advantages of I.C:
Reduced size (Compactness)
Economical because they are mass produced.
Highly reliable due to the elimination of soldered joints.
Improved functional performance.
Increased operating speeds.
Reduced power consumption.
Basic building blocks of any linear I.C.
There are many blocks involved in the design of Linear ICs but the
following are the common circuits used in most of the circuits.
Constant current source circuits
Differential amplifiers
Band gap reference circuits
Supply and Temperature compensation circuits.
Why op-amp is considered to be the most important IC in the field
of Linear IC?
The OP-amp (Operational Amplifier) is a versatile device that can be
used to amplify dc as well as ac input signals and was originally such as
addition, subtraction, multiplication and integration. Thus the name
operational amplifier.With the addition of suitable external feedback
components, the modern day op-amp can be used for a variety of
applications. Such as ac and dc signal amplification, active filters,
oscillators, comparators, regulators and others.
THE IDEAL OP-AMP:
Operational Amplifiers, or Op-amps as they are more commonly called,
are one of the basic building blocks of Analogue Electronic Circuits. It is a
linear device that has all the properties required for nearly ideal DC
3
amplification and is used extensively in signal conditioning, filtering or to
perform mathematical operations such as add, subtract, integration and
differentiation. An ideal Operational Amplifier is basically a 3-terminal
device that consists of two high impedance inputs, one an Inverting input
marked with a negative sign, ("-") and the other a Non-inverting input
marked with a positive plus sign ("+"). The amplified output signal of an
Operational Amplifier is the difference between the two signals being
applied to the two inputs.
The following is a summary of the different types of Operational Amplifiers
and their configurations discussed in this tutorial section.
The Operational Amplifier, or Op-amp as it is most commonly
called, is an ideal amplifier with infinite Gain and Bandwidth when
used in the Open-loop mode with typical d.c. gains of 100,000, or
100dB.
The basic construction is of a 3-terminal device, 2-inputs and 1-
output.
An Operational Amplifier operates from a dual positive (+V) and
an corresponding negative (-V) supply but they can also operate from
a single DC supply voltage.
It has Infinite Input impedance, (Z) resulting in "No current
flowing into either of its two inputs" and zero input offset voltage "V1
= V2".
It also has Zero Output impedance, (Z=0).
Op-amps sense the difference between the voltage signals
applied to the two input terminals and then multiply it by some pre-
determined Gain, (A).
This Gain, (A) is often referred to as the amplifiers "Open-loop
Gain".
Op-amps can be connected into two basic circuits, Inverting and
Non-inverting.
Equivalent Circuit for Ideal Operational Amplifiers
4

IDEALIZED CHARACTERISTICS:
PARAMETER IDEALIZED CHARACTERISTIC
Voltage Gain, (A) Infinite - The main function of an operational
amplifier is to amplify the input signal and the
more open loop gain it has the better, so for
an ideal amplifier the gain will be infinite.
Input impedance, (Z
in
) Infinite - Input impedance is assumed to be
infinite to prevent any current flowing from
the source supply into the amplifiers input
circuitry.
Output impedance, (Z
out
) Zero - The output impedance of the ideal
operational amplifier is assumed to be zero so
that it can supply as much current as
necessary to the load.
Bandwidth, (BW) Infinite - An ideal operational amplifier has an
infinite Frequency Response and can amplify
any frequency signal so it is assumed to have
an infinite bandwidth.
Offset Voltage, (V
io
) Zero - The amplifiers output will be zero when
the voltage difference between the inverting
and non-inverting inputs is zero.
From these "idealized" characteristics above, we can see that the
input resistance is infinite, so no current flows into either input
terminal (the current rule) and that the differential input offset
5
voltage is zero (the voltage rule). It is important to remember these
two properties as they help understand the workings of the amplifier
with regards to analysis and design of operational amplifier circuits.
However, real Operational Amplifiers such as the commonly
available uA741, for example do not have infinite gain or bandwidth
but have a typical "Open Loop Gain" which is defined as the
amplifiers output amplification without any external feedback
signals connected to it and for a typical operational amplifier is
about 100dB at DC (zero Hz). This output gain decreases linearly
with frequency down to "Unity Gain" or 1, at about 1MHz and this is
shown in the following open loop gain response curve.
BLOCK DIAGRAM REPRESENTATION OF OP-AMP:
An operational amplifier is a direct coupled high gain amplifier. It is
available as a single integrated circuit package. The operational amplifier
is a versatile device that can be used to amplify dc as well as ac input
signals and was originally designed for performing mathematical
operations such as addition, subtraction, multiplication and integration.
Thus the name operational amplifier stems from its original use for these
mathematical operations and is abbreviated to Op-amp.
With the addition of suitable external feedback components, the modern
day Op-amp can be used for a variety of applications, such as ac and dc
signal amplification, active filters, oscillators, comparators, regulators and
others. Since an operations amplifier is a multistage amplifier, it can be
represented by a block diagram as shown below.
Block diagram representation of op-amp:
6
Input
Stage
Inter
mediate
Stage
Level
Shifting
Stage
Output
Stage
Dial up
D.A
Such as
Enter
forever
using
Current
Saver
Push-Pull
Amplifier
I/P
The purpose of Input stage in an Op-amp:
The Input stage of any operational amplifier is to provide the most
of the voltage gain and also to provide the higher input impedance. Most
time the input stage is designed with a Dual input Balanced output
differential amplifier.
The requirement of Intermediate stage in an Op-amp:
The intermediate stage is usually another differential amplifier.
Which is driven by the output of the first stage. The intermediate stage
provides the extra amplification required at times. In most amplifiers the
intermediate stage is a dual input, unbalanced output differential
amplifier.
Level shifting stage in Op-amp:
In Intermediate stage we use a direct coupling because of which dc
voltage at the output of this stage is well above ground potential. Hence
the level shifter (translator) circuit is used after intermediate stage to shift
the dc level downward to zero volts with respect to ground.
The purpose of output stage:
The final stage is usually a push pull complementary amplifier
output stage. The output stage increases the output voltage swing and
raises the current supplying capability of the Co-amp. A well designed
output stage also provides the low output resistance.
VOLTAGE TRANSFER CURVE OF OP-AMP:
This is the basic op-amp equation in which the output offset voltage
is assumed to be zero. The graphic representation of this equation is
shown; where the output voltage, Vo is plotted against input difference
voltage Vid, keeping gain A constant. The output voltage cannot exceed
the positive and negative saturation voltage. These saturation voltages
are specified by an output voltage swing ratings of an op-amp for given
values of supply voltages. The output voltage is directly proportional to
the input difference voltage until it reaches the saturation voltages and
thereafter the output voltage remains constant.
7
AC-DC CHARACTERISTICS OF AN OP-AMP:
Opamps are easy to design with as long as you follow some basic rules
and understand how they operate. I won't go into all the theory of
opamps, just the basics. There are other web sites such as Williamson
Labs that will cover the fundamentals. The basic characteristics are as
follows:
1) Assume the output impedance as almost zero.
2) Assume the - input impedance as almost zero.
3) Assume the + input impedance as almost infinite.
4) The gain is programmable by the feedback resistor, the resistor
from the output pin to the negative input pin, from zero to infinite
depending on the device.
5) An opamp can amplify AC or DC voltages, or both.
Most opamp designs require a bipolar power supply (plus and minus
voltage) unless you offset the input to think it is operating on a bipolar
supply. This will be explained later.
Let's take the circuit in Figure 17. It is a basic inverting DC opamp
configuration using a positive and negative power supply. (This circuit will
also respond to AC also. AC circuits can contain DC blocking capacitors to
keep the opamp operating within DC parameters but will roll off low
frequencies depending on values and will not respond to DC. AC amplifiers
will be discussed later.) For the purpose of this example let's say the
power supply voltages are +/- 15 volts. A basic circuit uses two resistors.
An input resistor (Rin) and a feedback resistor (Rf). In this example both
resistors will be 10K ohms.
8
If you were to build this circuit and ground the input (0 volts), you will see
0 volts on the output. If you place +1 volts on the input, you will get -1
volt on the output. If you place -1 volts on the input, the output will be +1
volt. Why? Look at the formula in Figure 18 below.
Voltage gain (inverting) equals the value of the feedback resistor divided
by the value of the input resistor for a gain of one, or unity. No gain, but
an identical inverse of the input. If you varied the input voltage from +1 to
-1 volts you will see the output swing from -1 to +1 volts. This could also
be referred to as a linear amplifier because it tracks whatever voltage is
on the input to the output in a linear fashion, only inverted. So what? Well,
you have a unity gain inverting amplifier. What could this be used for? You
have an input impedance of 10K ohms and an output impedance of almost
zero ohms. Enough to provide drive for the next circuit or circuits. This
could also be called an inverting buffer. How do you get 10K ohms input
impedance? Remember, the inverting input, pin 2 is virtually zero ohms,
so the input resistor (resistance) becomes the input impedance. What kind
of gain would you have if both the feedback and input resistors were
220K? The same gain, only you have an input impedance of 220K ohms.
Much less of a load so your input circuit won't "swamp" or load the
preceding circuit.
Ok, let's make this thing actually amplify. Change the feedback resistor to
100K ohms while leaving the input resistor at 10K. Vary the input voltage
to +1 volts. Now the output swings to -10 volts. Sweep the voltage all the
way to -1 volts and you will see the output track all the way to +10 volts.
This smooth output transition from -10 to +10 from a +1 to -1 input is why
9
this circuit is also called a linear amplifier, because the output reflects the
input times 10 only inverted. The formula for seeing a gain of ten is in
Figure 19.
So from this basic circuit you can see how you can select different
resistors to get different amounts of gain. Just remember, your output
swing will never exceed the power supply voltages (or rails) and actually a
volt or two less than each rail for a basic opamp in this demonstration.
Raise the input voltage to +2 volts and measure the output and you will
see that it rests somewhere around -12 to -13 volts. This is the "rail" or
the lowest possible output voltage for the given +/- 15 volts. It also may
be referred to as saturation of the opamp. Some opamps are called rail-to-
rail opamps and they come closer to the actual power supply voltage.
Almost 0.3 volts from the power supply voltage. Next we will study the
non-inverting opamp circuit. Figure 21 shows a simple non-inverting DC
opamp circuit. For purposes of demonstration, the feedback resistor will
be 100K ohms and the input resistors are 10K ohms.
Putting +1.0 volts on the input will give +11 volts on the output. Putting
-1.0 volts on the input will give -11 volts on the output.
10
Using the formula in Figure 22, we get a gain of 11 or eleven times
the input. This can be used as a DC or AC amplifier. What if we wanted a
gain of ten? Change the feedback resistor to 90K ohms. What if we
wanted it to be exactly unity gain? Remove the resistor to ground. The
feedback resistor can be any value.
How about a gain of 100? Use a 990k feedback resistor. However,
you are asking for a lot of gain from the opamp. Don't forget, that's a lot
of amplification. 1 volt on the input in theory will give you 100 volts on the
output but that cannot happen because the power supply rails only supply
15 volts. So, you will "saturate" the opamp and it will slam up against the
rail at somewhere around 13 volts. But, if you are amplifying a very small
voltage such as 10 millivolts (0.01 volts), you will get 1 volt output.
Remember, the gain number is the same as the multiplication factor. 0.01
X 100 = 1.
What other advantages does this circuit have? It is a true buffer. A
buffer is a circuit that will duplicate the input voltage but provides drive.
This is important if you have a high impedance circuit and you need to
drive a low impedance load or many loads. Remember, the + input to the
opamp is already a high impedance input. Thus, the input resistor is
almost irrelevant with the exception of possible protection of the input to
the opamp. Remember also that the output impedance is very low.
Theoretically zero ohms but usually around 47 ohms depending upon the
device you are using.
A buffer can also be called a "follower". It mimics the input with a
low impedance output drive. The following circuit in Figure 23 is what is
referred to as a follower.
11
The input resistor can be almost any value since the input impedance is
almost infinite or can sometimes be omitted. What ever the input sees, it
will duplicate it on the output. This can provide extra drive for another
circuit without loading the input circuit. The feedback in this circuit is a
short. It can be a resistor of almost any value as long as there isn't any
other resistor on the minus input.
Let's talk about AC opamp designs.
AC circuits are typically used in audio amplification. Also mixing of signals,
distributing audio, and processing audio. You don't really want to use a DC
amplifier unless you know exactly what you are doing. DC circuits have
their place in high quality audio amplifications but you must remember
that the output will follow the input precisely. This is not an advantage for
most applications. Input circuits of unknown DC potential can and will
offset the amplifier and possible render it useless or drawing excess
current. Especially if driving a speaker or headphones.
Figure 24 is a typical AC coupled opamp circuit used to amplify a weak
signal.
12
The above circuit has a gain of 100. With an AC signal of 5
millivolts (0.05 volts), you will see a output swing of +/- 5 volts. This
circuit is typically used in the audio frequency range. The determining
factor is the device itself which can amplify up to 1 megahertz but the
gain will decrease at higher frequencies. You will have to study the data
sheets for the device you will be using in order to determine high
frequency gain. The capacitors will determine the low frequency cut-off. In
some circumstances you could leave the capacitors out and the circuit will
function down to DC. As you can see, the two capacitors are polarized.
The positive leads are shown to be pointing towards the device. Since this
uses a bi-polar power supply, the voltage potential is sitting at zero volts.
Because of this, the capacitors can be placed either way as long as the
input and output are referenced to ground. Also, R4 is not needed in most
applications using a bi-polar power supply. The + input can be tied
directly to ground.
Hint: When troubleshooting the opamp, placing a voltmeter on any inputs
or outputs will show zero volts if there is no signal present. Any voltages
other than zero means the circuit is not connected right or the opamp is
defective.
Since bi-polar power supplies aren't always available, you can
operate this same circuit from a single ended power supply. All that is
necessary is that the -V pin is tied to ground and the + input is "biased" to
half the power supply voltage. Of course you must realize that in order to
keep the same headroom, you will have to double the positive supply. In
most cases this isn't necessary especially if working with small signals.
Also the two capacitors, C1 and C2, must be present in order to keep the
opamp stable and operating in its linear region. Figure 26 shows how to
connect the same circuit with a single power supply.
13
You can bias the + input by building a voltage divider, filtering it,
and applying the 1/2 voltage to the + input. C3 is not a critical value.
Neither is R4 and R5. They can be as high as 100K
Hint: When troubleshooting this circuit, both inputs and the output will be
idling at 1/2 the power supply voltage with no signal present. Any voltage
other than 1/2 the supply means the circuit is not wired properly or the
opamp is defective. Example. If you are using a 12 volt supply, the DC
voltage on pins 1, 2, and 3 must be 6 volts.
Frequency response - the usable bandwidth of the circuit. This is
usually the 3db point. An example is in Figure 26, R2 and C1. The
impedance is 10K ohms and the capacitance is 1uf. Using the formula
f=1/(2Pi*(R*C)), the usable low frequency is down to16 HZ. An opamp can
also be used as a bias generator (or reference) for providing 1/2 the power
supply voltage for other opamps on the same board using a single ended
(uni-polar) power supply. Figure 28 shows the circuit.
14
Since the + input is a high impedance input, the values of R1 and R2 can
be almost any value as long as they are the same value. The arbitrary
values of 47K will not provide a noticeable drain on the power supply.
Depending on noise and stability, it may be necessary to place a small
capacitor (U10) from the + input to ground but it is not mandatory. In
Figure 28, if the +V is 24 volts, the output will be +12 volts. If the +V is 5
volts, the output will be +2.5 volts. To turn this circuit into a power
regulator, replace R2 with a zener and R1 with an appropriate value, and
the output of the opamp will provide a buffered regulated voltage source
15
FREQUENCY RESPONSE OF NON-COMPENSATED OP-AMP:
The open-loop response gives you some powerful insight into the op
amps performance. Open-loop means NO feedback; the response of the
naked op amp. Two important features are
1. DC Gain, Aol the open-loop gain at DC. This gain is provided by the
voltage controlled voltage source EGAIN. A higher gain means a higher
bandwidth and more gain accuracy when you close the loop with feedback
resistors.
2. First-Pole Frequency, fp1 the frequency where the open-loop gain
begins to fall. A simple RC creates this low-pass filter.
fp1 = 1/( 2 * * RP1 * CP1)
3. Unity-Gain Frequency, fu - the frequency where the open-loop gain falls
to 1 V/V. The bigger the fu, the faster your op amp responds. What
determines this frequency? Its a function of the DC Gain Aol and fp1.
fu = Aol x fp1
16
Open-loop Frequency Response Curve
COMPENSATING NETWORKS:
DOMINANT POLE COMPENSATION:
The essential idea of frequency compensation applied to op-amp is to
reshape the magnitude and plot. So that |AV | <1 when the < AV =
180. For Dominant pole compensation a phase log network is introduced
to narrow band the dominant gain.
The amplifier is modified by adding a dominant pole as shown below.
The pole added in the circuit should be much smaller in magnitude than
all other poles in the forward transfer function, Consider A to be the
uncompensated transfer function of the op-amp in the open loop
condition.
The RC network in series with op-amp acis as the dominant pole
The compensated transfer function A
17
( ) ( ) ( )
1
1
1
where fd=
2 RC
1
AOL
A =
f f f
1+j 1 1
f1 f2 fn
o
i
V
A
V
i
wc
A
i
R
wc
A
A
f
j
fc
But
j j
+
+ +
1 2 3
1
0<f <f <f
' ' becomes
A
1 1 1
1 2
Where
A
AOL
f f f
j j j
fd f f
_ _ _
+ + +

, , ,
The capacitance c is chosen so that the modified. Loop gain drops to o
dB with a slope of -20dB decade.
Usually f
d
=
2
wd
is selected so that the compensated transfer function

A passes through O dB at the pole f
1
of the uncompensated A
The frequency can be found graphically by having A passes through O dB
at the frequency f with a slope of -20dB decade.
Advantage:
The noise immunity of the system is improved since the noise
frequency components outside the Bandwidth are eliminated.
Disadvantage:
It reduces the open loop band width drastically.
POLE ZERO COMPENSATION:
When the dominant pole is used we know that the open loop band
width is reduced drastically. To avoid this problem we can provide a
different compensating network known as pole zero compensation
18
Here adding both pole and zero alters the uncompensated transfer
function A
The transfer function of the compensating network is given by
0 2 2 1
2 1 2 1 2
0
1
1
_
+

+ +
+

,
f
j
V Z R f
f
V Z Z R R
j
f
( )
1 2
2 2 1 2 2
1 1
f
2 2
f
R C R R C
The compensating network is designed to produce a zero at the first
corner frequency f of the uncompensated transfer function A
The pole of compensating network at
2
wo
fo

is selected so that the

compensated transfer function A passes through odB at the second
corner.
Frequency f
2
of the uncompensated transfer function A
The frequency can be found graphically by having A passes through O dB
at the frequency F
2
with a slope of -20dB/ decade.
The overall transfer can be written as
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1 0
2 1
1 2
0
0 2
2
1
1
i
V V V
A
V V Vi
f
j
R f
A
f
R R
j
f

_
+

+
+

,
Since R
2
> R
1
the above equation becomes
1 1
0
1
1
f
j
f
A A
f
j
f
_
+

+

,
by using the value of A in the above equation we get
1
0 1 2 3
1 1 1
2 3
0
AOL
A
f f f
j j j
fo f f
Where
f f f f
_ _ _
+ + +

, , ,
< < < <
CLOSED-LOOP FREQUENCY RESPONSE:
The relationship between circuit gain and bandwidth in an operational-
amplifier circuit can be expressed by the GAIN-BANDWIDTH PRODUCT
(GAIN BANDWIDTH = UNITY GAIN POINT). In other words, for
operational-amplifier circuits, the gain times the bandwidth for one
configuration of an operational amplifier will equal the gain times the
bandwidth for any other configuration of the same operational amplifier.
In other words, when the gain of an operational-amplifier circuit is
changed (by changing the value of feedback or input resistors), the
bandwidth also changes. But the gain times the bandwidth of the first
configuration will equal the gain times the bandwidth of the second
configuration. The following example should help you to understand this
concept
20
Closed-loop frequency-response curve for gain of 10.
CIRCUIT STABILITY:
Op amp instability is compensated out with the addition of an external RC
network to the circuit. There are thousands of different op amps, but all of
them fall into two categories: uncompensated and internally
compensated. Uncompensated op amps always require external
compensation components to achieve stability; while internally
compensated op amps are stable, under limited conditions, with no
additional external components. Internally compensated op amps can be
made unstable in several ways: by driving capacitive loads, by adding
capacitance to the inverting input lead, and by adding in phase feedback
with external components. Adding in phase feedback is a popular method
of making an oscillator that is beyond the scope of this article. Input
capacitance is hard to avoid because the op amp leads have stray
capacitance and the printed circuit board contributes some stray
capacitance, so many internally compensated op amp circuits require
21
external compensation to restore stability. Output capacitance comes in
the form of some kind of loada cable, converter-input capacitance, or
filtercapacitanceand reduces stability in buffer configurations.
SLEW RATE:
Slew rate is the maximum rate of change of output voltage of op-
amp with respect to time, usually specified in V/M sec. for eg 2V/M sec.
Slew rate means that the output raises or falls no faster than 2v every
microseconds. Ideally we would like to have in finite slew rate so that the
output voltage would change simultaneously with the input.Practical op-
amps are available with slew rates from 0.1 V/Ms to well above 1000 v/Ms.
Slew rate is caused by current limiting and the saturation of internal
stages of an op-amp when a high frequency, large amplitude signal is
applied. The resulting current is the maximum current available to charge
the compensation capacitor raises is
dvc I
dt C
. This slew rate limiting is
caused by the capacitor charging rate in which the voltage across the
capacitor is the output voltage.We should role that unity gain bandwidth is
the small signal high frequency limitation on the phenomenon. A large
signal is one whose amplitude is comparable with the power supply
voltages. Typically small signal is in the range of milli or micro volts while
a large signal is on the order of volts.
Generally slew rate is specified for unity gain and is measured by
applying a step input (dc) voltage slew rate is sometimes given indirectly
in data sheets as output voltage swing. As a function of frequency or as a
voltage follower large signal pulse response. Slew rate limiting depends
on both frequency and amplitude often increases with closed loop gain
and power supply voltages. When slew rate increases over a certain value
distortion starts to get involved.
Generally the slew rate is specified for unity gain and hence let us
considers the voltage follower shown below.
22
Let us assume that the input is a large amplitude and high frequency
sinewave. The equation of the input signal is
Vs = Vm sin wmt
With no slew rate limitation
Vo = Vmsinwmt and
dvo
WVm
dt
wmt.
The maximum rate of change of the output occurs
Coswt =1
When
max
6
rate = 2 f VM volt / sec
2 fVm
slew rate = V/Msec
10
dvo
WVm
dt
or
slew

faithful reproduction of this sinusoid requires that WVm slew rate. For
output free of distortion the slew rate determines the maximum frequency
of operation f
max
for a desired output swing. The frequency f
max
is called full
power band width and is defined as the maximum frequency at which an
undistorted sinusoidal can be obtained with peak voltage vm. Thus
23
max
.
2 output swing
rate
2 Vm
S R
F
peat
slew

For most general purpose op-amps few power bandwidth ranges

from 5 to 50 KHZ for a peak output swing of 10v.
METHODS OF IMPROVING SLEW RATE:
The slew rate can be improved with higher closed loop gain and d.c
supply voltage. But the slew rate also varies with temperature i.e slew
rate decreases with increase in temperature.
Another method of improving slew rate is The rate at which voltage
across the capacitor increases is given by
dvc

dt
I
C
Where I is the maximum current furnished by the op amp to the capacitor

C. From the equation it is clear that for a higher slew rate op-amp should
have either a higher current or a small value of capacitor.
INVERTING AND NON-INVERTING CONFIGURATION:
INVERTING AMPLIFIER:
We saw in the last tutorial that the Open Loop Gain of an ideal Operational
Amplifier can be very high, up to about 1,000,000 (120dB) or more.
However, this very high gain is of no real use to us as it makes the
amplifier both unstable and hard to control as the smallest of input
signals, just a few micro-volts, would be enough to cause the output to
saturate and swing towards one or the other of the voltage supply rails
losing control. As the open loop DC gain of an operational amplifier is
extremely high we can afford to lose some of this gain by connecting a
suitable resistor across the amplifier from the output terminal back to the
inverting input terminal to both reduce and control the overall gain of the
amplifier. This then produces and effect known commonly as Negative
Feedback, and thus produces a very stable Operational Amplifier system.
Negative Feedback is the process of "feeding back" some of the output
signal back to the input, but to make the feedback negative we must feed
24
it back to the "Negative input" terminal using an external Feedback
Resistor called Rf. This feedback connection between the output and the
inverting input terminal produces a closed loop circuit to the amplifier
resulting in the gain of the amplifier now being called its Closed-loop Gain.
This results in the inverting input terminal having a different signal on it
than the actual input voltage as it will be the sum of the input voltage plus
the negative feedback voltage giving it the label or term of a Summing
Point. We must therefore separate the real input signal from the inverting
input by using an Input Resistor, Rin. As we are not using the positive non-
inverting input this is connected to a common ground or zero voltage
terminal as shown below, but the effect of this closed loop feedback
circuit results in the voltage potential at the inverting input being equal to
that at the non-inverting input producing a Virtual Earth summing point
because it will be at the same potential as the grounded reference input.
Inverting Amplifier Circuit
25
In this Inverting Amplifier circuit the operational amplifier is connected
with feedback to produce a closed loop operation. There are two very
important rules to remember about inverting amplifiers is that, "no
current flows into the input terminal" and that "V1 equals V2". This is
because the junction of the input and feedback signal (X) is at the same
potential as the positive (+) input which is at zero volts or ground then,
the junction is a "Virtual Earth". Because of this virtual earth node the
input resistance of the amplifier is equal to the value of the input resistor,
Rin and the closed loop gain of the inverting amplifier can be set by the
ratio of the two external resistors.
We said above that there are two very important rules to remember about
Inverting Amplifiers or any operational amplifier for that matter and they
are.
1. No Current Flows into the Input Terminals
2. The Differential Input Voltage is Zero as V1=V2 = 0
(Virtual Earth)
Then by using these two rules we can find the equation for calculating the
gain of an inverting amplifier, using first principles.
Current ( i ) flows through the resistor network as shown.
26
Then, the Closed-Loop Voltage Gain of an Inverting Amplifier is given as.
and this can be transposed to give:
The negative sign in the equation indicates an inversion of the output
signal with respect to the input as it is 180
o
out of phase. This is due to
the feedback being negative in value.
27
Example No1
Find the closed loop gain of the following inverting amplifier circuit.
Using the previously found formula for the gain of the circuit
we can now substitute the values of the resistors in the circuit as follows,
Rin = 10k and Rf = 100k.
and the gain of the circuit is calculated as -Rf/Rin = 100k/10k = 10.
therefore, the closed loop gain of the inverting amplifier circuit above is
given 10 or 20dB.
Example No 2.
The gain of the original circuit is to be increased to 40, find the new
values of the resistors required.
Assume that the input resistor is to remain at the same value of 10K,
then by re-arranging the closed loop voltage gain formula we can find the
new value required for the feedback resistor Rf.
Gain = -Rf/Rin
therefore, Rf = Gain x Rin
28
Rf = 40 x 10,000
Rf = 400,000 or 400K
The new values of resistors required for the circuit to have a gain of 40
would be,
Rin = 10K and Rf = 400K.
The formula could also be rearranged to give a new value of Rin, keeping
the same value of Rf. One final point to note about Inverting Amplifiers, if
the two resistors are of equal value, Rin = Rf then the gain of the
amplifier will be -1 producing a complementary form of the input voltage
at its output as Vout = -Vin. This type of inverting amplifier configuration
is generally called a Unity Gain Inverter of simply an Inverting Buffer.
NON-INVERTING AMPLIFIER:
The second basic configuration of an operational amplifier circuit is that of
a Non-inverting Amplifier. In this configuration, the input voltage signal,
(Vin) is applied directly to the Non-inverting (+) input terminal which
means that the output gain of the amplifier becomes "Positive" in value in
contrast to the "Inverting Amplifier" circuit we saw in the last tutorial and
whose output gain is negative in value. Feedback control of the non-
inverting amplifier is achieved by applying a small part of the output
voltage signal back to the inverting (-) input terminal via a Rf - R2 voltage
divider network, again producing negative feedback.
This produces a Non-inverting Amplifier circuit with very good stability, a
very high input impedance, Rin approaching infinity (as no current flows
into the positive input terminal) and a low output impedance, Rout as
shown below.
Non-inverting Amplifier
29
In the previous Inverting Amplifier tutorial, we said that "no current flows
into the input" of the amplifier and that "V1 equals V2". This was because
the junction of the input and feedback signal (V1) are at the same
potential in other words the junction is a "Virtual Earth" summing point.
Because of this virtual earth node the resistors, Rf and R2 form a simple
voltage divider network across the amplifier and the voltage gain of the
circuit is determined by the ratios of R2 and Rf as shown below.
Equivalent Voltage Divider Network
Then using the formula to calculate the output voltage of a potential
divider network, we can calculate the output Voltage Gain of the Non-
inverting Amplifier as:
30
Then the closed loop voltage gain of a Non-inverting Amplifier is given as:
We can see that the overall gain of a Non-Inverting Amplifier is greater but
never less than 1 (unity), is positive and is determined by the ratio of the
values of Rf and R2. If the feedback resistor Rf is zero the gain will be
equal to 1 (unity), and if resistor R2 is zero the gain will approach infinity,
but in practice it will be limited to the operational amplifiers open-loop
differential gain, (A
o
)
The amplified output signal of an Operational Amplifier is the difference
between the two signals being applied to the two inputs. In other words
the output signal is a differential signal between the two inputs and the
input stage of an Operational Amplifier is in fact a differential amplifier as
shown below.
IDEAL OPEN-LOOP AND CLOSED-LOOP OPERATION OF OP-AMP:
The input stage is a differential amplifier. The differential amplifier used
as an input stage provides differential inputs and a frequency response
down to d.c. Special techniques are used to provide the high input
impedance necessary for the operational amplifier. The second stage is a
high-gain voltage amplifier. This stage may be made from several
transistors to provide high gain. A typical operational amplifier could have
a voltage gain of 200,000. Most of this gain comes from the voltage
amplifier stage. The final stage of the OP AMP is an output amplifier. The
output amplifier provides low output impedance. The actual circuit used
31
could be an emitter follower. The output stage should allow the
operational amplifier to deliver several milliamperes to a load. Notice that
the operational amplifier has a positive power supply (+V
CC
) and a
negative power supply (-V
EE
). This arrangement enables the operational
amplifier to produce either a positive or a negative output. The two input
terminals are labeled "inverting input" (-) and "noninverting input" (+).
The operational amplifier can be used with three different input conditions
(modes). With differential inputs (first mode), both input terminals are
used and two input signals which are 180 degrees out of phase with each
other are used. This produces an output signal that is in phase with the
signal on the noninverting input. If the noninverting input is grounded and
a signal is applied to the inverting input (second mode), the output signal
will be 180 degrees out of phase with the input signal (and one-half the
amplitude of the first mode output). If the inverting input is grounded and
a signal is applied to the noninverting input (third mode), the output
signal will be in phase with the input signal (and one-half the amplitude of
the first mode output).
BLOCK DIAGRAM OF AN OPERATIONAL AMPLIFIER.
CLOSED LOOP OP-AMP:
Op-amp is in closed loop configuration when there is a connection either
direct or via another network exist between the input and output
terminals. We can control the gain of op-amp if we introduce a
modification in the basic circuit. This modification involves a feedback ie
32
the input signal is fed back to the input either direct or via another
network.
OPEN LOOP OP-AMP:
Open-loop operational amplifier
Here, an operational amplifier is shown without a feedback loop (i.e.,
"open loop"), in order to illustrate some of its fundamental properties.
Operational amplifiers are almost never used in this way, because the
open loop gain is far too high to be useful. The differential input voltage
(the voltage between the two input terminals of the op amp), V
diff
, is
controlled by the slider on the left. The output voltage V
out
= A*V
diff
.
Because the open-loop gain A is so big, V
out
is saturated unless V
diff
is very
small. Note that the output voltage of an operational amplifier has definite
voltage limits. In this case the limits are +14 volts and -14 volts. If you
attempt to make the output voltage exceed those limits, the output will
"saturate" at the limit until the input voltage is reduced. You can
investigate the effect of the open-loop gain with the slider on the right
(Most op amps have an open-loop gain of 50,000 or higher). The
differential input current, I
d
, is the current that flows between the inputs of
33
the op amp. It is given by V
diff
/R
d
and is very small if the output is not
saturated, because then V
diff
is very small and R
d
is typically 1 Megohm or
greater
BLOCK DIAGRAM REPRESENTATION OF FEEDBACK
CONFIGURATIONS:
Different feedback configurations
An op-amp that uses feedback is called a feedback amplifier. A
feedback amplifier is sometimes referred to as a closed loop amplifier
because the feedback forms a closed loop between the input and the
output. A close loop amplifier can be represented by using two blocks one
for op-amp and the other for a feedback circuit. These connections are
classified according to whether the voltage or current is fed back to the
input in series or parallel.
1. Voltage series feedback
2. Voltage shunt feedback
3. Current series feedback
4. Current shunt feedback.
34
35
UNIT II
GENERAL LINEAR APPLICATIONS
INPUT OFFSET PROBLEMS:
It is important to note that the equations shown below, pertaining to each
type of circuit, assume that an ideal op amp is used. Those interested in
construction of any of these circuits for practical use should consult a
more detailed reference. See the External links and Further reading
sections. Resistors used in practical solid-state op-amp circuits are
typically in the k range. Resistors much greater than 1 M cause
excessive thermal noise and make the circuit operation susceptible to
significant errors due to bias or leakage currents. Practical operational
amplifiers draw a small current from each of their inputs due to bias
requirements and leakage. These currents flow through the resistances
connected to the inputs and produce small voltage drops across those
resistances. In AC signal applications this seldom matters. If high-precision
DC operation is required, however, these voltage drops need to be
considered. The design technique is to try to ensure that these voltage
drops are equal for both inputs, and therefore cancel. If these voltage
drops are equal and the common-mode rejection ratio of the operational
amplifier is good, there will be considerable cancellation and improvement
in DC accuracy.
If the input currents into the operational amplifier are equal, to reduce
offset voltage the designer must ensure that the DC resistance looking out
of each input is also matched. In general input currents differ, the
difference being called the input offset current, I
os
. Matched external input
resistances R
in
will still produce an input voltage error of R
in
I
os
Most
manufacturers provide a method for tuning . the operational amplifier to
balance the input currents (e.g., "offset null" or "balance" pins that can
interact with an external voltage source attached to a potentiometer).
Otherwise, a tunable external voltage can be added to one of the inputs in
order to balance out the offset effect. In cases where a design calls for
one input to be short-circuited to ground, that short circuit can be
replaced with a variable resistance that can be tuned to mitigate the
offset problem.
36
Power supply effects:
Although the power supplies are not shown in the operational amplifier
designs below, they can be critical in operational amplifier design. Power
supply imperfections (e.g., power signal ripple, non-zero source
impedance) may lead to noticeable deviations from ideal operational
amplifier behavior. For example, operational amplifiers have a specified
power supply rejection ratio that indicates how well the output can reject
signals that appear on the power supply inputs. Power supply inputs are
often noisy in large designs because the power supply is used by nearly
every component in the design, and inductance effects prevent current
from being instantaneously delivered to every component at once. As a
consequence, when a component requires large injections of current (e.g.,
a digital component that is frequently switching from one state to
another), nearby components can experience sagging at their connection
to the power supply. This problem can be mitigated with copious use of
bypass capacitors placed connected across each power supply pin and
ground. When bursts of current are required by a component, the
component can bypass the power supply by receiving the current directly
from the nearby capacitor (which is then slowly charged by the power
supply).
Additionally, current drawn into the operational amplifier from the power
supply can be used as inputs to external circuitry that augment the
capabilities of the operational amplifier. For example, an operational
amplifier may not be fit for a particular high-gain application because its
output would be required to generate signals outside of the safe range
generated by the amplifier. In this case, an external pushpull amplifier
can be controlled by the current into and out of the operational amplifier.
Thus, the operational amplifier may itself operate within its factory
specified bounds while still allowing the negative feedback path to include
a large output signal well outside of those bounds.
DC & AC AMPLIFIERS:
37
Here's one challenge of today's electronics: if it's portable, it likely to be
battery powered, and your circuit must be designed to perform in a single-
supply world. The key to single-supply design is in remembering that
voltage potentials are meaningful only when taken relative to other
potentials. For an op amp circuit, the bottom line is this: the signal should
be somewhere around mid supply. The table below compares the
potentials of a dual versus single supply design.
PEAKING AMPLIFIER:
The circuit shown in Figure 1 has a maximum output (or 'peaks') at a
certain frequency. It is said to have a peaking frequency response,
hence its name 'peaking amplifier'. The main component of this circuit
is the operational amplifier (such as the 741 or 351), which is
configured as an inverting amplifier with a parallel LC network in the
feedback circuit. This LC network in the feedback path is the one that
determines the frequency at which the output of the circuit peaks. This
frequency fp is known as its resonant or peak frequency, and is given
by: fp = 1 / [2(sqrt(LC))]. At the resonant frequency, the impedance of
the parallel LC network becomes very high. If this impedance is
denoted by Rr, then the gain G of the amplifier in Figure 1 at resonant
frequency is given by: G = -(RF//Rr) / R1. At frequencies below or above
fp, the impedance of the LC network is below Rr, which means that the
gain G of the amplifier circuit is also less than [-(RF//Rr) / R1]. This is
why the output of the circuit is maximum at the resonant frequency.
38
Circuit Diagram for an Op-Amp-based Peaking Amplifier
SUMMING:
Summing Amplifier
The Summing Amplifier is a very flexible circuit based upon the standard
Inverting Operational Amplifier configuration. We saw previously in the
Inverting Amplifier tutorial that the Inverting Amplifier has a single input
signal applied to the Inverting input terminal. If we add another input
resistor equal in value to the original input resistor, Rin we end up with
another operational amplifier circuit called a Summing Amplifier,
"Summing Inverter" or even a "Voltage Adder" circuit as shown below.
Summing Amplifier Circuit
39
The output voltage, (Vout) now becomes proportional to the sum of the
input voltages, V1, V2, V3 etc. Then we can modify the original equation
for the inverting amplifier to take account of these new inputs thus:
However, if all the input impedances, (Rin) are equal in value the final
equation for the output voltage is given as:
We now have an operational amplifier circuit that will amplify each
individual input voltage and produce an output voltage signal that is
proportional to the algebraic "SUM" of the three individual input voltages
V
1
, V
2
and V
3
. We can also add more inputs if required as each individual
input "see's" their respective resistance, Rin as the only input impedance.
This is because the input signals are effectively isolated from each other
by the "virtual earth" node at the inverting input of the op-amp. A direct
voltage addition can also be obtained when all the resistances are of
equal value and Rf is equal to Rin.
A Scaling Summing Amplifier can be made if the individual input resistors
are "NOT" equal. Then the equation would have to be modified to:
40
We can also rearrange the formula to make the feedback resistor R
F
the
subject and the output voltage is found from
Allowing the output voltage to be easily calculated if more input resistors
are connected to the amplifiers input. The input impedance of each
individual channel is the value of their respective input resistors, ie, R
1
, R
2
,
R
3
... etc.
The Summing Amplifier is a very flexible circuit indeed, enabling us to
effectively "Add" or "Sum" together several individual input signals. If the
inputs resistors, R
1
, R
2
, R
3
etc, are all equal a unity gain inverting adder
can be made. However, if the input resistors are of different values a
"scaling summing amplifier" is produced which gives a weighted sum of
the input signals.
Example No1
Find the output voltage of the following Summing Amplifier circuit.
Summing Amplifier
Using the previously found formula for the gain of the circuit
41
We can now substitute the values of the resistors in the circuit as follows,
we know that the output voltage is the sum of the two amplified input
signals and is calculated as:
then the output voltage of the Summing Amplifier circuit above is given as
-45 mV and is negative as its an inverting amplifier.
If the input resistances of a summing amplifier are connected to
potentiometers the individual input signals can be mixed together by
varying amounts. For example, measuring temperature, you could add a
negative offset voltage to make the display read "0" at the freezing point
or produce an audio mixer for adding or mixing together individual
waveforms (sounds) from different source channels (vocals, instruments,
etc) before sending them combined to an audio amplifier.
Summing Amplifier Audio Mixer
SCALING AND AVERAGING AMPLIFIER:
A SCALING AMPLIFIER is a special type of summing amplifier with the
output signal determined by multiplying each input signal by a different
42
factor (determined by the ratio of the input- signal resistor and feedback
resistor) and then adding these products.
AVERAGING AMPLIFIER:
The summing amplifier can output the average of two, three or more
signals. This is different than a signal average. The summing amplifier
cannot, for example, output the average of a triangle signal. For that, you
need an integrator to perform the average in the analog realm, or you
need to sample the signal and calculate the average with a
microcontroller. This type of average is the signal average in the time
domain. I will write an article about the average of a signal in a near
future.
In this post I will show you how to average two or more signals with a
summing amplifier. In How to Derive the Summing Amplifier Transfer
Function I wrote that the summing amplifier shown in Figure 1
43
Figure 1
Has the following transfer function:
(1)
If R1 and R2 are equal, and equal with a common value Rin, as in Figure 2,
Figure 2
the new transfer function becomes
(2)
The equation shows that, when R1 = R2 the amplifier output level is the
average between the two input signals times the gain of 1 + R4/R3. In
reality, the two resistors cannot be perfectly equal, due to tolerances, so
you will still have to use equation (1) for a correct calculation of the
output signal. Still, if you choose matched resistors, the output will be
44
very close to the theoretical expression of equation (2).
Now, the fact that Rin does not count in the average transfer function
does not mean that Rin can be any value. This resistor has to be chosen
carefully, because it dictates the loading of the input signals. Indeed,
looking at the amplifier in fig 2, if we write the loop equation for V1, Rin,
Rin, V2, and consider that the current in the op amp input is insignificant,
the loop current is
(3)
Therefore, the smaller Rin is, the larger the current sourced/sunk by V1
and V2. If we choose Rin in the kiloohms or tens of kiloohms range, the
loading on the input signals will not be significant for the usual op amp
voltage levels.
As an example, the summing amplifier in Figure 3 is an average amplifier
with two input signals, made with Analog Devices OP27GS.
Figure 3
The first signal, v1(t) has a frequency of 1 kHz, an amplitude of 0.5V and
rides on a 4V DC level. The second signal, v2(t) has a frequency of 2 kHz,
an amplitude of 0.5V and rides on a 2V DC level. Every moment in time
the amplifier performs the average between the two signals. The
waveforms are shown in Figure 4, where the output signal is shown with
green. For this example I removed the gain resistors R4 and R3 to better
illustrate the average of the two input signals. In this case, the average
45
amplifier has a gain of one, so that the output signal lands exactly
between input signals as in Figure 4.
Figure 4
But what if we have 3, 4 or more input signals and we need to build a
circuit that outputs the average of all these signals?
In The Transfer Function of the Non-Inverting Summing Amplifier with N
Input Signals I demonstrated the transfer function of a summing amplifier
with multiple inputs (see Figure 5).
Figure 5
46
In that article I showed that the transfer function is
(4)
where j counts the input signals and k the input resistors.
The average of n input signals can be achieved the same way as we did
with the summing amplifier in Figure 1. We will make all input resistors
equal, so that R1 = R2 = = Rn = Rin, then we can reduce the
parenthesis to a simple expression as in equation (5),
(5)
Where with Rin I noted the common value of the input resistors.
In this case Vout becomes
(6)
and, reduced even more,
(7)
Equation (7) is the output level of an average amplifier with n input
signals and with the gain of 1 + Rf2/Rf1. One can easily see that equation
(7) is the same as equation (2) when n = 2.
INSTRUMENTATION AMPLIFIER:
47
An instrumentation (or instrumentational) amplifier is a type of differential
amplifier that has been outfitted with input buffers, which eliminate the
need for input impedance matching and thus make the amplifier
particularly suitable for use in measurement and test equipment.
Additional characteristics include very low DC offset, low drift, low noise,
very high open-loop gain, very high common-mode rejection ratio, and
very high input impedances. Instrumentation amplifiers are used where
great accuracy and stability of the circuit both short- and long-term are
required.
Although the instrumentation amplifier is usually shown schematically
identical to a standard op-amp, the electronic instrumentation amp is
almost always internally composed of 3 op-amps. These are arranged so
that there is one op-amp to buffer each input (+,), and one to produce
the desired output with adequate impedance matching for the function.
The most commonly used instrumentation amplifier circuit is shown in the
figure. The gain of the circuit is The rightmost amplifier, along with the
resistors labelled R
2
and R
3
is just the standard differential amplifier
circuit, with gain = R
3
/ R
2
and differential input resistance = 2R
2
. The two
amplifiers on the left are the buffers. With R
gain
removed (open circuited),
they are simple unity gain buffers; the circuit will work in that state, with
gain simply equal to R
3
/ R
2
and high input impedance because of the
buffers. The buffer gain could be increased by putting resistors between
the buffer inverting inputs and ground to shunt away some of the
negative feedback; however, the single resistor R
gain
between the two
48
inverting inputs is a much more elegant method: it increases the
differential-mode gain of the buffer pair while leaving the common-mode
gain equal to 1. This increases the common-mode rejection ratio (CMRR)
of the circuit and also enables the buffers to handle much larger common-
mode signals without clipping than would be the case if they were
separate and had the same gain. Another benefit of the method is that it
boosts the gain using a single resistor rather than a pair, thus avoiding a
resistor-matching problem (although the two R
1
s need to be matched),
and very conveniently allowing the gain of the circuit to be changed by
changing the value of a single resistor. A set of switch-selectable resistors
or even a potentiometer can be used for R
gain
, providing easy changes to
the gain of the circuit, without the complexity of having to switch matched
pairs of resistors.
The ideal common-mode gain of an instrumentation amplifier is zero. In
the circuit shown, common-mode gain is caused by mismatches in the
values of the equally-numbered resistors and by the mis-match in
common mode gains of the two input op-amps. Obtaining very closely
matched resistors is a significant difficulty in fabricating these circuits, as
is optimizing the common mode performance of the input op-amps.
[3]
VOLTAGE TO - CURRENT CONVERTER
A voltage to current converter accepts an input voltage and produces an
output current which is proportional to the input voltage.
The circuit below shows the voltage to current converter in which
load resistor RL is floating (not connected to ground)

The input voltage is applied to the non inverting input terminal and the
feed back across R
1
drives the inverting input terminal. This circuit is also
49
called a current series negative feed back amplifier because the feedback
voltage across R
1
(applied to the inverting terminal) depend on the output
current I and is in series with the input difference voltage V
id
.
Analysis:
Writing kirchoffs voltage equation for the input loop.
V
in
= V
id
= V
f
But V
id
=0 due to Virtual ground.
in 1
1
V = R

in f
o
in
o
V V
i
V
i
R
This means that in the circuit an input voltage V
in
is converted in to an
output current i
o
= Vin/R1. In other words, input voltage vin appears
across R
1
. if R
1
is a precision resistor, the output current (io) will be
precisely fixed.
The voltage to current converter can be used in such applications as
Low voltage dc and ac voltmeters
Diode match finders
Light emitting diodes (LEDS)
Zener diode testers.
CURRENT TO VOLTAGE CONVERTER:
In a voltage to current converter if we are desired to ground one of the
load terminals. It is no longer possible to place the load with in the
feedback loop of the op amp. The voltage to current converter circuit
shown below is suitable in case of grounded load. The purpose of the
positive feedback is to raise the effective output resistance of the circuit
and ideally make it infinite as required for the ideal current source.
50
In this circuit one terminal of the load is grounded and load current is
controlled by an input voltage.
Analysis:
The analysis of the circuit is accomplished by first determining the
voltage V
1
at the non inverting input terminal and then establishing the
relationship between V
1
and the load current.
Applying KCL at node V
1
I
1
+ I
2=
I
L
1 1
1
0
1
2
2

+
+
+
in o
L
in L
in L
V V V V
I
R R
V Vo V RI
V V I R
v
Since op-amp is connected in non inverting mode gain = 1+ R/R = R V
o
= 2 Vin
V
0
= Vin + V
o
- I
L
R
that is
V
in
= I
L
R
Or
in
L
V
I
R
This means that load current depend on the input voltage
V
in
and resistor R. Notice that as resistors must be equal in value. The
circuit will perform satisfactorily provided that load size less than R
51
value.
THE INTEGRATOR:
In the previous tutorials we have seen circuits which show how an
operational amplifier can be used as part of a positive or negative
feedback amplifier or as an adder or subtractor type circuit using just
resistors in both the input and the feedback loop. But what if we were to
change the purely Resistive (Rf) feedback element of an inverting
amplifier to that of a Frequency Dependant Impedance, (Z) type element,
such as a Capacitor, C. We now have a resistor and capacitor combination
forming an RC Network across the operational amplifier as shown below.
Integrator Amplifier Circuit
As its name implies, the Integrator Amplifier is an operational amplifier
circuit that performs the mathematical operation of Integration, that is we
can cause the output to respond to changes in the input voltage over time
and the integrator amplifier produces a voltage output which is
proportional to that of its input voltage with respect to time. In other
words the magnitude of the output signal is determined by the length of
time a voltage is present at its input as the current through the feedback
loop charges or discharges the capacitor.
When a voltage, Vin is firstly applied to the input of an integrating
amplifier, the uncharged capacitor C has very little resistance and acts a
bit like a short circuit (voltage follower circuit) giving an overall gain of
less than 1, thus resulting in zero output. As the feedback capacitor C
begins to charge up, its reactance Xc decreases and the ratio of Zf/Rin
increases producing an output voltage that continues to increase until the
52
capacitor is fully charged. At this point the ratio of feedback capacitor to
input resistor (Zf/Rin) is infinite resulting in infinite gain and the output of
the amplifier goes into saturation as shown below. (Saturation is when the
output voltage of the amplifier swings heavily to one voltage supply rail or
the other with no control in between).
The rate at which the output voltage increases (the rate of change) is
determined by the value of the resistor and the capacitor, "RC time
constant". By changing this RC time constant value, either by changing
the value of the Capacitor, C or the Resistor, R, the time in which it takes
the output voltage to reach saturation can also be changed for example.
If we apply a constantly changing input signal such as a square wave to
the input of an Integrator Amplifier then the capacitor will charge and
discharge in response to changes in the input signal. This results in the
output signal being that of a sawtooth waveform whose frequency is
dependant upon the RC time constant of the resistor/capacitor
combination. This type of circuit is also known as a Ramp Generator and
the transfer function is given below.
53
Ramp Generator
Since the node voltage of the integrating op-amp at its inverting input
terminal is zero, the current Iin flowing through the input resistor is given
as:
The current flowing through the feedback capacitor C is given as:
Assuming that the input impedance of the op-amp is infinite (ideal op-
amp), no current flows into the op-amp terminal. Therefore, the nodal
equation at the inverting input terminal is given as:
From which we have an ideal voltage output for the Integrator Amplifier
as:
54
This can also be re-written as:
Where j = 2 and the output voltage Vout is a constant 1/RC times the
integral of the input voltage Vin with respect to time. The minus sign (-)
indicates a 180
0
phase shift because the input signal is connected directly
to the inverting input terminal of the op-amp.
The AC or Continuous Integrator:
If we changed the above square wave input signal to that of a sine wave
of varying frequency the Integrator Amplifier begins to behave like an
active "Low Pass Filter", passing low frequency signals while attenuating
the high frequencies. At 0Hz or DC, the capacitor acts like an open circuit
blocking any feedback voltage resulting in very little negative feedback
from the output back to the input of the amplifier. Then with just the
feedback capacitor, C, the amplifier effectively is connected as a normal
open-loop amplifier which has very high open-loop gain resulting in the
output voltage saturating.
This circuit connects a high value resistance in parallel with a continuously
charging and discharging capacitor. The addition of this resistor, R
2
across
the capacitor, C gives the circuit the characteristics of an inverting
amplifier with finite closed-loop gain of R
2
/R
1
at very low frequencies while
acting as an integrator at higher frequencies has the capacitor shorts out
the feedback resistor, R
2
.
The AC Integrator with DC Gain Control
This then forms the basis of a Active Low Pass Filter as seen before in the
filters section tutorials with a corner frequency given as.
55
THE DIFFERENTIATOR:
The basic Differentiator Amplifier circuit is a the exact opposite to that of
the Integrator operational amplifier circuit that we saw in the previous
tutorial. Here, the position of the capacitor and resistor have been
reversed and now the Capacitor, C is connected to the input terminal of
the inverting amplifier while the Resistor, Rf forms the negative feedback
element across the operational amplifier. This circuit performs the
mathematical operation of Differentiation, that is it produces a voltage
output which is proportional to the input voltage's rate-of-change and the
current flowing through the capacitor. In other words the faster or larger
the change to the input voltage signal, the greater the input current, the
greater will be the output voltage change in response becoming more of a
"spike" in shape.
As with the integrator circuit, we have a resistor and capacitor forming an
RC Network across the operational amplifier and the reactance (Xc) of the
capacitor plays a major role in the performance of a Differentiator
Amplifier.
Differentiator Amplifier Circuit
The capacitor blocks any DC content only allowing AC type signals to pass
through and whose frequency is dependant on the rate of change of the
56
input signal. At low frequencies the reactance of the capacitor is "High"
resulting in a low gain (Rf/Xc) and low output voltage from the op-amp. At
higher frequencies the reactance of the capacitor is much lower resulting
in a higher gain and higher output voltage from the differentiator
amplifier.
However, at high frequencies a differentiator circuit becomes unstable
and will start to oscillate. This is due mainly to the First-order effect, which
determines the frequency response of the op-amp circuit causing a
Second-order response which, at high frequencies gives an output voltage
far higher than what was expected. To avoid this the high frequency gain
of the circuit needs to be reduced by adding an additional small value
capacitor across the feedback resistor Rf.
Ok, some math's to explain what's going on. Since the node voltage of the
operational amplifier at its inverting input terminal is zero, the current, i
flowing through the capacitor will be given as:
The Charge on the Capacitor = Capacitance x Voltage across the
Capacitor
The rate of change of this charge is
but dQ/dt is the capacitor current i
From which we have an ideal voltage output for the Differentiator
Amplifier is given as:
Therefore, the output voltage Vout is a constant -Rf.C times the derivative
of the input voltage Vin with respect to time. The minus sign indicates a
180
0
phase shift because the input signal is connected to the inverting
57
input terminal of the operational amplifier.
One final point to mention, the Differentiator Amplifier circuit in its basic
form has two main disadvantages compared to the previous Integrator
circuit. One is that it suffers from instability at high frequencies as
mentioned above, and the other is that the capacitive input makes it very
susceptible to random noise signals and any noise or harmonics present in
the circuit will be amplified more than the input signal itself. This is
because the output is proportional to the slope of the input voltage so
some means of limiting the bandwidth in order to achieve closed-loop
stability is required
Differentiator Waveforms
If we apply a constantly changing signal such as a Square-wave,
Triangular or Sine-wave type signal to the input of a differentiator
amplifier circuit the resultant output signal will be changed and whose
final shape is dependant upon the RC time constant of the
Resistor/Capacitor combination.
Improved Differentiator Amplifier
The basic single resistor and single capacitor differentiator circuit is not
widely used to reform the mathematical function of Differentiation
because of the two inherent faults mentioned above, Instability and Noise.
So in order to reduce the overall closed-loop gain of the circuit at high
58
frequencies, an extra Resistor, R2 is added to the input as shown below.
Improved Differentiator Amplifier Circuit
The circuit which we have now acts like a Differentiator amplifier at low
frequencies and an amplifier with resistive feedback at high frequencies
giving much better noise rejection. This then forms the basis of a Active
High Pass Filter as seen before in the filters section.
LOG AND ANTILOG AMPLIFIER:
LOG AMPLIFIER:
Log amplifiers are used to perform many functions such as l
n
, log
n
, or sin
The circuit of a log amplifier using op-amp is formed by providing a
grounded base transistor or diode at the feedback path of an inverting
amplifier transistor.
Since the collector is held at virtual ground and the base is also grounded,
59
the transistors, voltage, current relationship becomes that of the diode
and is given by
( )
( )
/
c
/
1
since I
1

qv kT
E s
E
qve kT
c E s
I I e
I
I I I e
I
s
is the emitter saturation current.
K Boltsman constant
T absolute temperature
( )
( )
( )
/
/
/
1
1
since 1
qvE kT c
qve kT c
qve kT c c
I
e
Is
I
e
Is
I I
e
Is Is

+
>>
Taking natural log and both sides we get
1
0
ln
vi
Ic=
R
E
E
KT Ic
V
q Is
But
V V
_

,

1
1
ln
ln
o
o
KT Vi
V
q R Is
KT Vi
V
q R Is

Where V
ref
= R
1
IS.
Thus the output voltage is proportional to the rognithm of input voltage.
PEAK DETECTOR:
The peak detector is a circuit that remembers the peak value of a
signal. As shown in Fig. 5-7, when a positive voltage is fed to the non-
inverting input after the capacitor has been momentarily shorted (reset),
the output voltage of the op-amp forward biases the diode and charges up
60
the capacitor. This charging lasts until the inverting
The Peak Detector.
And non-inverting inputs are at the same voltage, which is equal to the
input voltage. When the noninvertinginput voltage exceeds the voltage at
the inverting input, which is also the voltage across the capacitor, the
capacitor will charge up to the new peak value. Consequently, the
capacitor voltage will always be equal to the greatest positive voltage
applied to the non-inverting input. Once charged, the time that the peak
detector remembers this peak value is typically several minutes and
depends on the impedance of the load that is connected to the circuit.
Consequently, the capacitor will slowly discharge toward zero. To
minimize this rate of discharge, a voltage follower can be used to buffer.
The detectors output from any external load, as shown in Fig. 5-8.
Momentarily shorting the capacitor to ground immediately sets the output
to zero.
PRECISION RECTIFIERS:
When a diode is used as a rectifier to change an ac signal to a pulsating
dc signal, the diode does not begin to conduct until the voltage drop
across the diode is greater than 0.3 volt (for germanium types) or 0.7 volt
(for silicon types). Consequently, diodes by themselves are not suitable
for small-signal rectification. The half-wave rectifier, shown in Fig. 5-9, will
rectify small input signals. When the input signal is positive, all the current
in the feedback loop flows through D1 and the output voltage of the
circuit will be zero. When the input signal is negative, the current in the
61
feedback loop flows through diodes D1 and D2, so that the input voltage,
which appears inverted across R2, also is the output voltage.
Peak detector with buffer.
Precision half-wave rectifier.
Since the op-amp has high gain, a very small negative-going input is
sufficient to make D2 conduct. For this reason, this circuit is commonly
referred to as a precision half-wave rectifier.
A full-wave precision rectifier is formed by summing the input and
output voltages of the half-wave rectifier.
62
Precision full-wave rectifier.
COMPARATOR:
A comparator is a circuit that compares an input voltage with a reference
voltage. The output of the comparator then indicates whether the input
signal is either above or below the reference voltage. As shown for the
basic circuit in Fig. 5-1, the output voltage approaches the positive supply
voltage when the input signal is slightly greater than the reference
voltage, VREF. When the input is slightly less than the reference, the op-
amps output approaches the negative supply voltage. Consequently, the
exact threshold is dominated by the op-amps input offset voltage, which
should be nulled out.
The comparator.
63
Comparator limiting with a zener diode.
If the output voltage of the comparator is larger than required for a given
application, such an interfacing with 5-volt. TTL integrated circuits, the
output can be limited by a suitable zener diode, for lit ICs.
An inverting comparator.
ZERO CROSSING DETECTOR:
Zero-crossing is a commonly used term in electronics, mathematics, and
image processing. In mathematical terms, a "zero-crossing" is a point
where the sign of a function changes (e.g. from positive to negative),
represented by a crossing of the axis (zero value) in the graph of the
function.
64
SCHMITT TRIGGER:
A Schmitt trigger circuit is a fast-operating voltage-level detector. When
the input voltage arrives at the upper or lower trigger levels, the output
changes rapidly. The circuit operates with almost any type of input
waveform, and it gives a pulse-type output.
The circuit of an op-amp Schmitt trigger circuit is shown in figure. The
input voltage v
in
is applied to the inverting input terminal and the
feedback voltage goes to the non-inverting terminal. This means the
circuit uses positive voltage feedback instead of negative feedback, that
is, in this circuit feedback voltage aids the input voltage rather
than opposing it. For instance, assume the inverting input voltage to be
slightly positive. This will produce a negative output voltage. The voltage
divider feedsback a negative voltage to the non-inverting input, which
results in a larger negative voltage. This feedsback more negative voltage
until the circuit is driven into negative saturation. If the input voltage
were, slightly negative instead of positive, the circuit would be driven into
the positive saturation. This is the reason the circuit is also referred to as
regenerative comparator.
65
When the circuit is positively saturated, a positive voltage is fedback to
the non-inverting input. This positive input holds the output in the high
state. Similarly, when the output voltage is negatively saturated, negative
voltage is fedback to the non-inverting input, holding the output in the low
state. In either case, the positive feedback reinforces the existing output
state.
The feedback fraction, = R
2
/R
1
+ R
2
When the output is positively saturated, the reference voltage applied to
the non-inverting input is
V
ref

=

+
V
sat
When the output is negatively saturated, the reference voltage is
V
ref

=

-
V
sat
The output voltage will remain in a given state until the input voltage
exceeds the reference voltage for that state. For instance, if the output is
positively saturated, the reference voltage is + V
sat
. The input voltage v
in
must be increased slightly above + V
sat
to switch the output voltage
from positive to negative, as shown in figure. Once the output is in the
negative state, it will remain there indefinitely until the input voltage
becomes more negative than V
sat
. Then the output switches from
negative to positive. This can be explained from the input-output
characteristics of the Schmitt trigger shown in figure, as below.
66
Characteristics of the Schmitt trigger
Assume that input voltage v
in
is greater than the + V
sat
, and output
voltage v
OUT
is at its negative extreme (point 1). The voltage across R
2
in
the figure is a negative quantity.
As a result, v
in
must be reduced to this negative voltage level (point 2 on
the characteristics) before the output switches positively (point 3). If the
input voltage is made more negative than the V
sat
, the output remains
at + +v
OUT
(points 3 to 4). For the output to go negative once again, v
in
must be increased to the + V
sat
level (point 5 on the characteristics).
In figure, the trip points are defined as the two input voltages where the
output changes states. The upper trip point (abbreviated UTP) has a value
UTP = V
sat
and the lower trip point has a value
LTP = V
sat
The difference between the trip points is the hysteresis H and is given as
H = + V
sat
(- V
sat
) = 2 V
sat
The hysteresis is caused due to positive feedback. If there were no
positive feedback, would equal zero and the hysteresis would disappear,
because the trip points would both equal zero.
Hysteresis is desirable in a Schmitt trigger because it prevents noise form
causing false triggering.
To design a Schmitt trigger, potential divider current I
2
is once again
selected to be very much larger than the op-amp input bias current. Then
the resistor R
2
is calculated from equation
R
2
= UTP/I
2
and R
1
is determined from
R
1

=
(V
OUT
UTP) /
SAMPLE AND HOLD CIRCUIT:
In electronics, a sample and hold (S/H, also "follow-and-hold"
[1]
) circuit is
an analog device that samples (captures, grabs) the voltage of a
67
continuously varying analog signal and holds (locks, freezes) its value at a
constant level for a specified minimal period of time. Sample and hold
circuits and related peak detectors are the elementary analog memory
devices. They are typically used in analog-to-digital converters to
eliminate variations in input signal that can corrupt the conversion
process.
[2]
A typical sample and hold circuit stores electric charge in a capacitor and
contains at least one fast FET switch and at least one operational
amplifier.
[1]
To sample the input signal the switch connects the capacitor
to the output of a buffer amplifier. The buffer amplifier charges or
discharges the capacitor so that the voltage across the capacitor is
practically equal, or proportional to, input voltage. In hold mode the
switch disconnects the capacitor from the buffer. The capacitor is
invariably discharged by its own leakage currents and useful load
currents, which makes the circuit inherently volatile, but the loss of
voltage (voltage droop) within a specified hold time remains within an
acceptable error margin
68
For accurate analog to digital conversion the analog input voltage should
be held constant during the conversion cycle. If the analog input voltage
changes by more than t 1/2 LSB an error can occur in the digital output
code. To illustrate the effect of a changing analog input voltage on the
conversion processor, let us consider a situation of a successive
approximation ADC with an analog input that is initially zero, but there
happen to be a large change in voltage amplitude occurring during the
conversion process. Fig 5.2 shows the changing input voltage and its
effect on the successive approximation conversion process.
As shown in fig 5.2 analog input voltages at start of conversion process is
zero volts and at the end of conversion process it is near to 1.5 volts, and
the conversion process result is 010
2
, i.e. 2.5 V. This result does not
correspond to the analog voltage at the start of conversion or at the end
of conversion. To minimize the occurrence of these errors it is necessary
to hold the value of the analog input voltage constant during the
conversion process. The sample and hold circuit does this task.
As its name implies, the sample and hold (/H) circuit samples the
value of the input signal in response to a sampling command and hold it
at the output until arrival of the next command. It samples an analog
input voltage in a very short period, generally in the range of 1 to 10 s,
and holds the sampled voltage level for an extended period, which can
range from a few milliseconds to several seconds. Fig 5.3 shows input
and output response of the sample and hold circuit.
69
Fig 5.3 input and output response of sample and hold circuit
The sample and hold circuit uses to basic components analog switch
and capacitor. The fig 5.4 shows the basic sample and hold circuit.
70
Fig 5.4 principle diagram for sample and hold circuit
The circuit tracks the analog signal until the sample command causes the
digital switch to isolate the capacitor from the signal, and the capacitor
holds this analog voltage during A/D conversion.
CLIPPERS AND CLAMPERS:
CLIPPERS:
Clipper is a circuit that is used to clip off (remove) a certain portion
of the input signal to obtain a desired output wave shape. In op-amp
clipper circuits, a rectified diode may be used to clip off certain parts of
the input signal. Fig. 2-2-4 (a) shows an active positive clipper, a circuit
that removes positive parts of the input signal. The clipping level is
determined by the reference voltage
With the wiper all the way to the left, V
ref
is o and the non-inverting input
is grounded. When V
in
goes positive, the error voltage drives the op-amp
output negative and turns on the diode. This means the final output V
O
is
0 (same as V
ref
) for any positive value of V
in
.
When V
in
goes negative, the op-amp output is positive, which turns
off the diode and opens the loop. When this happens, the final output V
O
is
free to follow the negative half cycle of the input voltage. This is why the
negative half cycle appears at the output. To change the clipping level, all
we do is adjust V
ref
as needed.
71
CLAMPERS:
A clamper is an electronic circuit that prevents a signal from exceeding a
certain defined magnitude by shifting its DC value. The clamper does not
restrict the peak-to-peak excursion of the signal, but moves it up or down
by a fixed value. A diode clamp (a simple, common type) relies on a diode,
which conducts electric current in only one direction; resistors and
capacitors in the circuit are used to maintain an altered dc level at the
clamper output
In clamper circuits, a predetermined dc level is added to the input voltage.
In other words, the output is clamped to a desired dc level. If the clamped
dc level is positive, the clamper is called a positive clamper. On the other
hand, if the clamped dc level is negative, it is called a negative clamper.
72
The other equivalent terms for clamper are dc inserter or dc restorer.
A clamper circuit with a variable dc level is shown in fig. 2-2-5 (a).
Here the input wave form is clamped at +V
ref
and hence the circuit is
called a positive clamper.
1uF
C1
Vo
R
1
R
4 +
Fig 2-2-5(a) Peak clamper circuit
The output voltage of the clamper is a net result of ac and dc input
voltages applied to the inverting and non-inverting input terminals
respectively. Therefore, to understand the circuit operation, each input
must be considered separately. First, consider V
ref
at the non-inverting
input. Since this voltage is positive, is +V
O
is positive, which forward
biases diode D1. This closes the feedback loop and the op-amp operates
as a voltage follower. This is possible because C
1
is an open circuit for dc
voltage. Therefore V
O
= V
ref
. As for as voltage V
in
at the inverting input is
concerned during its negative half-cycle D1 conducts, charging C
1
to the
negative peak value of the V
P
. However, during the positive half-cycle of
V
in
diode D1 is reverse biased and hence the voltage V
P
across the
capacitor acquired during the negative half-cycle is retained. Since this
voltage V
P
is in series with the positive peak voltage V
P
, the output peak
voltage V
O
=2V
P
. Thus the net output is V
ref
+V
P
, so the negative peak of 2V
P
is at V
ref
. For precision clamping C
1
R
d
<<T/2, where R
d
is the forward
resistance of the diode D1 (100 typically) and T is the time period of V
in
.
The input and output wave forms are shown in fig. 2-2-5(b)
73
A/D AND D/A CONVERTERS:
A/D:

Figure: symbol for 4 bit ADC
The A/D conversion is a quantizing process whereby an analog signal is
converted into equivalent binary word. Thus the A/D converter is exactly
opposite function that of the D/A converter.
Performance parameters of ADC
The fig 5.26 shows the digital output of an ideal 3 bit ADC plotted against
the analog input voltage.
74

b
0
b
1
b
2
b
3
ADC
Analog
input
Let us define the performance parameters of ADC, referring to the fig
5.26, which shows the output input characteristics of ADC
Resolution
Fig 5.26 shows eight (2
3
) discrete output states from 000
2
to 111
2
, each
step being
1
8
V apart. Therefore, we can say that expression of ADC
resolution is the same as for the DAC and is repeated here:
Resolution = 2
n
Resolution is also defined as the ratio of a change in value of input
voltage, V
i
, needed to change the digital output by 1 LSB. If the full scale
input voltage required to cause a digital output of all 1s is V
iFS
, then
resolution can be given as
Resolution =
iFS
n
V
2 -1
Quantization Error
Fig 5.26 shows that the binary output is 011 for all values of V
i
between
1/4 and 1/2 V. There is an unavoidable uncertainty about the exact value
of V
i
when the output is 011. This uncertainty is specified as quantization
error. Its value is t
1
2
LSB.
It is given as, Q
E
=
iFS
n
V
(2 - 1)2
75
Increasing the number of bits results in a finear resolution and a smaller
quantization error.
The quantization error can be observed by continuously sampling a
time varying analog signal with an ADC, converting it back to analog
with a DAC, and taking the difference between the two. The resulting
sawtooth like signal, called quantization noise.
The root mean square value of such signal, E
n
can be given as
E
n
=
FS
n
V
2 12
This is related to the resolution of the system. For each additional bit of
resolution E
n
is cut in half, that is reduced by 6 dB.
Conversion time
It is an important parameter for ADC. It is defined as the total time
required to convert an analog signal into its digital output. It depends on
the conversion technique used and the propagation delay of circuit
components.
D/A:
A DAC (Digital to Analog Converter) accepts an n bit input word b
1
, b
2
, b
3
.b
a
in binary and produce an analog signal proportional to it. Fig 5.11
shows circuit symbol and input output characteristics of a 4 bit DAC.
There are four digital inputs, indicating 4 bit DAC. Each digital input
requires an electrical signal representing either a logic 1 or a logic 0. The
b
n
is the least significant bit, LSB, whereas b
1
is the most significant bit,
MSB.
Figure: (a) DAC circuit symbol
76
Figure: (b) shows analog output voltage V
0
is plotted against all
16 possible digital input words.
Performance parameters of DAC
The various performance parameters of DAC are,
Resolution
Resolution is defined in two ways
Resolution is the number of different analog output values that can
be provided by a DAC. For an n bit DAC resolution =2
n
Resolution in also defined as the ratio of a change in output voltage
resulting from a change of 1 LSB at the digital inputs. For an n bit
DAC it can be given as
Resolution =
oFS
n
V
2 - 1
Where, V
0FS
= Full scale output voltage
From equation 5.4, we can say that, the resolution can be determined
by the number of bits in the input binary word. For an 8 bit DAC
resolution can be given as
Resolution = 2
n
2
n
= 256
If the full scale output voltage is 10.2 V then by second definition
the resolution for an 8 bit DAC can be given as
Resolution =
oFS
n 8
V 10.2 10.2
2 - 1 2 - 1 255

= 40 mV/LSB
Therefore, we can say that an input change of 1 LSB causes the
77
output to change by 40 mV
From the resolution, we can obtain the input output equation for a DAC
Thus V
0
= resolution D
Where D = decimal value of the digital input
And V
0
= output voltage
The resolution takes care of changes in the input.
Accuracy
It is a comparison of actual output voltage with expected output. It is
expressed in percentage. Ideally, the accuracy of DAC should be, at
worst, t 1/2 of its LSB. If the full scale output voltage is 10.2 V then for an
8 bit DAC accuracy can be given as
Accuracy =
oFS
n
V
(2 -1) 2
=
10.2
20 mV
255 2

Monotonicity
A converter is said to have good monotonicity if it does not miss any step
backward when stepped through its entire range by a counter.
Conversion time
It is a time required for conversion of analog signal into its digital
equivalent. It is also called as setting time. It depends on the response
time of the switches and the output of the amplifier.
Setting time
This is the time required for the output of the DAC to within t 1/2 LSB of
the final value for a given digital input i.e. zero to full scale.
Stability
The performance of converter changes with temperature, age and power
supply variations. So all the relevant parameters such as offset, gain,
linearity error and monotonicity must be specified over full temperature
and power supply ranges. These parameters represent the stability of the
converter.
78
UNIT III
ACTIVE FILTERS AND OSCILLATORS
SECOND ORDER ACTIVE FILTER
An improved filter response can be obtained by using a second
order active filter. A second order filter consists of two RC pairs and has a
roll-off rate of -40 dB/decade. A general second order filter (Sallen-Key
filter) is shown in figure. The results derived here can be used for
analyzing low pass and high pass filters.
Figure: Sallen Key filter (General second order filter)
The op-amp is connected as non-inverting amplifier and hence,

1 ....(1)
f
o B o B
i
R
V v A v
R
_
+

,
Where
+ 1 ....(2)
f
o
i
R
A
R
and v
B
is the voltage at node B.
Kirchhoffs current law (KCL) at node A gives
v
i
Y
1
= v
A
(Y
1
+ Y
2
+Y
3
) v
o
Y
3
v
B
Y
2
79
= v
A
(Y
1
+ Y
2
+ Y
3
) v
o
Y
3
-
2 o
o
v Y
A
....(3)
Where v
A
is the voltage at node A.
KCL at node B gives,
( )
( )
( )
2 4
2 2 4
o 2 4
A
2
v
v = .....(4)
o
A B
o
o
v Y Y
v Y v Y Y
A
Y Y
A Y
+
+
+
Substituting Equation (4) in Equation (3) and after simplification, we get
the voltage gain as
( ) ( )
1 2
1 2 4 1 2 3 2 3
....(5)
1
o o
i o
v A YY
v YY Y Y Y Y Y Y A
+ + + +
To make a low pass filter, choose, Y
1
= Y
2
= 1 / R and Y
3
= Y
4
= sC as
shown in figure. For simplicity, equal components have been used. From
Equation (5), we get the transfer function H(s) of a low pass filter as,
( )
( )
2 2 2
....(6)
3 1
o
o
A
H s
s C R sCR A
+ +
This is to note that from Equation (6), H(0) = A
o
for s = 0 and H() = 0 for
s = and obviously the configuration is for low pass active filter. It may
be noted that for minimum dc offset R
i
R
f
/ (R
f
+ R
i
) = R + R = 2R should
be satisfied.
Second order physical systems have been studied extensively since
long back and their step response, damping coefficient and its cause and
effect relationship are known. We shall exploit those ideas in case of
80
second order RC active filter. The transfer function of low pass second
order system (electrical, mechanical, hydraulic or chemical) can be
written as,
( )
2
2 2
h
o h
h
A
H s
s s
+ +
....(7)
where A
o
= the gain
h
= upper cut-off frequency in radians / second
= damping coefficient
Comparing Equation (6) and Equation (7) we get,
1
h
RC

....(8)
( )
3
o
A
....(9)
That is, the value of the damping coefficient for low pass active RC filter
can be determined by the value of A
o
chosen.
Putting s = j in Equation (7) we get
( )
( ) ( )
2
H j
/ / 1
o
h h
A
j j
+ +
......(10)
The normalized expression for low pass filter is
( )
2
...(11)
1
o
A
H jw
s s
+ +
where normalized frequency
h
s j

,
( )
( ) ( )
o
2
o
2 2
2
2
A
20 log H j 20 log
1 / /
A
= 20 log
1
h h
h h
h j
+ +
_

_ _
+

, ,
,
....(12)
81
The frequency response for different values of is shown in figure.
It may be seen that for a heavily damped filter ( > 1.7), the response is
stable. However, the roll-off begins very early to the pass band. As is
reduced, the response exhibits overshoot and ripple begins to appear at
the early stage of pass band. If is reduced too much, the filter may
become oscillatory. The flattest pass band occurs for damping coefficient
of 1.414. This is called a Butterworth filter. Audio filters are usually
Butterworth. The chebyshev filters are more lightly damped, that is, the
damping coefficient is 1.06. However, this increases overshoot and
ringing occurs deteriorating the pulse response. The advantage, however,
is a faster initial roll-off compared to Butterworth. A Bessel filter is heavily
damped and has a damping coefficient of 1.73. This gives better pulse
response, however, causes attenuation in the upper end of the pass band.
We shall discuss only Butterworth filter in this text as it has
maximally flat response with damping coefficient = 1.414. From
Equation (12), with = 1.414, we get
( )
o o
4
1
V A
20 log H j 20 log 20 log
1
h
V

_
+

,
.....(13)
Hence for n-th order generalized low-pass Butterworth filter, the
normalized transfer function for maximally flat filter can be written as
82
( )
2
1
1
n
o
h
H jw
A
_
+

,
....(14)
BUTTERWORTH FILTERS:
The Butterworth filter is a type of signal processing filter designed to have
as flat a frequency response as possible in the passband so that it is also
termed a maximally flat magnitude filter. It was first described by the
British engineer Stephen Butterworth in his paper entitled "On the Theory
of Filter Amplifiers".
[
BAND-PASS FILTERS:
The design of band pass filters can become very involved even when
using operational amplifiers. However it is possible to simplify the design
equations while still being able to retain an acceptable level of
performance of the operational amplifier filter for many applications.
Circuit of the operational amplifier active band pass filter
83
As only one operational amplifier is used in the filter circuit, the gain
should be limited to five or less, and the Q to less than ten. In order to
improve the shape factor of the operational amplifier filter one or more
stages can be cascaded. A final point to note is that high stability and
tolerance components should be used for both the resistors and the
capacitors. In this way the performance of the operational amplifier filter
will be obtained.
WIDE BAND PASS FILTER:
Wide Band pass filter is one special type of Band pass filter. This wide
Band pass filter has its Q factor (figure of merit) to be less than 10
Q <10
Where
H L
L
c
.
fc= center frequency
B.W=Bandwidth
fc
Q=
f -f
cut off frequency
F cut off frequency
f
H
H L
fc
Q
BW
f high
Low
f f
A wide Band pass filter can be formed by simply cascading high pass and
84
low pass sections and is generally the choice for simplicity of design and
performance.
To obtain a t 20dB decode band pass we can cascade a first order high
pass filter and first order low pass filter. To obtain t 40dB roll off we can
use second order low pass and high pass filter.
To realize a Band pass response, however f
H
must be larger than f
L
NARROW BAND PASS:
The narrow band pass filter using multiple feedback is shown below. As
85
shown in figure the filter uses only one op-amp compared to all the filters
this narrow band filter is unique in the following aspects.
1. It has two feedback paths hence the name multiple feedback filter.
2. The op-amp is used in inverting mode.
Generally the narrow band pass filter is designed for a specific values of
center frequency fc and Q or fc and bandwidth. The circuit components
are determined from the following relationships.
To simplify the design calculations choose C
1
= C
2
= C
1
2 2
3
2
2 (2 )
f
Q
R
fccA
Q
R
fc Q Af
Q
R
fcC
Where A
f
is the gain at F
c
given by
3
1
2
F
R
A
R
The gain A
f
however must satisfy the condition
A
f
< 2 Q
2
Another advantage of the multiple feedback filter is that its centre
frequency fc can be changed to a new frequency f
c
1
without changing gain
or bandwidth. This is accomplished simply by changing R
2
to R
2
1
so that
86
2
1
2 2
fc
R R
fc
_

,
BAND REJECT FILTER:

Also called band-elimination, band-reject, or notch filters, this kind of filter
passes all frequencies above and below a particular range set by the
component values. Not surprisingly, it can be made out of a low-pass and
a high-pass filter, just like the band-pass design, except that this time we
connect the two filter sections in parallel with each other instead of in
series.
ALL PASS FILTER:
An all-pass filter is a signal processing filter that passes all frequencies
equally, but changes the phase relationship between various frequencies.
It does this by varying its propagation delay with frequency. Generally, the
filter is described by the frequency at which the phase shift crosses 90
(i.e., when the input and output signals go into quadrature when there
is a quarter wavelength of delay between them).
They are generally used to compensate for other undesired phase shifts
that arise in the system, or for mixing with an unshifted version of the
original to implement a notch comb filter. They may also be used to
convert a mixed phase filter into a minimum phase filter with an
equivalent magnitude response or an unstable filter into a stable filter
with an equivalent magnitude response.
87
OSCILLATORS AND WAVE GENERATORS:
Introduction:
The 555 timer is a highly stable device for generating accurate time
delay or oscillation. Signetics Corporation first introduced this device as
the SE555 / NE555 and it is available in two packages styles, 8 pin
circular style. TO -99 can or 8 pin mini DIP or as 14 pin DIP. The 556
timer contains two 555 timers and is a 14 pin DIP. The 556 timer
contains two 555 timers and is a 14 pin DIP. There is also available
counter timer such as Exars XR 2240 which contains a 555 timer plus a
programmable binary counter in a single 16 pin package. A single 555
timer can provide time delay ranging from microseconds to hours whereas
counter timer can have a maximum timing range of days.
The 555 timer can be used with supply voltage in the range of + 5V
to 18 V and can drive load upto 200 mA. It is compatible with both TTL
88
8
V
CC
7
Discharge
6 Threshold
5 Control voltage
1 Ground
2
Trigger
3
Output
4
Reset
555
8 pin
diagram
and CMOS logic circuits. Because of the wide range of supply voltage, the
555 timer is versatile and easy to use in various applications. Various
applications include oscillator, pulse generator, ramp and square wave
generator, mono shot multivibrator, burglar alarm, traffic light control
and voltage monitor etc.
Description of Functional Diagram
Figure 8.1 gives the pin diagram and Fig. 8.2 gives the functional
diagram for 555 IC timer. Referring to Fig. 8.2, three 5 k internal
resistors act as voltage divider, providing bias voltage of (2/3) V
CC
to the
upper comparator (CU) and (1/3) V
CC
to the lower comparator (LC), where
V
CC
is the supply voltage. Since these two voltages fix the necessary
comparator threshold voltage, they also aid in determining the timing
interval. It is possible to vary time electronically too, by applying a
modulation voltage to the control voltage input terminal (pin 5). In
applications, where no such modulation is intended, it is recommended by
manufacturers that a capacitor (0.01 F) be connected between control
voltage terminal (pin 5) and ground to by pass noise or ripple from the
supply.
In the standby (stable) state, the output
Q
of the control flip flop (FF) is
(HIGH). This makes the output LOW because of power amplifier which is
basically an inverter. A negative going trigger pulse is applied to pin 2 and
should have its dc level greater than the threshold level of the lower
comparator (i.e. V
CC
/3). At the negative going edge of the trigger, as the
trigger passes through (V
CC
/ 3), the output of the lower comparator goes
HIGH and sets the FF (Q = 1,
Q
=0 ). During the positive excursion, when
the threshold voltage at pin 6 passes through (2 /3) V
CC
, the output of the
upper comparator goes HIGH and resets the FF (Q = 0,
Q
= 1).The reset
input (pin 4) provides a mechanism to reset the FF in a manner which
89
overrides the effect of any instruction coming to FF from lower
comparator. This overriding reset is effective when the reset input is less
than about 0.4 V. when this reset is not used, it is returned to V
CC
. The
transistor Q
2
serves as a buffer to isolate the reset input from the FF and
transistor Q
1
. The transistor Q
2
is driven by an internal reference voltage
V
ref
obtained from supply voltage V
CC
.
PHASE SHIFT OSCILLATOR:
RC-phase shift oscillator circuit is shown below. The circuit consists of an
op-amp as the amplifying stage and three RC- cascaded networks as the
feedback circuit. The feedback circuit provides feedback voltage from the
output back to the input of the amplifier.
The op-amp is used in the inverting mode, therefore any signal that
appears at the inverting terminal is shifted by 180 at the output. An
additional 180 phase shift required for oscillation is provided by the
cascaded RC networks. Thus the total phase shift around the loop is
360/ or 0 A
1
some specific frequency when the phase shift of the
cascaded RC networks is exactly 180 and the gain of the amplifier is
sufficiently large the circuit will osculate at that frequency.
The frequency is called the frequency of oscillation
0
1 0.065
6
f
RC RC

At this frequency the gain Av must be at least 29. That is
90
1
1
29
29
F
F
R
R
R R
Thus the circuit will produce a sinusoidal waveform of frequency fo. If the
gain is 29 and the total phase shift around the circuit is exactly 360
For a desired frequency of oscillation choose a capacitor C and then
calculate the value of R A desired output amplitude can be obtained by
using a back to back zener diodes.
WIEN BRIDGE OSCILLATOR:
One of the most widely used audio frequency oscillator is the wein bridge
oscillator because of its simplicity and stability.
The condition of zero phase shifts is achieved by balancing the bridge
Form feedback network, the feed back network is
91
0
(1 )
( / )
(1 )
1
3 ( )
f
R
V
jwRc
V
R
R i wc
jwRc
R
R i w iwrc
wc
1
+
+ 1
]
+ + +
must be near for AU =1. therefore the imaginary term must be zero.
2
1
0 R C
c

1
w
Rc

frequency of oscillation fo =
1
2 Rc
using this value of becomes
3
1
3
R
R

Therefore for sustained oscillation the amplifier must have a gain of
precisely 3
Practically Av must b e slightly less or greater than 3.
For A <3 the oscillation will either die down or fail to start when power is
applied.
For AV>3 the oscillation grows.
These problems are removed in the practical wein bridge oscillator with a
negative feedback.
VOLTAGE-CONTROLLED OSCILLATOR(VCO):
VCO Voltage Controlled Oscillator
A Voltage controlled oscillator is an Oscillator circuit in which the
frequency of oscillation is controlled by externally applied voltage. The
VCO provides the linear relationship between the applied voltage and the
oscillation frequency. The Applied voltage is said to be control. Since the
frequency is controlled by the control voltage. The voltage controlled
oscillator is also called as voltage to frequency conversion (converter).
92
V
in
C(t) = N or or
(Control voltage) with frequency (f
0
)
The transfer function K0 for such a device has the units of radians per
volt (rad IV) and represents how much frequency shift occurs for a given
change in control voltage. VCOs can be placed in one of the two
categories: Multivibrators (VCMs) and LC oscillators (VCOs). VCMs
provide the simplest and most straight forward solution.
Various applications of VCO.
Frequency Modulation
Signal generation
Frequency shift keying modulators
In frequency multipliers
Converting low frequency signals such as ECG and EEG in to audio
frequency range signals.
Tone generation.
features of IC566.
IC566 is a monolithic voltage controlled oscillator. Which is most
commonly used in many applications Pin configuration
The figure above shows the pin diagram of NE/SE 566 VCO manufactured
by signetics. It is a 8 pin dual in package IC
Pins (1) and (8) form the supply voltage for the IC.
Pin (3) and (4) are the two output pins in which pin (3) provides
square wave signal and pin (4) provides a Triangular wave signal.
Pin (5) is the input pin where the control voltage is provided from
External source.
Pin (6) and (7) can be used to connect Resistor and capacitor
externally to vary the center frequency of oscillation.
Features of IC 566:-
93
Wide supply voltage range from 10V to 24V
Very Linear modulation characteristics
High Temperature stability.
Excellent power supply rejection
Very wide variation of frequency with fixed C
The frequency can be controlled by means of current, voltage,
resistor or capacitor.
The block diagram of IC566 is show below. It consists of the following
components namely.
Constant current source circuit.
Buffer amplifier
Schmitt Trigger.
Inverter.
Operation:
The op-amp A1 is used as a buffer. The op-amp A2 is used as a Schmitt
trigger and the op-amp A3 is used as an Inverter. The voltage V
c
is
applied to the modulation input pin which is a control voltage. The
capacitor C
1
is linearly charged or discharged by a constant current
source. The charging current can be controlled by controlling the voltage
V
c
at the pin(5) or by varying he resistance R that is external to the IC.
The Schmitt trigger determines the charging and discharging levels. The
output voltage of the Schmitt trigger is designed to swing between +v and
0.5V.
For Ra = Rb, the voltage at the non-inverting terminal swings between
0.5v to 0.25V. Thus the triangular wave is generated due to alternate
94
charging and discharging. When the C voltage becomes less than 0.25 V
the output of the Schmitt trigger goes high. Due to similar current source
is used for charging and discharging, the time taken by C
1
to charge and
discharge is same. This produces the exact triangular wave. The output of
the Schmitt trigger output is step response which is available at pin 3 as
square wave output. Various wave forms are shown below
The frequency of the output wave form is dependent on R
1

0
1 1 0
2( ) 1
( )
cc c
cc
V V
f
RC V T
Connection diagram of IC 566 and derive the frequency of

oscillation.
A typical connection diagram of IC 566 to function as a voltage
controlled oscillator is given below.
95
Practically the modulating input voltage at the pin 5 is controlled using
a potential divider formed by the resistances R
2
and R
3
. The modulating
input is connected through capacitor coupling to the pin(5) and it must be
less than 3V(P-P). for a fixed Vc and C
1
the frequency can be varied in
the range 10:1 by varying the R
1
between 2K to 20k . for fixed R
1
&C
1
the frequency can be varied in the range 10:1 by varying control voltage
VC. In both the cases maximum possible output frequency is 1MH3. The
capacitor C
2
connected between pins 5 and 6 is used to eliminate any
oscillations present in constant current source.
The output frequency can be calculated as follows the total voltage on the
capacitor changes from 0.25 V
CC
to 0.5 V
CC.
Since the capacitor charges through constant current source
1
sin V value we get
V i
t C
u g
CC
1
1
0.25V
0.25 ( )

CC
i
t C
V C
t
i
The total time period T = 2 t
96
1
1
1
1
0
1 1
1 1
2 0.5 C
( ) /
( /
0.5 C
of oscillotion f
0.5
o
CC
cc c
cc c
o
CC
CC C
CC
i
f
T t V
but i V V R
V V R
f
V
V V
frequency
V RC

SQUARE WAVE GENERATOR:

Figure 1. Square Wave Generator Circuit Diagram

This is a square wave generator circuit. The main component of
this circuit is the 741, a general-purpose operational amplifier. This
circuit employs a single power supply Vs that can range from +5V to
+15V.

The square wave output of this circuit is easy to adjust. 'Timing' is
defined by C1, R4, R5, R6, and R7 while duration is defined by R1, R2,
and R3. Pulse symmetry is achieved by making the resistance from pin
3 to ground equal to the resistance from pin 3 to Vs. If this is desired,
then R1, R2, and R3 may simply be replaced by two equal resistors
from pin 3, one of which is tied to Vs while the other is tied to ground.
97
TRIANGULAR WAVE GENERATOR:
Suppose our design calls for a +/-10 V triangle wave, cruising along at 10
kHz. This means that Vth+ = +10 V and Vth- = -10 V. Given VP = +5 V,
VN = -5 V, let's choose R2 = 10 k and then calculate R1 = 20 k from
the equation above.
Now, if you have a 1 nF cap in stock, then what value of RI is needed for
10 kHz (T = 100 s)? Because Vo needs to swing Vo = 10 - (-10) = 20 V
in an interval T = 50 s, we solve the above equation in the Linear
Ramps section for RI.
RI = (VP / CI ) (T / Vo)
= (5 V / 1 nF) (50 s / 20 V)
= 12.5 k
Want to speed up or slow down the action? Just change the current source
level by doubling or halving RI. Run a new simulation and watch it go.
Need a different peak to peak voltage swing? Simply raise or lower R1.
But beware - changing the voltage thresholds also changes the time
required to reach the thresholds. Also, make sure Vth+ and Vth- are not
outside the +/-15V limits of the op amp model!
And don't forget the option of changing the reverse voltage of the zener
diode via the BV parameter. Just remember the charging currents and
thresholds will change too.
SAW-TOOTH WAVE GENERATOR:
Sawtooth wave generators using opamp are very common. But the
disadvantage is that it requires a bipolar power supply. A sawtooth wave
generator can be built using a simple 555 timer IC and a transistor as
shown in the circuit diagram.
98
The working of the circuit can be explained as follows:
The part of the circuit consisting of the capacitor C, transistor,zener diode
and the resistors form a constant current source to charge the capacitor.
Initially assume the capacitor is fully discharged. The voltage across it is
zero and hence the internal comparators inside the 555 connected to pin
2 causes the 555's output to go high and the internal transistor of 555
shorting the capacitor C to ground opens and the capacitor starts charging
to the supply voltage. As it charges, when its voltage increases above
2/3rd the supply voltage, the 555's output goes low, and shorts the C to
ground, thus discharging it. Again the 555's output goes high when the
voltage across C decreases below 1/3rd supply. Hence the capacitor
charges and discharges between 2/3rd and 1/3rd supply.
Note that the output is taken across the capacitor. The 1N4001 diode
makes the voltage across the capacitor go to ground level (almost).
The frequency of the circuit is given by:
f = (Vcc-2.7)/(R*C*Vpp)
where:
Vcc= Supply voltage.
Vpp= Peak to peak voltage of the output required.
99
Choose proper R,C,Vpp and Vcc values to get the required 'f' value.
UNIT IV
PLL AND TIMER ICS
PLL phase locked loops
The figure below shows the phase locked loop in its basic form
100
As shown in the figure, PLL consists of
i) The phase detector
ii) Low pass filter
iii) Error amplifier
iv) V.C.O
The phase detector, or Comparator compares the input frequency fin
and the output frequency f
0
. The output of the phase detector is
proportional to the phase difference between fin and f
out
. The output
voltage of a phase detector is a dc voltage and is often referred to as
error voltage. The output of the phase detector is then applied to the low
pass filter which removes the high frequency noise and produces a dc
level. This dc voltage is amplified by the error amplifier before given as
input to the VCO. The filter also helps in establishing the dynamic
characters of the PLL. The output frequency of the VCO is directly
proportional to the input dc level. The VCO frequency is compared with
the input frequency and adjusted until it is equal to the input frequencies.
In short the phase located loop goes through three states
(i) Free running stale
(ii) Capture
(iii) Phase lock
Before the input is applied the phase locked loop is said to be in free
running state.
Once the input is applied, the voltage controlled oscillator starts to
change and at this point the phase locked loop is said to be capture.
The VCO frequency continuous to change until it equals the input
frequency, and the phase locked loop is then in the lock state.
When phase locked, the loop tracks any change in the input
frequency through its respective action.
CLOSED LOOP ANALYSIS OF PLL:
101
A phase-locked loop or phase lock loop (PLL) is a control system that tries
to generate an output signal whose phase is related to the phase of the
input "reference" signal. It is an electronic circuit consisting of a variable
frequency oscillator and a phase detector that compares the phase of the
signal derived from the oscillator to an input signal. The signal from the
phase detector is used to control the oscillator in a feedback loop. The
circuit compares the phase of the input signal with the phase of a signal
derived from its output oscillator and adjusts the frequency of its oscillator
to keep the phases matched.
Frequency is the derivative of phase. Keeping the input and output phase
in lock step implies keeping the input and output frequencies in lock step.
Consequently, a phase-locked loop can track an input frequency, or it can
generate a frequency that is a multiple of the input frequency. The former
property is used for demodulation, and the latter property is used for
indirect frequency synthesis.
Phase-locked loops are widely used in radio, telecommunications,
computers and other electronic applications. They may generate stable
frequencies, recover a signal from a noisy communication channel, or
distribute clock timing pulses in digital logic designs such as
microprocessors. Since a single integrated circuit can provide a complete
phase-locked-loop building block, the technique is widely used in modern
electronic devices, with output frequencies from a fraction of a hertz up to
many gigahertz.
PHASE DETECTORS:
The two inputs of the phase detector are the reference input and the
feedback from the voltage controlled oscillator (VCO). The PD output
controls the VCO such that the phase difference between the two inputs is
held constant, making it a negative feedback system. There are several
types of phase detectors in the two main categories of analog and digital.
Different types of phase detectors have different performance
characteristics.
For instance, the frequency mixer produces harmonics that adds
complexity in applications where spectral purity of the VCO signal is
important. The resulting unwanted (spurious) sidebands, also called
"reference spurs" can dominate the filter requirements and reduce the
capture range and lock time well below the requirements. In these
applications the more complex digital phase detectors are used which do
102
not have as severe a reference spur component on their output. Also,
when in lock, the steady-state phase difference at the inputs using this
type of phase detector is near 90 degrees. The actual difference is
determined by the DC loop gain.
A bang-bang charge pump phase detector must always have a dead band
where the phases of inputs are close enough that the detector detects no
phase error. For this reason, bang-bang phase detectors are associated
with significant minimum peak-to-peak jitter, because of drift within the
dead band.
[citation needed]
However these types, having outputs consisting of
very narrow pulses at lock, are very useful for applications requiring very
low VCO spurious outputs. The narrow pulses contain very little energy
and are easy to filter out of the VCO control voltage. This results in low
VCO control line ripple and therefore low FM sidebands on the VCO.
In PLL applications it is frequently required to know when the loop is out of
lock. The more complex digital phase-frequency detectors usually have an
output that allows a reliable indication of an out of lock condition.
ANALOG MULTIPLIERS:
In Analog. A multiplier is an active network the output of which is
proportional to the product of the two input signals. A general
representation of multiplier is shown below
X
Y Z=K.XY
Where x, y input signals, Z output
K Multiplier scale factor
The multiplier Integrated circuits are most commonly used in
practice. Monolithic Integration has lowered the cost of multiplier ICs
considerably. Such an IC is not only useful as multiplier but can be used as
a simple and direct solution to complex signal processing problems. Such
ICs can be used as a simple and direct solution to complex signal
processing problems. Such ICs can be configured to use in many
applications as signal multiplications in process instrumentation, chemical
analyzers, servo mechanism control systems, frequency doublers, phase
angle defectors, true R.M.S converter and so-on. The ICs can be used to
improve the data acquisition through rationing two signals.
103
X
A Basic Multiplier is an active circuit in which the output voltage is
proportional to the product of the two input signals. A schematic symbol
of such a basic multiplier IC is shown below
The V+ and V- are supply terminals for the IC. Where dual supply is to
be connected. The X and Y are the two input terminals where two
inputs V
1
and V
2
are connected.
The output of such basic multiplier is
V
o
= K (V
1
V
2
).
As long as it is ensured that both the input voltages are below the
reference voltage.
(V
1
V
2
< V
ret
)
The output of the basic multiplier will not saturate Depending on the use
of the basic multiplier, it is necessary to restrict the polarity of one or both
the inputs.
Depending upon the polarity restriction, the IC operation is called as
i) One Quadrant Multiplier:-
In such operation, the polarities of both the inputs must always be
positive
ii) Two Quadrant Multiplier:-
IC functions properly if one input is held positive and the other is
allowed to swing in both positive and negative.
iii) Four Quadrant Multiplier:-
If both the inputs are allowed to swing in both positive and negative
directions, the operation is four quadrant Multiplier.
The following are the major Techniques used for providing multiplier IC.
104
Logarithmic Multipliers
Quarter square Multipliers
Pulse width / Height modulation Multipliers
Variable Transconductance Multipliers
Current rating Multipliers
Triangle averaging multipliers.
Out of these techniques logarithmic, pulse modulation and variable
Transconductance are best suitable for monolithic IC realization of the
multipliers. Compared to the above Techniques Variable Trans
conductance technique has many advantages and hence most commonly
used for IC.
The advantages of variable Transconductance multiplier technique are
Simple to integrate in to Monolithic IC
Provides very good accuracy
Very cheap hence economical.
Provides four quadrant operation
It provides high speed operation atleast 2 or 3 times faster
than logarithmic
Reduced error in both Accuracy wise and linearity wise
Variety of Bandwidth ranges can be formed starting from
10MHz.
Reduced feed through voltage.
APPLICATIONS USING PLL:
Phase-locked loops are widely used for synchronization purposes; in space
communications for coherent demodulation and threshold
[disambiguation needed]
extension, bit synchronization, and symbol synchronization. Phase-locked
loops can also be used to demodulate frequency-modulated signals. In
radio transmitters, a PLL is used to synthesize new frequencies which are
a multiple of a reference frequency, with the same stability as the
reference frequency.
Other applications include:
Demodulation of both FM and AM signals
Recovery of small signals that otherwise would be lost in noise (lock-
in amplifier)
Recovery of clock timing information from a data stream such as
from a disk drive
105
Clock multipliers in microprocessors that allow internal processor
elements to run faster than external connections, while maintaining
precise timing relationships
DTMF decoders, modems, and other tone decoders, for remote
control and telecommunications
Clock recovery
Some data streams, especially high-speed serial data streams (such as
the raw stream of data from the magnetic head of a disk drive), are sent
without an accompanying clock. The receiver generates a clock from an
approximate frequency reference, and then phase-aligns to the transitions
in the data stream with a PLL. This process is referred to as clock
recovery. In order for this scheme to work, the data stream must have a
transition frequently enough to correct any drift in the PLL's oscillator.
Typically, some sort of redundant encoding is used; 8B10B is very
common.
Deskewing
If a clock is sent in parallel with data, that clock can be used to sample the
data. Because the clock must be received and amplified before it can
drive the flip-flops which sample the data, there will be a finite, and
process-, temperature-, and voltage-dependent delay between the
detected clock edge and the received data window. This delay limits the
frequency at which data can be sent. One way of eliminating this delay is
to include a deskew PLL on the receive side, so that the clock at each data
flip-flop is phase-matched to the received clock. In that type of
application, a special form of a PLL called a delay-locked loop (DLL) is
frequently used.
[10]
Clock generation
Many electronic systems include processors of various sorts that operate
at hundreds of megahertz. Typically, the clocks supplied to these
processors come from clock generator PLLs, which multiply a lower-
frequency reference clock (usually 50 or 100 MHz) up to the operating
frequency of the processor. The multiplication factor can be quite large in
cases where the operating frequency is multiple gigahertz and the
reference crystal is just tens or hundreds of megahertz.
106
Spread spectrum
All electronic systems emit some unwanted radio frequency energy.
Various regulatory agencies (such as the FCC in the United States) put
limits on the emitted energy and any interference caused by it. The
emitted noise generally appears at sharp spectral peaks (usually at the
operating frequency of the device, and a few harmonics). A system
designer can use a spread-spectrum PLL to reduce interference with high-
Q receivers by spreading the energy over a larger portion of the spectrum.
For example, by changing the operating frequency up and down by a
small amount (about 1%), a device running at hundreds of megahertz can
spread its interference evenly over a few megahertz of spectrum, which
drastically reduces the amount of noise seen on broadcast FM radio
channels, which have a bandwidth of several tens of kilohertz.
Clock distribution
Typically, the reference clock enters the chip and drives a phase locked
loop (PLL), which then drives the system's clock distribution. The clock
distribution is usually balanced so that the clock arrives at every endpoint
simultaneously. One of those endpoints is the PLL's feedback input. The
function of the PLL is to compare the distributed clock to the incoming
reference clock, and vary the phase and frequency of its output until the
reference and feedback clocks are phase and frequency matched.
PLLs are ubiquitousthey tune clocks in systems several feet across, as
well as clocks in small portions of individual chips. Sometimes the
reference clock may not actually be a pure clock at all, but rather a data
stream with enough transitions that the PLL is able to recover a regular
clock from that stream. Sometimes the reference clock is the same
frequency as the clock driven through the clock distribution, other times
the distributed clock may be some rational multiple of the reference.
107
Jitter and noise reduction
One desirable property of all PLLs is that the reference and feedback clock
edges be brought into very close alignment. The average difference in
time between the phases of the two signals when the PLL has achieved
lock is called the static phase offset (also called the steady-state phase
error). The variance between these phases is called tracking jitter. Ideally,
the static phase offset should be zero, and the tracking jitter should be as
low as possible.
[dubious discuss]
Phase noise is another type of jitter observed in PLLs, and is caused by the
oscillator itself and by elements used in the oscillator's frequency control
circuit. Some technologies are known to perform better than others in this
regard. The best digital PLLs are constructed with emitter-coupled logic
(ECL) elements, at the expense of high power consumption. To keep
phase noise low in PLL circuits, it is best to avoid saturating logic families
such as transistor-transistor logic (TTL) or CMOS.
[citation needed]
Another desirable property of all PLLs is that the phase and frequency of
the generated clock be unaffected by rapid changes in the voltages of the
power and ground supply lines, as well as the voltage of the substrate on
which the PLL circuits are fabricated. This is called substrate and supply
noise rejection. The higher the noise rejection, the better.
To further improve the phase noise of the output, an injection locked
oscillator can be employed following the voltage controlled oscillator in
the PLL.
Frequency Synthesis
In digital wireless communication systems (GSM, CDMA etc.), PLLs are
used to provide the local oscillator (LO) for up-conversion during
transmission and down-conversion during reception. In most cellular
handsets this function has been largely integrated into a single integrated
circuit to reduce the cost and size of the handset. However, due to the
high performance required of base station terminals, the transmission and
reception circuits are built with discrete components to achieve the levels
of performance required. GSM LO modules are typically built with a
frequency synthesizer integrated circuit and discrete resonator VCOs.
[
Frequency synthesizer manufacturers include Analog Devices,
[11]
National
Semiconductor and Texas Instruments. VCO manufacturers include
Sirenza, Z-Communications, Inc. (Z-COMM).
108
AM, PM AND FSK MODULATORS AND DEMODULATORS:
AM DEMODULATION:
Circuit (Block) Diagram
The above circuit is used to demodulate AM signals, which uses a PLL
circuit.
The PLL is locked to the carrier frequency of the incoming signal.
The output of VCO, which has the same frequency as the carrier but
unmodulated is fed to the multiplier
Since VCO output is always 90 out of phase with the incoming AM
signal under the locked condition, before feeding to the multiplier
the AM signal is also shifted in phase by 90. Thus both the signals
applied to the multiplier are in phase.
The output of the multiplier contains both the sum and the
difference signals
The demodulated output is obtained after filtering the high
frequency components using a L.P.F.
Since the PLL responds only to the carrier frequencies which are
very close to the VCO output, a PLL AM detector exhibits a high
degree of selectivity and noise immunity which is not possible with
the conventional peak detector type. AM modulators.
WORKING OF FM DETECTOR USING PLL:
The PLL can be very easily used as an FM detector or demodulator
The fig above status the block diagram of the FM detector using
PLL.
When the PLL is located in on the FM signal, the VCO frequency follows
109
the Instantaneous frequency of the FM signal, and the error voltage or a
control voltage is proportional to the deviation of the inpw frequency from
the centre frequency. Therefore the a-c component of error voltage or
control voltage of VCO will represent a true replica of the modulating
voltage that is applied to the FM carrier at the transmitter.
The faithful reproduction of modulating voltage depends on the linearity
between the instantaneous frequency deviation and the control voltage of
VCO. It is also important to note that, the FM frequency should remain in
the locking range of PLL of get the faithful replica of the modulating
signal. It the product of the modulation frequency fm and the frequency
deviation exceeds the (fc>2) the VCO will not be able to follow the
instant tenuous frequency variations of the FM signal.
FSK DEMODULATOR :
In digital data communication, binary data is transmitted by means of a
carrier frequency. It uses two different carrier frequencies for logic l and
logic O states of binary data signal. This type of data transmission is
called frequency shift keying (FSK). In this data transmission, on the
receiving end the two carrier frequencies are converted into 1 and 0 to
get the original binary data. This process is called as FSK demodulation .
A PLL can be used as a FSK demodulator as show in the diagram below
It is similar to the PLL demodulator for analog FM signals excepts for the
addition of a comparator to produce a reconstructed digital output signal.
Let us consider that there are two frequencies, one frequency (f
1
) is
represented as 0 and other frequency (f
2
) is represented as 1 if the
PLL remain in locked into the FSK signal at both F
1
and f
2
the VCO control
voltage which is also supplied to the comparator will be given as
110
V
C1
= (f
1
- f
2
) / K
V
and
V
C2
= (f
2
f
1
) / K
V
respectively.
Where K
V
is the voltage to frequency transfer co-efficient of the VCO
The difference between the two control voltage levels will be
V
C
= (f
2
- f
1
) / K
V
The reference voltage for the comparator is derived from the additional
LPF and it is adjusted between V
C1
&V
C2
. Hence for V
C1
output goes to high
& for V
C2
output goes to low.
FREQUENCY SYNTHESIZERS:
PLL can also be used to translate the frequency of a highly stable,
but fixed-frequency reference oscillator by a small factor. A scheme for
this purpose is shown in fig. As shown, a mixer (or multiplier) and a low-
pass filter are associated with the basic PLL.
In this case, the reference frequency f
R
and the VCO output to are
applied as inputs to the mixer stage, the output of which is passed
through the low-pass filter so that only the difference frequency (f
o
-f
R
)
appears at the phase comparator.
Fig:
The translation or offset frequency f
1
(i.e. f
1
<<f
R
) is also applied to
the phase comparator. Therefore, when the system is in lock, the two
input to the phase comparator are at the same frequency. Thus.
111
O R 1
O R 1
f f f
or
f f f

+
This indicates that frequency translation is achieved, this arrangement is
also useful is frequency synthesis applications.
TIMER IC 555:
Introduction:
The 555 timer is a highly stable device for generating accurate time
delay or oscillation. Signetics Corporation first introduced this device as
the SE555 / NE555 and it is available in two packages styles, 8 pin
circular style. TO -99 can or 8 pin mini DIP or as 14 pin DIP. The 556
timer contains two 555 timers and is a 14 pin DIP. The 556 timer
contains two 555 timers and is a 14 pin DIP. There is also available
counter timer such as Exars XR 2240 which contains a 555 timer plus a
programmable binary counter in a single 16 pin package. A single 555
timer can provide time delay ranging from microseconds to hours whereas
counter timer can have a maximum timing range of days.
The 555 timer can be used with supply voltage in the range of + 5V
to 18 V and can drive load upto 200 mA. It is compatible with both TTL
and CMOS logic circuits. Because of the wide range of supply voltage, the
555 timer is versatile and easy to use in various applications. Various
applications include oscillator, pulse generator, ramp and square wave
generator, mono shot multivibrator, burglar alarm, traffic light control
and voltage monitor etc.
555 TIMER FUNCTIONAL DIAGRAM AND SPECIFICATIONS:
112
8
V
CC
7
Discharge
6 Threshold
5 Control voltage
1 Ground
2
Trigger
3
Output
4
Reset
555
8 pin
diagram
Figure 8.1 gives the pin diagram and Fig. 8.2 gives the functional diagram
for 555 IC timer. Referring to Fig. 8.2, three 5 k internal resistors act as
voltage divider, providing bias voltage of (2/3) V
CC
to the upper
comparator (CU) and (1/3) V
CC
to the lower comparator (LC), where V
CC
is
the supply voltage. Since these two voltages fix the necessary comparator
threshold voltage, they also aid in determining the timing interval. It is
possible to vary time electronically too, by applying a modulation voltage
to the control voltage input terminal (pin 5). In applications, where no
such modulation is intended, it is recommended by manufacturers that a
capacitor (0.01 F) be connected between control voltage terminal (pin 5)
and ground to by pass noise or ripple from the supply.
In the standby (stable) state, the output
Q
of the control flip flop
(FF) is (HIGH). This makes the output LOW because of power amplifier
which is basically an inverter. A negative going trigger pulse is applied to
pin 2 and should have its dc level greater than the threshold level of the
lower comparator (i.e. V
CC
/3). At the negative going edge of the trigger, as
the trigger passes through (V
CC
/ 3), the output of the lower comparator
goes HIGH and sets the FF (Q = 1,
Q
=0 ). During the positive excursion,
when the threshold voltage at pin 6 passes through (2 /3) V
CC
, the output
of the upper comparator goes HIGH and resets the FF (Q = 0,
Q
= 1).
The reset input (pin 4) provides a mechanism to reset the FF in a
manner which overrides the effect of any instruction coming to FF from
lower comparator. This overriding reset is effective when the reset input is
less than about 0.4 V. when this reset is not used, it is returned to V
CC
. The
transistor Q
2
serves as a buffer to isolate the reset input from the FF and
transistor Q
1
. The transistor Q
2
is driven by an internal reference voltage
113
V
ref
obtained from supply voltage V
CC
.
APPLICATION AS MONOSTABLE, ASTABLE, BISTABLE, PULSE
WIDTH MODULATOR:
Mono-stable Multivibrators using 555 timers:
Figures 8.3 shows a 555 timer connected for mono stable operator
and its functional diagram is shown in Fig. 8.4. In the standby state, FF
holds transistors Q
1
on, thus clamping the external timing capacitor C to
ground. The output remains at ground potential, i.e. LOW. As the trigger
passes through V
CC
/ 3, the FF is set, i.e.
Q
= 0. This makes the transistor
Q
1
off and the short circuit across the timing capacitor C is released. As
Q

is LOW, output goes HIGH (= V
CC
). The timing cycle now begins. Since C is
unclamped, voltage across it rises exponentially through R towards V
CC
with a time constant RC
as in Fig 8.5 (b). After a time period T (calculated later) the capacitor
voltage is just greater than (2 /3) V
CC
and the upper comparator resets the
FF, that is R = 1, S = 0 (assuming very small trigger pulse width). This
makes
Q
= 1, transistor Q
1
goe son (i.e. saturates), thereby discharging
the capacitor C rapidly to ground potential. The output returns to the
standby state or ground potential as shown in Fig 8.5 (c)
114
The voltage across the capacitor as in Fig. 8.5 (b) is given by
At t = T,
Therefore,
( ) ( )
( )
t / RC
c cc
c cc
V 1 e 8.1
2/ 3 V

( )
( )
( ) ( )
T / RC
cc CC
2
V V 1 e
3
or,
T RC In 1/ 3
or, T 1.1RC seconds 8.2
It is evident from Eq. (8.2) that the timing interval is independent of

the supply voltage. It may also be noted that once triggered, the output
remains in the HIGH state until time T elapses, which depends only upon R
and C. Any additional trigger pulse coming during this time will not
change the output state. However, if a negative going reset pulse as in
Fig. 8.5 (d) is applied to the reset terminal (pin 4)during the timing cycle,
transistor Q
2
goes off Q
1
becomes on and the external timing capacitor C
115
is immediately discharged. The output now will be as in Fig. 8.5 (e). It may
be seen that the output of Q
2
is connected directly to the input of Q
1
so as
to tune on Q
1
immediately and thereby avoid the propagation delay
through the FF. Now even
if the reset is released, the output will still remain LOW until a negative
going trigger is again applied at pin 2. figure 8.6 shows a graph of the
various combinations of R and C necessary to produce a given time delay.
Sometimes the mono-stable circuit of Fig. 8.3 mistriggers on
positive pulse edges, even with the control pin bypass capacitor. To
prevent this, a modified circuit as shown in Fig. 8.7 is used. Here the
resistor and capacitor combination of 10 k and 0.001 F at the input
116
forms a differentiator. During the positive going edge of the trigger, diode
D becomes forward biased, thereby limiting the amplitude of the positive
spike to 0.7 V.
APPLICATIONS:
Missing Pulse Detector:
Missing pulse detector circuit using 555 timer is shown in Fig. 8.8.
Whenever, input trigger is low, the emitter diode of the transistor Q is
forward biased. The capacitor C gets clamped to few tenths of a volt (
0.7 V). The output of the timer goes HIGH. The circuit is designed so that
the time period of the monostable circuit is slightly greater (1/3 longer)
than that of the triggering pulses. So long as trigger pulse train keeps
coming at pin 2, the output remains HIGH. However, if a pulse misses, the
trigger input is high and transistor Q is cut off. The 555 timer enters into
normal state of monostable operation. The output goes LOW after time T
of the mono shot. Thus this type of circuit can be used to detect missing
heartbeat. It can also be used for speed control and measurement. If input
trigger pulses are generated from a rotating wheel, the circuit tells when
the wheel speed drops below a predetermined value.
117
Linear Ramp Generator:
Linear ramp can be generated by the circuit shown in Fig. 8.10. The
resistor R of the mono stable circuit is replaced by a constant current
source. The capacitor is charged linearly by the constant current source
formed by the transistor Q
3
. The capacitor voltage
c
can be written as
t
c
0
1
i dt (8.3)
C

where i is the current supplied by the constant current source. Further,

the KVL equation can be written as
( )
1
CC BE B E C E E (8.4)
1 2
R
V V I R I R iR
R R
+1
+
where I
B
, I
C
are the base current and collector current respectively. is
the current amplification factor in CE mode and is very high. Therefore,
( )
( )
( )
I CC BE 1 2
E 1 2
RV V R R
i 8.5
R R R
+
+
118
Now putting the value of the current i in Eq. (8.3), we get
( )
( )
( )
I CC BE 1 2
c
E 1 2
RV V R R
t 8.6
C R R R
+

+
At tune t = T, the capacitor voltage
C
becomes (2/3) V
CC
. Then we get
( )
( )
( )
I CC BE 1 2
cc
E 1 2
RV V R R
2
V T 8.7
3 R R R C
+

+
Which gives the time period of the linear ramp generator as
( ) ( )
( )
( )
CC E 1 2
1 CC BE 1 2
2/ 3 V R R R C
T 8.8
R V V R R
+
+
119
Frequency Divider:
A continuously triggered monostable circuit when triggered by a
square wave generator can be used as a frequency divider, if the timing
interval is adjusted to be longer than the period of the triggering square
wave input signal. The monostable multivibrator will be triggered by the
first negative going edge of the square wave input but the output will
remain HIGH (because of greater timing interval) for next negative going
edge of the input square wave as shown in Fig. 8.12. the mono shot will
however be triggered on the third negative going input, depending on the
choice of the time delay. In this way, the output can be made integral
fractions of the frequency of the input triggering square wave.
Pulse Width Modulation:
The circuit is shown in Fig. 8.13. This is basically a mono stable
120
multivibrator with a modulating input signal applied at pin 5. By the
application of continuous trigger at pin 2, a series of output pulses are
obtained, the duration of which depends on the modulating input at pin
5. The modulating signal applied at pin 5 gets superimposed upon the
already existing voltage (2/3) V
CC
at the inverting input terminal of UC.
This is turn changes the threshold level of UC and the output pulse width
modulation takes place. The modulating signal and the output waveform
are shown in Fig. 8.14. It may be noted form the output waveform that the
pulse duration, that is, the duty cycle only varies, keeping the frequency
same as that of the continuous input pulse train trigger.
ASTABLE OPERATION OF IC 555 TIMERS:
The device is connected for astable operation in Fig. 8.15, for better
understanding, the complete diagram of astable multivibrator with
detailed internal diagram of 555 is shown in Fig. 8.16. Comparing with
monostable operation, the timing resistor is now split into two sections R
A
121
and R
B
. Pin 7 of discharging transistor Q
1
is connected to the junction of R
A
and R
B
. When the power supply V
CC
is connected, the external timing
capacitor C charges towards V
CC
with a time constant
(R
A
+ R
B
) C. During this time, output (pin 3) is high (equals V
CC
) as Reset R
= 0, Set S = 1 and this combination makes
Q
= 0 which has unclamped
the timing capacitor C.
When the capacitor voltage equals (to be precise is just greater than),
(2/3)V
CC
the upper comparator triggers the control flip flop so that
Q
= 1.
This, in turn, makes transistor Q
1
on and capacitor C starts discharging
towards ground through R
B
and transistor Q
1
with a time constant R
B
C
(neglecting the forward resistance of Q
1
). Current also flows into transistor
Q
1
through R
A
. Resistors R
A
and R
B
must be large enough to limit this
current and prevent damage to the discharge transistor Q
1
. The minimum
value of R
A
is approximately equal to V
CC
/ 0.2 A is the maximum current
through the on transistor Q
1
.
During the discharge of the timing capacitor C, as it reaches (to be
precise, is just less than) V
CC
/ 3, the lower comparator is triggered and at
this stage S = 1, R = 0, which turns
Q
= 0. Now
Q
= 0 unclamps the
external timing capacitor C. The capacitor C is thus periodically charged
and discharged between (2/3) V
CC
and (1/3) V
CC
respectively. Figure 8.17
shows the timing sequence and capacitor voltage wave form. The length
of time that the output remains HIGH is the time for the capacitor to
charge from (1/3) V
CC
to (2/3) V
CC
. It may be calculated as follows:
122
The capacitor voltage for a low pass RC circuit subjected to a step
input of V
CC
volts is given by
( )
t / RC
c cc
V 1 e

The time t
1
taken by the circuit to charge from 0 to (2/3) V
CC
is,
( ) ( ) ( )
1
t / RC
CC CC
2/ 3 V V 1 e 8.9
or t
1
= 1.09 RC
and the time t
2
to charge from 0 to (1/3) V
CC
is,
( ) ( ) ( )
2
t / RC
CC CC
1/ 3 V V 1 e 8.10
or, t
2
= 0.405 RC
So the time to charge from (1/3) V
CC
to (2/3) V
CC
is
t
HIGH
= t
1
t
2
t
HIGH
= 1.09 RC 0.405 RC = 0.69 RC
So, for the given circuit,
t
HIGH
= 0.69 (R
A
+ R
B
)C (8.11)
The output is low while the capacitor discharges from (2/3) V
CC
to
(1/3) V
CC
and the voltage across the capacitor is given by
(1/3) V
CC
(2/3) V
CC
e
-t / RC
Solving, we get t = 0.69 RC
So, for the given circuit, t
LOW
= 0.69 R
B
C (8.12)
123
Notice that both R
A
and R
B
are in the charge path, but only R
B
is in the
discharge path. Therefore, total time,
T = t
HIGH
+ t
LOW
Or,
T = 0.69 (R
A
+ 2R
B
) C
So,
( )
A B
1 1.45
f
T R 2R C
+
Figure 8.18 shows a graph of the various combination of (R
A
+ R
B
)
and C necessary to produce a given stable output frequency. The duty
cycle D of a circuit is defied as the ratio of ON time to the total time period
T = (t
ON
+ t
OFF
). In this circuit, when the transistor Q
1
is on, the output goes
low. Hence,
LOW
B
A B
t
D 100
T
R
100
R 2R

+
With the circuit configuration of Fig. 8.15 it is not possible to have a
duty cycle more than 50% since t
HIGH
= 0.69 (R
A
+ R
B
) C will always be
greater than t
LOW
= 0.69 R
B
C. In order to obtain a symmetrical square
wave i.e. D = 50%, the resistance R
A
must be reduced to zero. However,
now pin 7 is connected directly to V
CC
and extra current will flow through
Q
1
when it is on. This may damage Q
1
and hence the timer.
An alternative circuit which will allow duty cycle to be set at
124
practically any level is shown in Fig. 8.19 During the charging portion of
the cycle, diode D
1
is forward effectively short circuiting R
B
so that
t
High
= 0.69 R
A
C
However, during the discharging portion of the cycle, transistor Q
1
becomes ON, thereby grounding pin 7 and hence the diode D
1
is and
reversed biased.
So t
LOW
= 0.69 R
B
C (8.15)
T = t
HIGH
+ t
LOW
= 0.69 (R
A
+ R
B
)C (8.16)
Or,
( )
( )
A B
1.45
f 8.17
R R C
+
and duty cycle
B
A B
R
D
R R
+
Resistors R
A
and R
B
could be made variable to allow adjustment of
frequency and pulse width. However, a series resistor of at least 100
(fixed) should be added to each R
A
and R
B
. This will limit peak current to
the discharge transistor Q
1
when the variable resistors are at minimum
value. And, if R
A
is made equal to R
B
then 50% duty cycle is achieved.
Symmetrical square wave generator by adding a clocked JK flip
flop to the output of the non symmetrical square wave generator is shown
in Fig. 8.20. The clocked flip flop acts as binary divider to the timer
output. The output frequency in this case will be one half that of the timer.
125
The advantage of this circuit is of having output of 50% duty cycle without
any restriction on the choice of R
A
and R
B
.
APPLICATION OF ASTABLE MULTIVIBRATOR:
Square Wave Generator:
It can be observed from the expression of duty cycle that in astable
operation exact 50% duty cycle is not possible to achieve. To get exactly
50% duty cycle i.e. square wave output it is necessary to modify the
astable timer circuit.
In the modified circuit, the capacitor C charges through R
A
and diode D
and discharges through R
B
. To obtain square wave (50% duty cycle)
resistance R
B
is adjusted such that it is equal to the summation of
resistance R
A
and the forward resistance of diode D. Usually,
potentiometer is used for exact adjustment f resistors.
126
Voltage Controlled Oscillator (VCO)
Fig 6.21 shows the circuit diagram for voltage control oscillator. It is
basically an astable multivibrator circuit with variable control voltage.
We know that internally set voltage at the control voltage terminal
is 2 /3 V
CC
. In this circuit, the control voltage is externally set by the
potentiometer. With change in the control voltage, the upper threshold
voltage changes and thus the time required to charge capacitor upto
upper threshold voltage changes. Similarly, discharges time also changes.
As a result, the frequency of the output voltage changes.
If control voltage is increased, the capacitor will take more time to
charge and discharge and therefore frequency will decrease. On the other
hand, if control voltage is decreased, the capacitor will take less time to
charge and discharge, increasing the frequency of the output signal. Thus
by varying control voltage we can change the frequency.
FSK Generator:
Binary code consists of 1s and 0s. It can be transmitted by shifting
a carrier frequency. One fix frequency represents one and other
represents zero. This type of transmission if called frequency shift keying
(FSK) technique. Astable multivibrator using 555 can be used to generate
FSK signal.
The circuit for FSK generation is as shown in the Fig 6.22.
127
When digital input is HIGH (logic 1), transistor T
1
is OFF and 555
timer works in a normal astable mode. The frequency of the output
waveform can be given as
( )
0
1 2
1.45
f
R 2R C
+
When input is LOW (logic 0), transistor T
1
is ON and connects the
resistance R
P
in parallel with R
1
.With this connecting effective R
left
becomes R
1
|| R
P
, and output frequency is now given by
( )
0
1 P 2
1.45
f
R || R 2R C
1 +
]
with this connection effective resistance R
eff
becomes R
1
|| R
P
Timer as a Schmitt Trigger
128
The Fig. 6.23 shows the use of 555 timer as a Schmitt trigger.
The input is given to the pins 2 and 6 which are tied together. Pins 4
and 8 are connected to supply voltage + V
CC
. The common point of two
pins 2 and 6 is externally biased at V
CC
/2 through the resistance network
R
1
and R
2
. Generally R
1
= R
2
to get the biasing of V
CC
/ 2. The upper
comparator will trip at 2 /3 V
CC
while lower comparator at 1 / 3 V
CC
. The
bias provided by R
1
and R
2
is centered within these two thresholds.
Thus when sine wave of sufficient amplitude, greater than V
CC
/ 6 is
applied to the circuit as applied to the circuit as input, it causes the
internal flip flop to alternately set and reset. Due to this, the circuit
produces the square wave at the output, as shown in the Fig. 6.24
BISTABLE MULTIVIBRATORS:
In a Bistable Multivibrators circuit, both states are stable, and the circuit
will remain in either state indefinitely. This type of Multivibrator circuit
passes from one state to the other "Only" when a suitable external trigger
pulse T is applied and to go through a full "SET-RESET" cycle two
triggering pulses are required. This type of circuit is also known as a
"Bistable Latch", "Toggle Latch" or simply "T-latch".
129
NAND Gate Bistable Multivibrator.
The simplest way to make a Bistable Latch is to connect together a pair of
Schmitt NAND Gates as shown above. The two NAND Gates, U2 and U3
form a SET-RESET (SR) Bistable which is triggered by the input NAND
Gate, U1. This U1 NAND Gate can be omitted and replaced by a single
toggle switch to make a switch debounce circuit as seen previously in the
SR Flip-flop tutorial. When the input pulse goes "LOW" the Bistable latches
into its "SET" state, with its output at logic level "1", until the input goes
"HIGH" causing the Bistable to latch into its "RESET" state, with its output
at logic level "0". The output of the Bistable will stay in this "RESET" state
until another input pulse is applied and the whole sequence will start
again.
Then a Bistable Latch or "Toggle Latch" is a two-state device in which both
states either positive or negative, (logic "1" or logic "0") are stable.
Bistable Multivibrators have many applications such as frequency dividers,
counters or as a storage device in computer memories but they are best
used in circuits such as Latches and Counters.
130
UNIT V
APPLICATION SPECIFIC ICS
VOLTAGE REGULATORS:
Introduction to Voltage Regulator
A power supply is an important element of any type of electronic
circuit. It provides the supply for the proper operation of the circuit. The
successful operation of the circuit depends on the proper functioning of
the power supply. Most of the electronic circuits require a smooth d.c.
voltage as that of batteries. The power supply in a circuit tries to provide
such a constant voltage. A block diagram containing the parts of a typical
power supply and nature of the voltages at various points is shown in the
Fig. 6.30.
The a.c voltage is connected to a transformer. The transformer
steps down the a.c. voltage down to the level required for the desired d.c.
output. The rectifier converts a.c. voltage to a d.c. voltage. The filter
circuit is used after the rectifier to reduce the ripple content in the d.c., to
make it smoother. Still then the d.c voltage usually has some ripple or a.c.
voltage variation. This voltage is called unregulated d.c. voltage. A
regulator circuit is a circuit used after the filter, which not only makes the
131
d.c voltage constant though input d.c voltage varies under certain
conditions. It keeps the output d.c. voltage constant under the variable
load conditions. It keeps the output d.c voltage constant under the
variable load conditions, as well. Thus input to a regulator is an
unregulated d.c. voltage while the output of a regulator is a regulated d.c.
voltage, to which the load is connected. Such a regulator block is shown
dotted in the figure. Now a days, complete regulator circuits are available
in integrated circuit form.
Voltage Regulator Characteristics:
Let us study some important regulator characteristics and the
factors affecting the load voltage.
Load Regulation:
The load regulation is the change in the regulated output voltage
when the load current is changed from minimum (no load) to maximum
(full load).
132
The load regulation is denoted as LR and mathematically expressed as,
LR = V
NL
- V
FL
Where
V
NL
= Load voltage with no load current
V
FL
= load voltage with full load current
The load regulation is often expressed as percentage by dividing the
LR by full load voltage and multiplying result by 100.
NL FL
FL
V V
%LR 100
V

The graph of load current against load voltage is called regulation
characteristics of a power supply. The ideal value of load regulation is
zero. Less the regulation, better is the performance of regulation
characteristics is shown in the Fig.
Source Regulation
The input to the unregulated power supply i.e. rectifier circuit is 230
V. a.c. supply. This line voltage may change, under the different load
condition. This affects the output voltage of rectifier which is V
in
for a
regulator circuit. Hence the characteristics which gives source effect on
regulator performance is defined.
The source regulation is also called line regulation or source effect
and denoted as SR.
The SR is defined as the change in the regulated load voltage for a
specified range of line voltage, typically 230 V t 10%
Mathematically it is expressed as,
SR = V
HL
- V
LL
Where V
HL
= load voltage with high line voltage
V
LL
= load voltage with low line voltage.
The percentage source regulation is defined as,
nom
SR
%SR 100
V

Where V
nom
= nominal load voltage.
133
Output Impedance
The output impedance of regulated power supply is very small. It
can supply different loads keeping load voltage constant. In a series
regulator, the pass transistor Q
2
is an emitter follower which has very low
output impedance Z
out
. The use of voltage feedback reduces it to,
( )
out
out CL
Z
Z , A
1 AB

+
Forward gain, B = Feedback factor.
Hence regulated power supply has output impedance in milliohms so it is
very stiff voltage source.
Ripple Rejection
The output of rectifier and filter circuit consists of ripples. The ripple
is equivalent to periodic changes in input voltage. Due to the negative
feedback, the ripple voltage gets attenuated by large amount. The factor
by which it gets reduced is 1+ AB. Mathematically the output ripple of a
voltage regulator is given by,
( )
( ) r in
R out
V
V
1 AB
+
The performance parameter, ripple rejection denoted as RR is defined as,
( )
( )
r outc
R in
V
RR
V
In datasheet, it is expressed in decibels (dB)

( )
( )
r out
R in
V
RR' 20logRR 20log dB
V

Note: As V
R (out)
is always less than V
R(in)
RR i.e. RR in dB is always
negative when defined as V
R (out)
/ V
R (in)
The Load Current (I
L
)
As discussed, the load current affects the load voltage. The variation
in load is indicated by the variation in the load current. Ideally the output
voltage should remain constant for the variation of load from no load to
134
the full load condition.
Temperature
The rectifier using the components like diodes is temperature
sensitive. Hence the temperature is an important factor responsible for
the changes in the load voltage. The semiconductor devices used in power
supplies, have their characteristics which is temperature dependent.
The voltage regulator circuit mainly, has to consider the above
discussed factors and has to provide constant d.c. load voltage
irrespective of changes in load, line voltage and the temperature.
Basic Voltage Regulator its types and advantages.
The basic voltage regulator in its simplest form consists of,
1. Voltage reference, V
R
2. Error amplifier
3. Feedback network
4. Active series or shunt control element.
The voltage reference generates a voltage level which is applied to the
comparator circuit, which is generally error amplifier. The second input to
the error amplifier is obtained through feedback network. Generally using
the potential divider, the feedback signal is derived by sampling the
output voltage. The error amplifier converts the difference between the
output sample and the reference voltage into an error signal. This error
signal in turn controls the active element of the regulator circuit, in order
to compensate the change in the output voltage. Such an active element
is generally a transistor.
Types of Voltage Regulators
Depending upon where the control element is connected in the
regulator circuit, the regulators are basically classified as,
1. Series voltage regulator
2. Shunt voltage regulator
Each type provides a constant d.c. output voltage which is regulated.
Shunt Voltage Regulator
135
The heart of any voltage regulator circuit is a control element. If
such a control element is connected in shunt with the load, the regulator
circuit is called shunt voltage regulator. The Fig 6.33 shows the block
diagram of shunt voltage regulator circuit.
The unregulated input voltage V
in,
tries to provide the load current.
But part of the current is drawn by the control element, to maintain the
constant voltage across the load. If there is any change in the load
voltage, the sampling circuit provides a feedback signal to the comparator
circuit. The comparator circuit compares the feedback signal with the
reference voltage and generates a control signal which decides the
amount of current required to be shunted to keep the load voltage
constant. For example if the load voltage increases then the comparator
circuit decides the control signal based on the feedback information,
which draws the increased shunt current I
sh
. Due to this the load current I
L
decreases, hence the load voltage decreases to its normal value. Thus the
control element maintains the constant output voltage by shunting the
current, hence the circuit is called shunt voltage regulator.
Block diagram of series voltage regulator
If in a voltage regulator circuit, the control element is connected in
series with the load, the circuit is called series with the load, series
voltage regulator circuit. The Fig. 6.34 shows the block diagram of series
136
voltage regulator circuit.
The unregulated d.c. voltage is the input to the circuit. The control
element, controls the amount of the input voltage, that gets to the output.
The sampling circuit provides the necessary feedback signal. The
comparator circuit compares the feedback with the reference voltage to
generate the appropriate control signal. For example, if the load voltage
tries to increase, the comparator generates a control signal based on the
feedback information. This control signal causes the control element to
decrease the amount of the output voltage. Thus the output voltage is
maintained constant.Thus, control element which regulates the load
voltage based on the control signal is in series with the load and hence
the circuit is called series voltage regulator circuit.
Advantages of IC Voltage Regulators
The various advantages of IC voltage regulators are,
1. Easy to use.
2. It greatly simplifies power supply design.
3. Due to mass production, low in cost.
4. IC voltage regulators are versatile.
5. Conveniently used for local regulation.
6. These are provided with features like built in protection,
programmable output current / voltage boosting, internal short
circuit current limiting etc.
FIXED, VARIABLE AND SWITCHING MODE VOLTAGE REGULATOR:
LINEAR IC 723 REGULATORS:
The popular general purpose precision regulator is IC 723. It is a
monolithic linear integrated circuit in different physical packages. The pin
diagram along with the various packages is shown in the Fig. (6.35 (a), (b)
and (C)
137
Important Features of IC 723
1. It works as voltage regulator at output voltage ranging from 2 to 37
volts at currents upto 150mA.
2. It can be used at load currents greater than 150 mA with use of
suitable NPN or PNP external pass transistors.
3. Input and output short circuit protection is provided.
4. It has good line and load regulation (0.03%)
5. Wide variety of applications of series, shunt, switching and floating
regulator.
6. Low temperature drift and high ripple rejection.
138
7. Low standby current drain.
8. Small size, lower cost
9. Relative ease with which power supply can be designed.
10. It provides a choice of supply voltage
INTERNAL STRUCTURE OF IC 723
The functional block diagram of IC 723 can be divided into four major
blocks
1. Temperature compensated voltage reference source, which is zener
diode.
2. An op amp circuit used as an error amplifier
3. A series pass transistor capable of a 150 mA output current.
4. Transistor used to limit output current.
The functioning of the above blocks can be explained with the help of a
simplified functional block diagram of IC 723 as shown in the Fig. 6.36.
Temperature compensated zener diode, constant current source and
reference amplifier constitutes the reference element. In order to get a
fixed voltage from zener diode, the constant current source forces the
zener to operate at a fixed point. Output voltage is compared with this
temperature compensated reference potential of the order of 7 volts. For
this V
ref
is connected to the non inverting input of the error amplifier.
This error amplifier is high gain differential amplifier. Its inverting
input is connected to the either whole regulated output voltage or part of
that from outside. For later case a potential divider of two scaling resistors
is used. Scaling resistors help in getting multiplied reference voltage or
scaled up reference voltage. Error amplifier controls the series pass
transistor Q
1
, which acts as variable resistor. The series pass transistor is
a small power transistor having about 800 mW dissipation. The
139
unregulated power supply source (< 36V. d.c.) is connected to collector of
series pass transistor. Transistor Q
2
acts as current limiter in case of short
circuit condition. It senses drop across R
SC
placed in series with regulated
output voltage externally. The frequency compensation terminal controls
the frequency response of the error amplifier. The required roll off is
obtained by connecting a small capacitor of 100pF between frequency
compensation and inverting input terminals.
The internal structure can be represented in more simplified form as
shown in the Fig. 6.37. Both non-inverting and inverting terminals of the
error amplifier are available on outside pins of IC 723. Due to this, device
becomes versatile and flexible to use. Only
restriction is that internal reference voltage is 7 volts and therefore we
have to use tow different circuits for getting regulated outputs of below 7
volts and above 7 volts.
SWITCHED MODE VOLTAGE REGULATORS:
The operating principle of switching regulators is completely
different than that of linear regulators. Such a switching regulator requires
an external transistor and a choke. The series pass transistor in such a
regulator is used as a controlled switch and is operated in cut off region or
saturation region. Hence the power transmitted across such a transistor is
in the form of discrete pulses rather than a steady flow of current.
When the transistor is operated in the cut off region, there is no
current and dissipates no power. While when it is operated in the
saturation region, a negligible voltage drop appears across it and hence
dissipates very small power, providing maximum current to load. In any
case, the power dissipated in the transistor is very small. Almost the
140
entire power gets transmitted to the load. Hence the efficiency of principle
of the switching regulators is always very high. The pulse width
modulation is the basic principle of the switching regulators. The average
value of repetitive pulse waveform is proportional to the area under the
waveform. So, switching regulators use the fact that if duty cycle of the
pulse waveform is varied, the average values of the voltage also change
proportionally.
Figure: Pulse width modulation
The duty cycle of the pulse waveform is the ratio of the on time t
on
to the period T of the pulse waveform. Mathematically it can be expressed
as,
Duty cycle ( )
on
on off
t
.... 6.28
t t
+
( )
on
on
t
T
t f .... 6.28
Where,
141

on
off
on off
t on time of pulse
t off time of pulse
T= time period
1
=t t
f
+
This basic pulse width is shown in the Fig. 6.50
The basic switching regulator consists of four major components:
a) Voltage source V
in
b) Switching transistor
c) Pulse generator, V
pulse
d) Filter F
1
Figure: Basic switching regulator
These blocks are connected together as shown in the Fig. 6.51, to
obtain the switching regulator.
A voltage source V
in
is a d.c. supply which is a battery, unregulated
or regulated voltage.
It has to satisfy the requirements as:
i) It has to supply required power and the losses associated with
the regulator
ii) It must be high to satisfy the minimum requirements of the
regulator
iii) It must be large to supply sufficient dynamic range of line and
load changes.
The switch is generally, a transistor. The pulse generator output makes
it on and off. The pulse generator produces a required pulse waveform.
The most effective range of pulse waveform frequency is 20 kHz. The
typical operating frequency range is 10 to 50 kHz. The filter F
1
may be RC,
RL or RLC. Most commonly used filter is RLC. It converts the pulse
waveform obtained from the switch into a d.c. output voltage.
142
Functional Block Diagram
The Fig. 6.52 shows the functional block diagram of basic switching
voltage regulator, which uses transistor Q
1
as a switch.
The part R
2
/ R
1
+ R
2
of the output is feedback to the inverting input
of error amplifier. It is compared with the reference voltage. The
difference is amplified and given to the comparator inverting terminal.
The oscillator generates a triangular waveform at a fixed frequency. It is
applied to the non inverting terminal of the comparator. The output of
the comparator is high when the triangular voltage waveform is above the
level of the error amplifier output. Due to this the transistor Q
1
remains in
cut off state. Thus the output of the comparator is nothing but a required
pulse waveform.
The period of this pulse waveform is same as that of oscillator
output say T. The duty cycle is denoted as = t
on
/ T or t
on
f as mentioned
earlier. This duty cycle is controlled by the difference between the
feedback voltage and the reference voltage. When Q
1
is on in saturation
state, V
CE (sat)
for Q
1
is zero. Hence entire input voltage V
in
appears at point
A. Thus the current flows through inductor L
1
. When Q
1
is off, L
1
still
continue to supply current through itself to the load. The diode D
1
provides the return path for the current.
143
The capacitor C
1
acts to smooth out the voltage and the voltage at
the output is almost d.c. in nature. The output voltage V
0
of the switching
regulator is a function of duty cycle and the input voltage V
in
.
Mathematically it is expressed as,
( )
on
0 in in
t
V V V .... 6.30
T

Thus when T is constant, output is proportional to t
on
. This method is
called as pulse width modulation (PWM). When t
on
is constant, the output
is inversely proportional to the period T i.e. proportional to frequency of
the pulse waveform. This method is called as frequency modulation. The
PWM technique is commonly used though it is more complex as it is most
suitable for the high current applications.
A high switching frequency allows small values of L
1
and C
1
and thus
reduces size, cost and weight. It also reduces the ripple at the output. But
the efficiency decreases and electrical noise increases. On the other hand,
low switching frequency improve efficiency and reduce noise but require
large filtering components. As a result of this the range of operating
frequency to get maximum efficiency is 10 to 50 kHz.
UNIVERSAL ACTIVE FILTER:
SWITCHED CAPACITOR FILTERS:
For getting good reliability and high performance, IC active filters
are used. But major limitations of such ICs is the values of integrated
resistors. The resistor values required for RC active filters are generally
very high and such large value resistors require large chip area. Similarly
the temperature and linearity characteristics of integrated resistors are
poor. Hence it is necessary to find the replacement for the high value
integrated resistors. The switched capacitor filters fulfill this requirement.
The switched capacitor filters use the on chip capacitors of small values
and MOS (metal oxide semiconductor) switches, to simulate high value
resistors. The switches are controlled by the external clock, whose
frequency can be easily controlled.
Advantages of Switched Capacitor Filter
The various advantages of switched capacitor filter are,
144
1. Very high value of resistors can be easily simulated using small
value capacitors, of the order of 10 pF.
2. The switched capacitor filters require no external reactive
components like inductors and capacitors.
3. Complete active filters can be easily obtained on a monolithic IC
chip.
4. The cut off frequencies of the filters are proportional to the
external clock frequency of switched capacitor filter. Hence can be
easily controlled.
5. The cut off frequencies of switched capacitor filters can be
programmed so as to obtain within very high range of frequencies,
of the order of 200000 : 1 range.
6. Accuracy is very high
7. The overall cost of the system is low.
8. Due to good temperature characteristics, the systems have good
temperature stability.
9. Reduction in size: A 10 M resistor can be simulated in a space 1 /
100
th
the space required for the resistor produced by using ordinary
integration technique.
The only disadvantages of the switched capacitor filters, is that they
generate more noise than the standard active filters.
Basic Operation of Switched Capacitor Filter
Figure: Crock schematic of switched capacitor fitter
A switched capacitor filter is a three terminal device which consists
of capacitor and MOS switches. The block schematic of switched capacitor
filter is shown in the Fig.6.59. The S
1
and S
2
are the two MOS switches and
C is the capacitor. The three terminals are marked as 1, 2 and 3. The
terminal 3 is common at input and output and generally grounded.
The two switches operated alternately and a capacitor C together is
145
used to simulate high value resistors. Let us see the simulation of a
resistor using capacitor and the two switches.
Figure: Resistance simulation
Consider a circuit using a basic switched capacitor filter, as shown in
the Fig. 6.60. The two switches S
1
and S
2
are the MOS transistors which
are alternately opened and closed. Thus when S
1
is closed, S
2
is open and
vice versa.
The switches are opened and closed alternately by using an external
clock with a frequency f
CLK
.
Consider the switch S
1
is in position a i.e. it is closed. So capacitor
C gets charged to voltage V
in
. Hence the total charge on the capacitor is,
( )
in
A C V ... 6.31
When S
1
is open and S
2
is in position b i.e. closed then the
capacitor C discharges and charge Q flows to the ground.
If the switches are ideal i.e. they open and close instantaneously
and resistance of the switches is zero when they are closed then charging
and discharging of the capacitor takes place instantly.
So let, I
in
= Charging current
and I
0
= Discharging current
Then, when S
1
is closed, I
in
flows instantly whose amplitude depends
on charge Q flowing per unit time. Hence I
in
occurs in pulse form, at the
146
instants when S
1
is closed. While when S
2
is closed, I
o
occurs in pulse form.
So the capacitor current consists of short bursts every time when switch is
closed. The waveforms of I
in
and I
o
, related to the closing and opening of
switches are shown in the Fig. 6.61.
Figure: Input and output current waveforms for as hched
capacitor filter.
The time between closing of switch S
1
or S
2
is called clock time,
denoted as T
CLK
. This can be controlled by an external clock.
Thus if switches are opened and closed at a faster rate, then
frequency of occurrence of current pulses will be high but their amplitudes
will remain unchanged. But due to frequent occurrence of current pulses,
the average current flowing will be more for higher switching rate. This
average current is rate of change of flux with respect to the clock time
T
CLK
.
147
( )
( )
( )
ave
CLK
in
ave in CLK
CLK
in
ave CLK
CLK
CLK
Q
I .... 6.32
T
CV
From 6.31 I C V f
T
V 1
.... 6.33
I C f
1
Where f
T

Consider a resistance to which voltage V

in
is applied, which drives
average current I
ave
, through the resistor. This is shown in the Fig. 6.62.
According to Ohms law,
in
ave
V
R
I

. (6.34)
Comparing (6.33) and (6.34) it can be concluded that the switched
capacitor filter can be effectively used to simulate the resistors. The value
of the resistor it is simulating can be written as,
( )
CLK
1
R .... 6.35
C f
Thus R is a function of capacitor C and the external clock frequency.

The capacitor C is constant hence the value of R can be adjusted as per
the requirement, by controlling the external clock frequency f
CLK
. It may be
noted that if V
in
is an a.c. signal then to simulate the R it is necessary that
the rate of change of V
in
must be much slower than f
CLK
.
Another Form of Switched Capacitor Filter
Consider another circuit shown in the Fig. 6.63 (a), for which we can
write,
( )
1 2
ave
V V
I .... 6.36
R
Another form of switched capacitor network can be used to simulate

the circuit shown in the Fig. 6.63 (a). Such a network is shown in the Fig.
6.63 (b).
148
When the switch is in position a a, then the charging current through
capacitor flows downwards and capacitor charges, to V
1
V
2
.
Q = C ( V
1
V
2
) .. (6.37)
When the switch alternates, the position of switch becomes bb and
current through capacitor reverses. And the charge on the capacitor
becomes,
Q = - C (V
1
V
2
) .. (6.38)
Now if switch position is chanted every T
CLK
seconds, then net flow of
charge during time T
CLK
will decide average current through capacitor.
( ) ( )
( )
1 2 1 2
ave
CLK CLK
1 2
ave
CLK
C V V C V V
Q Q'
I
T T
2C V V
I
T
1 1
] ]

( )
1 2
ave
CLK
V V
I
T
2C

1
1
]
. (6.39)
Comparing equations (6.36) and (6.39) we can say that the network
simulates the resistance R. The value of R is given by,
CLK
CLK
T 1
R ....(6.40)
2C C f

Thus the controlling the external clock frequency f
CLK,
any required
value of R can be simulated.
OPTOCOUPLERS:
In electronics, an opto-isolator, also called an optocoupler,
photocoupler, or optical isolator, is "an electronic device designed to
transfer electrical signals by utilizing light waves to provide coupling with
149
electrical isolation between its input and output".
[1]
The main purpose of
an opto-isolator is "to prevent high voltages or rapidly changing voltages
on one side of the circuit from damaging components or distorting
transmissions on the other side."
[2]
Commercially available opto-isolators
withstand input-to-output voltages up to 10 kV
[3]
and voltage transients
with speeds up to 10 kV/s.
[4]
An opto-isolator contains a source (emitter) of light, almost always a near
infrared light-emitting diode (LED), that converts electrical input signal
into light, a closed optical channel (also called dielectrical channel
[5]
), and
a photosensor, which detects incoming light and either generates electric
energy directly, or modulates electric current flowing from an external
power supply. The sensor can be a photoresistor, a photodiode, a
phototransistor, a silicon-controlled rectifier (SCR) or a triac. Because
LEDs can sense light in addition to emitting it, construction of
symmetrical, bidirectional opto-isolators is possible. An optocoupled solid
state relay contains a photodiode opto-isolator which drives a power
switch, usually a complementary pair of MOSFET transistors. A slotted
optical switch contains a source of light and a sensor, but its optical
channel is open, allowing modulation of light by external objects
obstructing the path of light or reflecting light into the sensor.
IC Optocoupler
150
Figure Circuit of MCT2E optocoupler
Optocouplers are available are available in a variety of packages,
the most common being six pin mini dual in line package. The
examples of such IC optocouplers are MCT2E and MCT2.
The MCT2E is optically coupled isolator consisting of a Gallium
Arsenide infrared emitting diode and an NPN silicon phototransistor,
mounted in a standard 6 pin dual in line package. The circuit is shown
in the figure.
Features of IC Optocoupler
151
Figure IC optocoupler with photodarlington
The various features of MCT2E are,
1) The isolation voltage of t 2500 V
2) High d.c. current transfer ratio
3) Total power dissipation is 250 mW.
4) Input to output isolation resistance of 1 x 10
11

5) Low cost dual in line package.
In the six pin dual in line package, optocoupler with
photodarlington is also available. It is shown in the figure.

Various Packages of IC Optocoupler
152
Figure Typical dual isolating optocoupler
Other than six pin dual in line package, 8 pin dual isolating
optocoupler is also available. The circuit of 8 pin dual isolating
optocoupler is shown in the figure. Similarly 16 pin, quad isolating
optocoupler is also available, which is shown in the figure.
Figure Typical quad isolating optocoupler
Advantages of Optocouplers
The various advantages of optocouplers are,
1. The electrical isolation between input and output circuit. The
coupling between input and output is through the beam of light.
There is a transparent insulating cap between the two elements
153
embedded in the design to permit the passage of light. So there
exists an insulation resistance of several mega ohms between input
and output circuit. This type of isolation is useful in high voltage
applications where the voltages of the input and output circuits
differ by several thousand volts.
2. The response times of optocouplers is so small that they can be
used to transmit data in the megahertz range.
3. Capable of wideband signal transmission
4. Unidirectional signal transfer means that output does not loop back
to the input circuit.
5. Easy interfacing with logic devices
6. Compact and light weight.
7. Much faster than the isolation transformers and relays.
8. As signal transfer is unilateral, changing load do not affect input.
9. The problems such as noise, transients, contact bounce etc. are
completely eliminated.
VOLTAGE TO FREQUENCY CONVERTER:
There are many instances where it is necessary to have available an
oscillator with a particular frequency. In lab you've "quartz clock"
oscillators, which produce a TTL-level output pulse at one particular
frequency. There are other types of oscillators available which can be
tuned by changing the frequency of a resistor or capacitor, or by applying
an external voltage. To begin with, let's look at the following circuit:
R
Reset
10.00V
+10.00V
V
th
0
V
th
One
shot
C
In this circuit, the input voltage is integrated by the integrator until it
reaches a set threshold determined by the "level adjust". When the
integrator output exceeds this threshold, the comparator output goes
"high", and the one-shot produces a "high" output signal. The "high"
154
output of the comparator turns on the MOSFET in parallel with the
integrating capacitor, making the first op-amp essentially a gain of "zero"
amplifier. The output of the op-amp is forced to zero, the comparator
goes back to its original "low" output, and the integration starts over
again. Thus, this circuit forms an oscillator, producing a "sawtooth"
waveform at the output of the ccomparator and a repetitive pulse at the
output of the one-shot. Since the integrator output has a constant slope
dV
dt

V
in
t
RC
, the time it takes to integrate from zero to the comparator
threshold Vth is directly proportional to Vth, so that the frequency of the
circuit can be easily controlled by varying Vth. This type of circuit, in
which the frequency of an oscillator can be controlled by an externally-
applied voltage, is called a Voltage-Controlled Oscillator, or "VCO". They
are also sometimes called "Voltage-to-Frequency" converters. This specific
type of oscillator is called a "regenerative" oscillator. Its frequency
depends on the comparator threshold, the value of the DC input voltage
Vin, and the values of the resistor and capacitor in the integrator.
(Note that a retriggerable one-shot must be used here- otherwise if
the integrator doesn't completely discharge, the circuit will "lock-up" at
the maximum or minimum integrator output voltage and stop
functioning!)
VCO's (or V-F converters) have many applications where one wants to
transmit the value of a continuously-varying signal over long wires,
without having to worry about noise pickup. The "analog" signal is used
to vary the frequency of the oscillator, and a digital signal is sent over the
long wires. At the other (receiving) end, a frequency-to-voltage converter
is used to convert the information back to an analog signal.
C
10.00V
One
shot
+2.1V
+10.000V
R
R
DigitalSignal
Input
Analog
Signal
Output
Lowpass
Filter
The frequency-to-voltage converter above operates by using a comparator
and a one-shot to give pulses of fixed length (although presumably the
155
pulses produced by the V-F converter and arriving at the F-V converter are
already a constant length, it's a good idea to clean them up a bit in this
way). Each pulse produced by the one-shot turns on the MOSFET for a
fixed length of time, allowing a fixed amount of charge (10.0 V/R*time) to
be applied to the inverting input of the op-amp. This scheme is sometimes
called a charge pump. The op-amp is acting as a low-pass filter, which
essentially integrates the input signal for a duration approximately equal
to RC. The effective time response of the circuit is determined by the RC
time constant of the low-pass filter.
V-F F-V
Analog
Signal
Analog
Signal
Verylongwire
In many applications, a fancier VCO with a sine-wave output is needed.
One common VCO is called a"state-variable" VCO. To understand the
state-variable VCO it is helpful to first look at the following circuit, which is
called a state-variable oscillator. It is related to a very useful type of
filter called a state-variable filter.
R
C
R
C
RF2
R
RF1
R1
V
in
The first op-amp inverts the input signal, thereby contributing a 180-
degree phase shift. The second and third op-amps each act as an
integrator and each contribute a 90-degree phase shift for input signals
which have a frequency f>>1/(2 RC) Note also that the output of the
first and second op-amps are both connected (through resistors) to the
inverting input of the first op-amps, so that there are two different
feedback paths
The response of this oscillator very sharply peaked at the frequency
where RC=1. The magnitude of this response is controlled by the
resistor RF1. The operation can be qualitatively understood by
considering that the first integrator contributes a 90-degree phase shift
(which tends to stabilize the circuit) and the second integrator contributes
156
a 180-degree phase shift (which tends to destabilize the circuit and drive
it into oscillation). By controlling the amount of feedback at 90-degrees
and a 180-degrees, the circuit will oscillate with some well-defined
amplitude and at a well-defined frequency. The utility of this circuit is
largely based on the fact that the output is sinusoidal.
Note that if there is no input signal applied at R1 (or if it is eliminated
completely), there will still be sufficient noise present (from Johnson noise,
etc.), such that the circuit will spontaneously oscillate at the resonant
frequency w=1/(RC). This is called the "free-running" frequency of the
oscillator.
Now, consider what happens if we add two analog multipliers in the
feedback loop.
R
R
R
C
R
C
100R
X
Y
XY
Multiplier
X
Y
XY
Multiplier
V
in
The multipliers control the total gain of the feedback system as well as the
relative amplitudes of the 180-degree and 90-degree components.
Although we won't do the analysis here, it shouldnt be a surprise that
applying a voltage at V
in
will change the frequency of oscillation. Such an
oscillator, in which the frequency of oscillation can be controlled by
applying an external voltage, is called a "voltage-controlled oscillator", or
"VCO". This particular kind of VCO is called a "State-Variable", or
"Quadrature" VCO. In this particular circuit, the oscillation frequency can
be varied from about
f
1
10
1
2RC
to
f 10
1
2RC
by applying external
voltages between 10 and 0.1 volts.
CONTROL ICS: TEMPERATURE CONTROL AND SMALL D.C. MOTOR
SPEED REGULATION BY ICS LIKE SL440, PA436, CA3059 - THEIR
BLOCK DIAGRAM AND OPERATIONAL DETAILS:
How do Temperature Controllers work?
To accurately control process temperature without extensive operator
157
involvement, a temperature control system relies upon a controller, which
accepts a temperature sensor such as a thermocouple or RTD as input. It
compares the actual temperature to the desired control temperature, or
setpoint, and provides an output to a control element. The controller is
one part of the entire control system, and the whole system should be
analyzed in selecting the proper controller. The following items should be
considered when selecting a controller:
1. Type of input sensor (thermocouple, RTD) and temperature range
2. Type of output required (electromechanical relay, SSR, analog
output)
3. Control algorithm needed (on/off, proportional, PID)
4. Number and type of outputs (heat, cool, alarm, limit)
ADB SL440/DMX/LC Softlux
ADB SL440/DMX/LC Softlux - Eight x 55w fluorescent lamps DMX/Local
Control c/w :
4-leaf Mirror Reflective 4 Flap Barndoor
Osram 55 watt 230/240 Volt 3200 K Tungsten Colour Temp
Studioline Tube or
Osram 55 watt 230/240 Volt 5200 K Daylight Colour Temp
Studioline Tube
Doughty T20900 TV Hook Clamp To Accept 29mm TV spigot
Doughty T73000 M10 29mm TV Spigot
Professional TV Grade Wire Safety Bond - ADB Type CAS120
2 meter detachable Power Cable without plug
Dimension : 695 x 680 x 605 mm
Net weight : 11.6 kg
158
MOTOR SPEED CONTROL USING SL440:
159
B.E./B.TECH DEGREE EXAMINATION, APRIL / MAY 2005
FOURTH SEMESTER
ELECTRONICS AND COMMUNICATION ENGINEERING
EC 244 LINEAR INTEGRATED CIRCUITS
PART A
1. Write down the characteristics of ideal operational amplifier.
2. Define: slew rate.
3. Mention two characteristics of instrumentation amplifier.
4. Mention two applications of Schemitt trigger.
5. What is amplitude modulation?
6. Define: lock range.
7. Draw the block diagram of delta modulation circuit.
8. Define: resolution of a D/A converter.
9. Name a timer IC and a voltage regulator IC.
10. Define ripple rejection with respect to voltage regulators.
PART B
11. (i) Explain the working of a current source with a circuit diagram.
(ii) Explain the operation of a basic differential amplifier.
12. (a) Explain the working of the following circuits:
(i) Instrumentation amplifier.
(ii) Sine wave oscillator.
Or
(b) Explain the working of
(i) Schmitt trigger
(ii) Antilog amplifier.
13. (a) (i) Explain the working of a four quadrant multiplier.
160
(ii) Write notes on any one compander IC.
Or
(b) (i) Explain working of PLL using appropriate block diagram
and explain any one application of the same.
(ii) Write notes on frequency synthesizers.
14. (a) (i) Explain the working of successive approximation A/D
converter.
(ii) Explain the working of a voltage to frequency converter.
Or
(b) (i) Explain a R-2R ladder type D/A converter.
(ii) Explain the working of a high speed sample and hold
circuit.
15. (a) Explain the working of the following circuits:
(i) Isolation amplifier
(ii) Voltage regulator
Or
(b) Write notes on:
(i) Fibre optic IC.
(ii) Sources of noise.
(iii) Low noise operational amplifiers.
B.E./B.TECH DEGREE EXAMINATION, NOV / DEC 2006
FOURTH SEMESTER
161
PART A
1. What are the characteristics of ideal operational amplifier?
2. Find out the frequency at which the gain of an operational
amplifier will be unity. The operational amplifier has a compensating
capacitor of 30 pF and g
m
of input stage is 45 micro mhos.
3. State the requirements of an instrumentation amplifier.
4. Name four applications of operational amplifier based comparators.
5. What is a four quadrant multiplier?
6. What is a PLL?
7. Name two analog switches. State a requirement of a device to
behave as analog switch.
8. Draw the block diagram of a delta modulator.
9. What are the advantages of switched capacitor filters?
10. Name the four kinds of noise.
PART B
11. (a) (i) Define CMRR, PSRR and slew rate of an
operational amplifier.
(ii) A 741 op-amp is used as a non-inverting amplifier with a
voltage gain of50. Find the typical output voltage that
would result from a common mode input with a peak
level of 100 mV. Assume a typical CMRR of 90 dB.
(iii) Find the slew rate of frequency compensated op-amp at
room temperature which has a unity cross-over
frequency of 5 MHz.
(b) (i) Explain the working of a simple current source.
(ii) Write notes on dominant-pole compensation used in op-
amps.
12. (a) (i) Explain the working of a Schmitt trigger circuit
with necessary diagrams.
(ii) Design a phase-shift oscillator for a frequency of
oscillation of 200 Hz. Assume C = 0.1 F.
162
Or
(b) (i) State the advantages and limitations of active filters.
(ii) A second order low-pass filter is to be designed with A
0
= 6, f
0
= 200 Hz and b = 0.6. Calculate the component
values.
(A
0
is the gain of op-amp, b/2 is the damping factor).
13. (a) Explain the operation of a four-quadrant amplifier.
Or
(b) (i) Explain the working of phase locked loop.
(ii) Explain one of its applications in detail.
14. (a) (i) Explain the working of binary weighted resistor D/A
converter.
(ii) Explain the working of any one type of voltage to
frequency converters.
Or
15. (a) Explain in detail about noise occurring in op-amp and make a
detail analysis of the same.
Or
(b) (i) Explain the internal details of 555 timer.
(ii) Explain its usage as astable multivibrator.
B.E./B.TECH DEGREE EXAMINATION, APRIL / MAY 2006
FOURTH SEMESTER
PART A
1. An opamp circuit shown in figure has differential gain Ad = 5 MV.
CalculateV
0
.
163
2. Compare the ideal and practical characteristics of opamp.
3. Draw the circuit diagram of an opamp integrator. Mention.
4. For the op amp shown in figure, determine the voltage gain.
5. What is a four quadrant multiplier? Draw the circuit diagram of a
squaring circuit using multiplier.
6. What is a compander IC? Enlist the features.
7. Which is the fastest A/D converter? Give reason.
8. An 12 bit D/A converter has resolution of 30 mv/LSB. Find the full
scale output voltage.
9. State the conditions required for designing a video amplifier.
10. What is a switched capacitor filter? Mention any two advantages.
PART B
11. (a) (i) Explain various stability criteria of opamp circuit.
(ii) Write a brief note on frequency compensation in op
amp.
Or
(b) (i) Determine the output voltage of a differential amplifier
having differential amplifier gain 2000 and the CMRR
100.
(ii) Explain the concept of current source applicable to
differential amplifier.
(iii) For the differential amplifier shown in figure find the
differential gain, common mode gain and CMRR.
164
Assume h
fe
= 100 h
ie
=1 K ohm.
Fig. Q.11 (b) (iii)
12. (a) (i) Determine the output voltage V
0
for the following circuit.
Fig. Q.12. (a) (i)
(ii) Briefly explain the working principle of Schmitt trigger.
Or
(b) (i) With circuit diagram discuss the following applications of
op amp.
(1) Voltage to current converter
(2) Precision rectifier
(ii) Draw the schematic of a linear IC saw-tooth wave
generator and explain the principle of operation.
13. (a) (i) Explain the working principle of Gilbert cell multiplier
circuit.
(ii) With block diagram discuss the principle of operation of
NE 566 PLL circuit.
Or
(b) (i) Explain PLL as a frequency synthesizer.
(ii) With circuit diagram explain the working of a NE 566
voltage controlled oscillator.
14. (a) (i) Explain the working principle of high speed sample and
hold circuit.
(ii) For an 8 bit successive approximation type A/D
165
converter is driven bya 2 MHz clock. Find the conversion
time.
Or
(b) (i) Briefly explain the working principle of successive
approximation type ADC.
(ii) An 8 bit DAC has a step size of 10 mv. Determine the
full scale output voltage and percentage resolution. Find
the output voltage for the input of 01010101.
15. (a) (i) A 555 timer configured in astable mode with R
A
= 2 K
ohm, R
B
= 4 K ohm and C = 0.1 F. Determine the
frequency of the output and duty cycle.
(ii) Write a note on switched mode power supply.
Or
(b) (i) With circuit diagram explain the working principle of IC
723 voltage regulator.
(ii) Explain the working principle of isolation amplifier IC
ISO 100.
B.E./B.TECH. DEGREE EXAMINATION, NOV/DEC 2007.
FOURTH SEMESTER
PART A
1. Find the maximum frequency for an opamp with sine wave output
voltage of 10 V peak and slew rate is 2 v/ s.
2. What do you mean by input offset current and input offset voltage?
3. Find V
0
for the following circuit shown in figure
Fig.Qn(3)
4. What is an antilog amplifier? Draw the circuit diagram of an antilog
amplifier
166
5. Draw the block diagram of NE566 voltage controlled oscillator.
6. What is an operational transconductance amplifier? Draw the
schematic
7. Calculate the quantizing error for an 8 bit A/D convertor with full
scale input voltage of 2.55 V.
8. What is a sample and hold circuit? Mention any two applications
9. What is a stager tuned amplifier?
10. What is the need for using for using switched capacitor filters
in MOS technology?
PART B
11. a) (I) Discuss the ideal characteristics of an opamp. Compare
with practical opamp.
(ii) Briefly explain different types of frequency compensation
techniques applied to opamp circuit.
Or
(b) (i) Explain the concept of Wildhar current source used in opamp
circuits.
(ii) For the noninverting opamp shown in figure, find the output
voltage V
0
Fig. Qn.11 (b) (ii)
12. (a) (i) Design a second order Butterworth active high pass
filter for a cut off frequency of 5 kHz.
(ii) What is a precision diode? With circuit schematic explain the
working principle of
full wave precision rectifier.
167
Or
(b) (i) With diagram explain the working principle of ICL 8038
function generator
(ii) Explain how a compander can be used as a zero crossing detector
13. (a) (i) briefly explain variable transconductance amplifier
(ii) How a PLL used as voltage multipliers?
Or
(b) (i) Write a note on compander ICs.
(ii) How a PLL used as frequency synthesizer?
14. (a) (i) With circuit schematic explain analog switches using FET.
(ii) Explain the working principle of duals slop A/D converter.
Or
(b) (i) Write short notes on voltage to time converters.
(ii)What are different sources of error in D/A converter?
15. (a) (i) Briefly explain LM 380 audio amplifier.
(ii) Discuss about protection circuits used in IC regulators
Or
(b) (i)What are the design consideration of video amplifier?
(ii) Briefly explain the working principle and the frequency response
characteristics of video amplifier IC.
B.E./B.TECH. DEGREE EXAMINATION, APRIL/MAY 2008.
FOURTH SEMESTER
PART A
1. Define unity gain band width of an OP-Amp.
2. Define slew rate. What causes it?
3. Draw the circuit diagram of a non-inverting amplifier.
4. Give any four applications of a comparator.
5. What is FSK technique?
6. Draw the circuit of AM detector using PLL
7. Which type ADC is the fastest? Why?
168
8. What is adaptive delta modulation?
9. What is a switched capacitor filter?
10. List the characteristics of optocoupler.
PART B
11. (a) What is a current mirror? Discuss in detail the Wildar current
sorce.
Or
(b) Explain
(i) Band gap reference.
(ii) Methods of improving slew rate
12. (a) (i) Explain the operation of Instrumentation amplifier
(ii) Detail the working of Log and Antilog amplifiers.
Or
(b) With a neat circuit, explain the operation of Schmitt trigger.
13. (a) (i) Explain PLL used as an Am detection.
(ii) Explain how frequency multiplication is done using PLL
Or
(b) (i) With a neat sketch, explain the working of variable
transconductance multiplier.
(ii) Write notes on frequency synthesizer.
14. (a) (i) Explain the working of Dual scope ADC.
(ii) With a neat circuit, explain the operation of a Binary
weighted resistor D/A converter.
Or
(b) (i) Write notes on Analog switches
(ii) Explain Delta modulation. what are its advantages and
disadvantages?
15. (a) What are the various blocks that form a Basic Voltage
Regulator? Explain the series and shunt voltage regulator.
List advantages of IC voltage regulators.
Or
(b) (i) Discuss the operation of IC 555 as a monostable
multivibrator. Draw the waveform and explain.
(ii) Draw the functional block diagram of switching regulator
and explain.
169
B.E./B.TECH. DEGREE EXAMINATION, APRIL/MAY 2008.
FOURTH SEMESTER
PART A
1. Define slew rate.
2. What does the term linear circuit generally convey?
3. Define CMRR.
4. What is precision rectifier? Give the circuit.
5. Define lock range and capture range of PLL
6. What is frequency synthesizer?
7. Draw the sample and hold Circuit
8. What is the principle of operation of voltage-to-time conversion?
9. How are the internal noises within ICs classified?
10. Give the basic principle of switching regulators.
PART B
11. (a) (i) Explain the frequency response of OP-AMP
(ii) Derive the open loop voltage gain as a function of frequency.
Or
(b) (i) Explain how the feed-forward compensation extends the
bandwidth of an OP-AMP.
(ii) Write about the temperature independent biasing
provided for differential amplifiers
12. (a) (i) Design a differentiator to differentiate an input signal
that varies in frequency from 10 Hz to about 1 KHz.
(ii) If a sine wave of 1 V peak at 1000 Hz is applied to the
differentiator, draw its output wave form.
(iii) Give the basic differentiator frequency response.
Or
(b) (i) Design a band pass filter using Op-Amp to have f
L
=500
Hz and f
H
=2 KHz with pass band given of 4.
170
(ii) Explain the triangle wave generator with neat diagram
and drive the time period.
13. (a) (i) Explain voltage controlled oscillator with its block
diagram and connection diagram using VCO 566 IC.
(ii) Write short notes on variable trans-conductance
multipliers.
Or
(b) (i) Explain the working of PLL with neat diagrams.
(ii) Write short notes on FSK modulator and demodulator.
14. (a) (i) Explain dual slope A/D Converter with circuit.
(ii) Compare binary weighted DAC with R-2R ladder network DAC.
Or
(b) For a 4 bit R-2R ladder network, determine the size of each
step if R= 10K and R
F
=40 K and V
cc
=t 15V. Calculate the
output voltage for D
0
=1, D
2
=0,D
2
=1,D
3
=1 if bit 1 is applied
as 5V and bit 0 is applied as 0 V.
B.E. / B.TECH. DEGREE EXAMINATION, NOV / DEC 2008
FOURTH SEMESTER
PART A
1. Define slew rate of an operational amplifier.
2. State the characteristics of an ideal operational amplifier.
3. Design a noninverting amplifier with a gain of 3 with an input
171
resistance of10K .
4. State the characteristics to be met by an instrumentation amplifier
intented to be used for medial application.
5. What is meant by frequency shift keying?
6. What is a frequency synthesizer?
7. Draw a sample and hold circuit.
8. Define quantization.
9. What is an op to coupler?
10. State any four sources of noise.
PART B
11.(a) (i) Explain the working of a difference amplifier with active load.
(ii) The CMRR of an op amp is 10
4
. Two sets of signals are
applied to it. First set is V
1
= 540 V and V
2
= 500 V. Calculate the
percent difference in output voltage for the two sets of signals.
(or)
(b) Explain the methods of frequency compensation used in
operational amplifiers.
12.(a) Explain the working of:
(i) Instrumentation amplifier
(ii) Full wave precision rectifier.
(or)
(b) Explain the working of (i) Schmitt trigger (ii) Monostable
multivibrator using op amp.
13.(a) (i) Explain the working of a voltage controlled oscillator.
(ii) Write notes on compander IC.
(Or)
(b) (i) With block schematic explain the working principle of PLL.
(ii) How is PLL used as frequency multiplier?
14.(a) (i) Discuss the working of a 8 bit weighted D/A converter.
(ii) Discuss on delta modulation.
(Or)
(b) (i) Explain the working of a successive approximation A/D converter.
(ii) Write notes on ADM.
15.(a) (i) Explain the working of a video amplifier.
172
(ii) In an astable multivibrator using 555 timer, R
A
= 2.2. K , R
B
= 6.8 K and C = 0.01 F. Calculate (1) t
HIGH
(2) t
LOW
(3) free
running frequency (4) Duty cycle.
(or)
(b) (i) Explain the working of switched mode regulators.
(ii) Explain how current boosting is achieved in 723 IC.
B.E. / B.TECH. DEGREE EXAMINATION, NOV / DEC 2008
FOURTH SEMESTER
PART A
1. State the applications of band gap reference circuit.
2. What is a current mirror? What are its advantages?
3. What is a V to C converter?
4. Draw the circuit of an integrator.
5. Define lock range and capture range.
6. List the applications of PLL?
7. What is an analog switch?
8. Define resolution of DAC.
9. Name two applications of an isolation amplifier.
10. What are the advantages of a switched capacitor filter?
PART B
173
11. (a) (i) Explain the working of a Wilder current source.
(ii) What is slew rate? Discuss the methods of improving slew
rate.
(or)
(b) (i) What is an active load? Explain the CE amplifier with active
load.
(ii) Explain pole zero compensation.
12.(a) Explain a monostable amplifier. Deduce the expression for a
closed loop voltage gain of a non inverting amplifier.
(or)
(b) (i) Explain the operation of a Schmitt trigger.
(ii) Explain log and antilog amplifiers.
13.(a) Explain a four quadrant Gillbert cell multiplier circuit.
(Or)
(b) (i) Explain VCO with suitable waveforms.
(ii) Write short note on frequency synthesizer.
14.(a) (i) Explain Sample and Hold circuit with suitable sketches.
(ii) Explain binary weighted resistance D/A converter
(Or)
(b) (i) With a neat sketch explain the working of dual slope A/D
converter.
(ii) What is delta modulation? Explain Adaptive DM.
15.(a) (i) Explain the operation of a monostable multivibrator using 555
timer.
(ii) Write short notes on Optocoupler.
(or)
(b) (i) Explain F/V convertor with a neat block diagram.
(ii) Draw the circuit of a switched capacitor Integrator and deduce
the expression for the characteristic frequency of the
Integrator.
174
DEGREE EXAMINATION, APRIL / MAY 2008
FOURTH SEMESTER
PART A
1. Define unit gain bandwidth of an OP - Amp.
2. Define slew rate. What causes it?
3. Draw the circuit diagram of a non inverting amplifier.
4. Give any four applications of a comparator.
5. What is FSK technique?
6. Draw the circuit of AM detector using PLL.
7. Which type ADC is the fastest? Why?
8. What is adaptive delta modulation?
9. What is a switched capacitor filter?
10. List the characteristics of optocoupler.
PART B
11.(a) What is a current mirror? Discuss in detail the Wildar current
source.
(or)
(b) Explain:
(i) Band gap reference.
(ii) Methods of improving slew rate.
12.(a) (i) Explain the operation of Instrumentation amplifier.
175
(ii) Detail the working of Log and Antilog amplifiers
(or)
(b) With a neat circuit, explain the operation of Schmitt trigger.
13.(a) (i) Explain PLL used as an Am Detection.
(ii) Explain how frequency multiplication is done using PLL.
(Or)
(b) (i) With a neat sketch, explain the working of variable
transconductance multiplier.
(ii) Write notes on frequency synthesizer.
14.(a) (i) Explain the working of Dual scope ADC.
(ii) With a neat circuit, explain the operation of a Binary weighted
resistor D/A converter.
(Or)
(b) (i) Write notes on Analog switches.
(ii) Explain Delta modulation. What are its advantages and
disadvantages?
15.(a) What are the various blocks that from a Basic Voltage Regulator?
Explain the series and shunt voltage regulator. List advantages of
IC voltage regulators.
(or)
(b) (i) Discuss the operation of IC 555 as a monostable multivibrator.
Draw the waveform and explain.
(ii) Draw the functional block diagram of switching regulator and
explain.
B.E./ B.TECH. DEGREE EXAMINATION, APRIL/MAY 2010
FOURTH SEMESTER
176
EC2254 LINEAR INTEGRATED CIRCUITS
(REGULATION 2008)
PART A
1. What is an integrated circuit?
2. What is current mirror?
3. Give the schematic of op-amp based current to voltage converter.
4. Draw the circuit diagram of differentiator and give its output equator.
5. What is a VCO?
6. Draw the relation between the capture ranges and lock range in a
PLL.
7. Define resolution of a data converter.
8. Give the advantage of integrating type ADC.
9. Draw the internal circuit for audio power amplifier.
10. What are the three different wave forms generated by ICL8038?
PART B
11. (a) (i) Define CMRR. Draw the circuit of an Op-amp differential
amplifier and give the expression for CMRR.
(ii) Define Slew Rate. Explain the cause of slew rate and derive
an expression for Slew rate for an op-amp voltage follower.
Or
(b) Briefly explain the various processes involved in fabricating
monostich IC which integrates bipolar transistor , diode, capacitor
and resistor.
12. (a) (i) Design a first order Low-pass filter for cut-off frequency of
2KHz and pass-band gain of 2.
(ii) Explain a positive clipper circuit using an Op-amp and a
diode with neat diagrams.
Or
12. (a) (i) Design a circuit to implement V
0
= 0.545 V
3
+ 0.273 V
4

1.25V
1
-2V
2
.
(ii) Draw and explain a simple Op-amp differentiator. Mention
its limitations. Explain with a neat diagram how it can be
overcome in a practical differentiator. Design an Op-amp
177
differentiator that will differentiate an input signal with
maximum frequency f
max
= 100 Hz.
13. (a) (i) With a neat diagram explain the variable transconductance
technique in analog multiplier and give its output equation.
(ii) Briefly explain the working of voltage controlled oscillator.
Or
(b) What are important building block of phase locked loop (PLL)
explain its Working?
14. (a) (i) Explain the working of R-2R ladder DAC
(ii) Explain the working of success approximation ADC.
Or
(b) (i) A dual slope ABC uses a 16-bit counter and a4 MHz clock
rate. The maximum input voltage is +10V. The maximum
integrator output voltage should be -8V when the counter
has recycled through 2
n
counts. The capacitor used in the
integrator is 0.1F. Find the value of resistor R of the
integrator.
(ii) What is the sample and hold circuit? Briefly explain the
construction and application
15. (a) (i) How is voltage regulators classified? Explain a series voltage
regulator?
(ii) What is an optocoupler? Briefly explain its characteristics.
Or
(b) With a neat circuit diagram and internal functional diagram
explain the working of 555 timers in astable mode.
*************************
178

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UNIT I

INTRODUCTION TO OPERATIONAL AMPLIFIERS

is selected so that the compensated transfer function

is selected so that the

For most general purpose op-amps few power bandwidth ranges

Where I is the maximum current furnished by the op amp to the capacitor

Connection diagram of IC 566 and derive the frequency of

SQUARE WAVE GENERATOR:

It is evident from Eq. (8.2) that the timing interval is independent of

where i is the current supplied by the constant current source. Further,

In datasheet, it is expressed in decibels (dB)

Consider a resistance to which voltage V

Thus R is a function of capacitor C and the external clock frequency.

Another form of switched capacitor network can be used to simulate

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