1 Microprocessors & microcontrollers

This course is really about microcontrollers (8051), not about micro-

processors such as the PC 8086.
Intel 8051 microcontroller
microprocessors IBM PC, general purpose, multi-chips required
for all the functions.
David Wilson microcontrollers true computer on a chip, logic functions, bit ad-
dressing, small cheap & fast. True “computer on a single chip”.
8051 Architecture & basic programming model Block diagram of a microprocessor & controller

ALU
S TUDENT V ERSION
Accumulator microprocessor
Working registers
Department of Electrical Engineering
University of Karlstad prog counter stack ptr

clock interrupt circuits

March 1998
timer
ALU I/O port

ACC
W.Reg. internal I/O port micro-controller
ROM

internal interrupt
RAM
stack ptr clock
PC

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Intel 8051 microcontroller
1/48 K ARLSTAD 2/48 1 Microprocessors & microcontrollers K ARLSTAD
 Microcomputers & microcontrollers
Essential elements of any computer are:
CPU or central processing unit
memory for both data and program
I/O or input/output system
Various different architectures exist depending on the application.
Mini-computer all 3 systems mounted on a board
Micro-computer 2 systems on a single chip.
Micro-controller All systems on a single chip.
The Intel 8051 is an example of a micro-controller.
David Wilson Intel 8051 microcontroller
3/48 1 Microcomputers & microcontrollers /2
2 An micro-controller application
DIW
Measuring house heating
Motivation I have just moved into a villa, and my electricity bill is
much higher than it was in Australia! So I would like to monitor the
temperature inside and outside of my house in different rooms over
at least 48 hours.
Requirement Use one 8051 as a data logger and local storage de-
vice. It should measure around 5 temperatures say every minute,
and store them so I can load them up from the 8051 via a serial ca-
ble to my PC every couple of days.
Heat distribution in my oven & fridge
Motivation I have an old oven without a fan, and I discover that
when baking, you must be very careful as to where you place the
food (near the top, or near the bottom etc.) I would like a time
varying 3D temperature map of my oven.
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K ARLSTAD 4/48 2 An micro-controller application K ARLSTAD
 3 Intel 8051 microcontroller 4 8051 pin layout
The 8051 is a Single Chip Computer or microcontroller made by The 40 pin package has a pin DIP (dual in-line package) layout as
Intel. It is one of the most widely used microcontroller chips in the follows:
world.

 A stand alone, high performance, single chip computer for con-

troller applications

 Small, cheap & 40 pins. (# of pins increases size & cost.)

 64k program memory
 64k data memory
Our 8031 version is very similar to the generic 8051, but it has some
features attractive for proto-typing:





 But a 44 pin square layout exists and the more advanced members
of the 8051 family have slightly different layouts.
For what is inside this ‘black-box’, see following overheads.

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5/48 3 Intel 8051 microcontroller K ARLSTAD 6/48 4 8051 pin layout K ARLSTAD
 5 8051 Controller 6 8051 CPU architecture
A minimal 8051-based controller needs only the following compo-
nents:

1.

2.

3.

Basic SBC51

8051 CPU Memory

Address bus -
A[0..15] A[0..15]
D[0..7]  - D[0..7]
- Read#
- WR#


- P3.[0..7]
- P1.[0..7]
input/output

 Buses (groups of 8) are wide lines, single lines are bits

 Address (2 buses) give 16 bits (0x0000 – 0xFFFF)
 Data is bidirectional, address unidirectional from CPU to mem- Compare what crosses the dashed line with the pin-out diagram
ory given previously.

 Read & write strobes one way.

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7/48 5 8051 Controller K ARLSTAD 8/48 6 8051 CPU architecture K ARLSTAD
 Ref Ayala, p56–57

8051 architecture given previously contains the following:

Registers  8bit CPU registers (called the ‘A’ register or accumu- 7 The Single-Board-Computer SBC51
lator & B register)
We have a laboratory proto-type single board computer based on
 16bit program counter & data pointer the Intel 8051 called a SBC51. However we will use a PC for editing,
 8bit program status word storage of source programs and assembling. We will “dump” the
 Control registers compiled code from the PC to SBC51 using a serial cable.
SBC51 board components
Internal ROM of zero (8031) to 4K (8051)

Internal RAM of 128 bytes Serial to PC

 4 register banks Port #1

 16 bytes (bit addressable) Display

 80 bytes of general purpose scratch pad. 80C32

Single
Timers & counters (16 bits) step
reset
EPROM

switch
8255

Analogue in/out switches Digital out

See the component layout on p58, and the circuit diagram follow-
ing. Also read chapter 9 of Ayala.

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9/48 6 8051 architecture /2 K ARLSTAD 10/48 7 The Single-Board-Computer SBC51 K ARLSTAD
 Getting started with the SBC51 Read this before the first laboratory.
A picture of an equivalent single board computer proto-type kit. 1. Connect the PC port COM1 to the SBC port P1 with the serial
(Not exactly the same as what we have in the lab) cable, 9600, no parity & 1 stop bit. Use MSD.EXE to check &
mode to check your settings.

2. Turn on the SBC51 & reboot the PC under DOS. (It will give
strange results under Windows or NT, possibly not communi-
cating)

3. Choose the SBC51 or andra program in the boot menu, and

then start the program:

c:> cd sbc51\work
c:> sbc51\work\sbc.exe

4. Load your program using the LOAD FILE menu.

This configuration has 5. Edit your file if necessary, use ALT-h for help.
 80C32 (square package) with B ASIC & external ROM 6. Assemble your program to a relocatable object file, a R03, then
 liquid crystal display (LCD) screen, 2 by 16 link to an Intel hexadecimal HEX file.

 Serial connection (to dump programs & data) 7. Choose TERMINAL and

 hexadecimal keypad (4  5) buttons (a) press ALT-C to set up the serial communication to the
SBC51.
(b) Press the RESET button on the SBC51
(c) Press ALT-L to download the hexcode.

8. Start with the laboratories, p3 1.1

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11/48 7 A single board computer /2 K ARLSTAD 12/48 7 Getting started with the SBC51 /3 K ARLSTAD
 Data memory internal 256 bytes is divided into two parts: general
scratch and the special function registers SFRs. (See description fol-
lowing).
8 8051 Memory types
Data memory
FFFF
The 8051 has two separate memory blocks, for data and program.
Since both blocks have the same address, this is called a Harvard 8 FF
>
< 128 bytes
architecture. direct addressing only
> internal
: SFR
64K
8 80
and
external
Separating the program memory from the data memory improves >
< 7F
128 bytes
direct & indirect addressing
reliablility since we cannot inadventently overwrite the program >
: internal
code, and allows us to use program ROM, or read only memory. 00 00

The 128 bytes in lower internal RAM have the following structure:
Program memory normally we will have 4K on the chip (but not in
the case of the 8031)
7F

scratch pad
Program memory .................................




20 9 bit addressable area
.................................

60K external bank #3 1F

................................. >
=
or 64K external bank #2 ................................. register banks
bank #1 ................................. >
;
bank #0 07 00
4K internal 7 6 5 4 3 2 1 0
8051 8031
(our proto-type version)
 Only one of the 4 register banks can be active at any particular
time
Data memory all 64K is off the chip except for (a miniscule 128
bytes).  Which one is active is given by flags in the PSW

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13/48 8 8051 Memory types K ARLSTAD 14/48 8 Data memory /2 K ARLSTAD
 9 Special Function Registers Program Status word (PSW)
Ayala, p62
The Special Function Registers (SFRs) contain memory locations
that are used for special tasks. (They should not be used for gen- The PSW is the most important of the SFRs. It is a byte register
eral purpose tasks.) which holds 8 bits that can addressed indivdually. Each bit is re-
Each SFR occupies internal RAM from 0x80 to 0xFF, (but some areas ferred to as a flag.
are empty!) They are 8 bits wide. Some examples are: Flags can be either set (1) or cleared (0). This is more efficient than
A register or accumulator is used for most ALU operations & exter- using an entire byte memory location for a binary variable.
nal moves The PSW is divided up as follows:
7 6 5 4 3 2 1 0
B used for mltiplication & division and can also be used for general
CY AC F0 RS1 RS0 OV – P
purpose storage
Note:
PSW Program Status Word is a bit addressable register. Refer to the
manual for the description of the bit fields.
 We start numbering from zero and go right to left (MSB, or most
significant bit first)
See p48
 Flags are zero and one (not 1 & 2)
Two special 16-bit registers (double registers):  One flag should not be used, but is reversed for future use. Use
at your own peril
PC or program counter. This is not directly addressable, nor does it
have a memory location  Address as PSW.3 for RS0 for example.
DPTR or data pointer. Is accessible two 8-bit registers: DPTRLow Each of the flags has a special function, consult the manual.
and DPThigh. Question What flags are set when the PSW holds 0x7C ?

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15/48 9 Special Function Registers K ARLSTAD 16/48 9 PSW /2 K ARLSTAD
 Bit addressable SFRs 10 8051 flags
Some special function registers are bit addressable. (This makes it
easier to program.) Flags are stored in the PSW, so will be affected if you change it (ex-
cept the parity flag).
The byte addresses are always multiples of 8, or they all lie in column
Arithmetic flags:
0 of the SFR register block. The bit addresses are just appended onto
the byte address.  C, AC & OV, (Carry, auxiliary carry & overflow)
So the fouth bit of the accumulator is Acc.3.  Increment/decrement do not effect the math flags.
byte address of the accumulator is 0E0h
so, the bit address is:  I.e. no OV if we INC A from FFh to 00h.
Acc.3 = 0E0h
 inc DPTR, note no DEC version.
+ 5 Addition
= 0E5h C if carry out of bit #7

AC is set if carry from bit 3 to bit 4. (Used in BCD addition)

OV is set if carry out of bit 7 but not bit 6

Question: How does this explains the (incorrect) command CLR or
B? is set if carry out of bit 6 but not bit 7.
In other words:
OV = C7 XORC6

Signed addition & subtraction is complicated, and you will need to

study the flags carefully.
Use pre-tested subroutines for your arithmetic routines if possible.
(See text books, or libraries on the internet.)

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17/48 9 Bit addressable SFRs /3 K ARLSTAD 18/48 10 8051 flags K ARLSTAD
 11 Accessing external memory 12 Prototyping 8051 design
Storage problems? What happens if our program is larger than Ayala, Chapter 9

4096 bytes of code?

For many small applications where we might want to change the
We have the ‘ROMless’ 8031 version, so we must
ROM code, we would like to use external EPROM, which means:
In assembler we use the movx (move external) to access the data
block, and movc to fetch from code memory.
 We have lost the use of ports 0 and ports 2 since they must be
used to interface with external ROM and not available for I/O.
We have two separate read signals, RD, (read) and P SEN , (pro-
gram send enable). The bar means that it is active low, (when zero,
 We may need external RAM (since the 128 bytes may not be
enough for our application), which means that we have lost
will do something).
port 3.6, WR, and 3.7, RD.

 Any serial communication requires 3.0 (RXD) and 3.1 (TXD)

Loss of ports leaves us with:

1. All of port #1, and

2. Port P3.2 – P3.5

for general purpose I/O and external interrupts and timing inputs.

Question How do we recover the use of the lost ports?

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19/48 11 Accessing external memory K ARLSTAD 20/48 12 Prototyping 8051 design K ARLSTAD
 Programmable Logic Devices
The PROM chip is an example of a Programmable Logic Device
PLD. Once programmed, it will retain the program even when the
power is turned off. 13 Reading to Ports
 One-time programmable devices uses tiny fuses which are 1. Store the address of the memory mapped port into the DPTR
burnt or blown (or we can use antifuses which have the same register, and
end function. Circuit size is 10 that for EPROMS.
2. indirectly address this through Acc.
 Eraseable Programmable read Only memory (EPROMS) can be
; Reading & writing from a PORT
re-programmed. This uses a modified MOS transistor with a
MOV DPTR, #0F012h; address to read digi-
floating gate that when uncharged does not effect the normal
tal input
operation. However if it is subjected to (high) +12V, then a
MOVX A, @DPTR ; read the val-
charge will move into the 2nd transistor which is stable (will
ues into Acc
last a decade).
Reprogram by subjecting the cells to UV light (via an expensive
MOV DPTR, #0F011h; address of LED outputs
ceramic window on top of the package). Wiping time takes
MOVX @DPTR, A ; write this value back out agai
about 20 minutes.
The actual values of the address are decided by the designed of the
 EEPROM or Electrically erasable proms are about 2.5 times particular circuit board, (SBC in our case).
larger than eproms, and are quicker to clear.

 FLASH proms are much quicker to erase (hence the name), and
can be reprogrammed while still on the circuit board. Suitable for
easy upgrading by the public of ROM chips in Modems and
PCs.

On the SBC51 board we have a 32k EPROM that is reprogrammed

by UV light. This holds the monitor program. (We don’t have the
source to this, but we could reverse assemble it.)

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21/48 12 Programmable Logic Devices /2 K ARLSTAD 22/48 13 Reading to Ports K ARLSTAD
 Ayala, p64, p129–130

Stack & the stack pointer makes housekeeping easier for certain
tasks like storing & retrieving numbers quickly. The name comes
14 Subroutines
from a ‘stack’ of dishes in a cafeteria or a stack of cigarettes at the
Question Subroutine overheads slow a program down so why use them? supermarket checkout.

To store data on the stack you PUSH it on.

To retreive data, you POP it off

Subroutines do exist in assembler programming using the CALL op-
code, but you must take care of the “housekeeping” yourself.
 All variables are global, so they may get altered or destroyed.
This includes the PSW, register banks etc.
The Stack is a small amount of internal ram. The start of the stack
is held in the stack pointer, SP. As you push data, the stack grows
upwards (to higher locations) in ram memory.
The following occurs when you store some data on the stack & then
pop it off again.

 You will need to save all variables before calling, and restore
them after returning from the subroutine.

 The stack is a special memory location (stack of registers) that

you can use. (see OHs following)

 The processor uses the stack to remember the address where to

return to after the subroutine has finished.

 The stack is pointed to by the stack pointer, SP.

 Near, Long (or far) and absolute calls are possible.

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23/48 14 Subroutines K ARLSTAD 24/48 14 stack /2 K ARLSTAD
 Ayala, p130 15 The stack & subroutine calls
Stack Note the cautions regarding usage! Ayala, p177

 The stack is reset to 07h, but since this will overwrite the reg-
ister banks, and bit area, we normally move it ‘out of harms
way’, to say 3Fh. (Done by the monitor program)
 If you push too many times, you will run off the end of internal
RAM adress 07h which will result in errors.
 SP “rolls over” from FFh to 00.
 Use direct address, not register names R1, R2 etc since the stack
has no way of knowing which register bank is in use at the
time.
 Use PUSH Acc not PUSH A.
What happens when a subroutine is called (including a hardware inter-
rupt) ?
1. The PC is incremented and this becomes the return address,
i.e. the spot the CPU will return to after it has completed the
subroutine.
2. The 16bit return address is pushed onto the stack, low byte
first,
3. during which the stack pointer SP is incremented twice.
4. The subrouine address is placed in the PC and the subroutine
is executed, until . . .

5. a RET return instruction is encounted, then

6. The CPU POPs the stack twice to recover the return address,
and places it in the PC. (Sp is decremented twice)

7. CPU starts from the return address . . .

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 Question What is the maximum number of nested subroutine calls 16 Interrupts
we can make?
Question What are the advantages/disadvantages of long calls as Interrupts are just special subroutines that may (or may not) be
opposed to short calls? called explicity.
Why have them?

1.

2.

3.

If conditions are “right”, when an interrupt occurs, then the proces-

sor will stop what it is doing, and jump to a specific place in mem-
ory (decided by the Intel 8051 designers) hooked that that particular
interrupt. (See following OH.)
It is up to the programmer to make sure that you supply a sensible
further course of action. This is called the interrupt handler routine
or interrupt service routine, ISR.
Types of interrupts
On the 8051 we have 2 timers or counters and 2 external interrupts.

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27/48 15 Subroutine review questions /2 K ARLSTAD 28/48 16 Interrupts K ARLSTAD
 Interrupt programming

 Signals or conditions generated external to the main program
– External events such as a change in a logic value
– Overflow of a counter
– Arrival of data at the serial port.
 Interrupts can be enabled or disabled by the programmer. (Al-
though some interrupts are non-maskable.)
Note that the computer does not explicitly call the ISR, this is de-
termined by outside events, & we cannot predict exactly where &
when it will call.
This splits out program into 2 parts, foreground & background
tasks.
Foreground tasks are under program control & are called explicitly
Background tasks are called via interrupts.

Interrupts on the 8051 This makes the writing of complex real-time controller applications
much easier.
 IE0 - external interrupt #0. Provided by an input pin on the
Relocating the ISRs Normally ROM (or EPROM) occupies low
chip.
memory, so the ISR is relocated to a higher address. (Otherwise
 IE1 - external interrupt #1. Provided by an input pin on the we would need to re-program the ROM everytime we wanted to
chip. change the ISR in our prototype.)
 TF0, TF1 - Timer/Counter Interrupts. Generated by internal
The Interrupt vector table
The interrupt table has been moved (by the monitor program).
timer/counters
Name 8051 relocated on the SBC51
 RI,TI Communication port interrupts. Indicates that a charac- INT 0 0003 single-step function
ter has been received or the buffer is empty and a character cna TIMER 0 000B 200B
be transmitted. INT 1 0013 2013
TIMER 1 001B 201B
Each interrupt forces the processor to jump to a different place in
serial port 0023 2023
memory.
Usage is by the LCALL op-code. However you must supply a RETI,
a return from interrupt op-code at the end of your interrupt handler
subroutine.
In our case we do a Long jump to +2000h.

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29/48 16 8051 interrupts /2 K ARLSTAD 30/48 16 ISRs /3 K ARLSTAD

17 Timers & counters
Timers (clocks) and counters are a good example for the advantages
of interrupts. Many applications require the counting of external
events;
 Calculate the frequency of an external pulse train, or
 generate a precise delay between other computer actions (say
for digital control)
Could use software techniques, but this keeps the processor occu-
pied. Better to use interrupts & the two 16-bit count-up timers. Can
either be programmed to:
TCON Timer control SFR contains timer 1&2 overflow flags, exter-
nal interrupt flags, timer control bits, falling edge/Low level selec-
tor bit etc. (refer documentation)
TMOD timer mode SFR is two four-bit registers (timer #1, timer #0).
Select timer/counter & various modes.)
Applications Say we want to count a specified number of events
(clock pulses or external events), then
1. Store the start number in the counter. (Value = max count- de-
sired count+1)
2. Counter automatically increments (in the background)
3. When it rolls over to zero, it will ste the timer flag.

1. count internal : : : 4. Test the flag in the program, or generate an interrupt.

2. count external : : :
Timing configures the counter to count the internal clock fre-
quency/12. (E.g. if fc = 6:0Mhz, then the timer clock will have
All counter action is controlled by the TMOD (timer mode register)
a frequency of 500kHz.)
and the TCON (timer/counter control register).
Configure as a timer:

1. Clear C=T bit in TMOD (Count internal frequency)

2. Set TRx in the TCON (timer run) and the gate bit in the TMOD
 x must be 1.
must be 0, or the external pin INT

3. Select one of 4 modes.

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 Ref: Ayala, p210

Ref: Ayala, pp205–212 Using a timer interrupt allows a timer to run and generate a timer
interrupt while the main program is running.
Timing subroutines
In microcontroller applications we need to wait a specified time, 1. Setup the timer for a delay of 1000 s. Enable the interrupts,
and so we need to have programmable time delays. and place the interrupt vector at 001Bh.
In all cases your application will be written for a specific clock fre- 2.
quency, say 12MHz, 16MHz, 11.0592 MHz etc.)
3.
If you subsequently change the clock frequency, you will need to
update your code, & possibly do some timing tests.
The timing options are:

1. Pure software time delays (wastefull)

2. Software polled timer (still wastefull, but OK in non-critical

apps)

3. Pure hardware using interrupts (accurate & preferred method)

Question We are mostly interested in the hardware timing version,

why?

You should read carefully the Pure Hardware Delay code example
on pp210–212 in Ayala.

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 18 Computer communications 19 Interfacing
Phil Melore, http://www.plcs.net/comhistory29.htm Usually means connecting your PC to periperals such as printers,
plotters, modems, data acquisition hardware etc.
Computer communication systems have their roots in the old telegraph. Early attempts
to communicate electronically over long distances began as early as the late 1700’s. In My portable PC
1810 a German man (von Soemmering) was using a device with 26 wires (1 for each letter
of the alphabet) attached to the bottom of an aquarium. When current passed through COM1:

the wires, electrolytic action produced small bubbles. By choosing the appropriate wires My PC serial LP1:
to energize, he was able to send encoded messages “via bubbles”. This then caught the ???? parallel
attention of the military and the race to find a system was on.
1 bit + control ?| ??{z????}?
In 1839, 2 Englishmen, Cooke and 8-bit
Wheatstone, had a 13 mile telegraph in
use by a British railroad. Their device
had 5 wires powering small electromag-
nets which deflected low-mass needles. For interfacing we have two options
By applying current to different combi-
nations of 2 wires at a time the needles Parallel all 8 (or more) bits used together to send an entire byte
were deflected so that they pointed to
letters of the alphabet arranged in a ma-
at a time. (Requires about 20 pins practically) Speed is about
trix. This “2 of 5” code only allowed 150kbits/second for a maximum distance of 2–3 meters. (No
20 combinations so the letters “z,v,u,q,j
and c” were omitted (forget about å, ä,
standard, although C ENTRONIX PARALLEL, or ECP, or EPP (ex-
and ö). This telegraph was a big step for tended parallel port) are common. Writes one byte at a time,
the time, but the code was not binary
(on/off) but rather it was trinary (the
reads one nybble at a time.
needle moved left,right,or not at all).
Serial Send just one bit at a time. (Requires 5–8 pins practically.)
The biggest problems with these devices was the fact that they were parallel (required Follows RS-232 standard and extensions. Typical speed is 9600
multiple wires) so it was S.F.B. Morse who created the fully serial binary system; Morse bits/second (although faster versions are more common now
code. with compression etc.)

Easy to program:
Use the IN and OUT op-codes on the 8086 PC. or use the Port[]
command in Pascal.

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 Serial port hardware comes in 2 flavors– a 25-pin type and a 9-pin
type (shown below).

20 Serial communications: RS232

9-PIN 25-PIN PURPOSE
The serial RS232 standard is a serial asynchronous communications 1 1 frame ground (internally connected to the chassis)
protocol. (RS is for ‘recommended standard’) 2 3 receive data (RD) (pin where the data from the external device enters)
3 2 transmit data (TD) (pin where the data leaves)
4 20 data terminal ready (DTR)
Serial The infomation travels down a single line 5 7 signal ground
6 6 data set ready (DSR)
Asynchronous means that it is not necessary to exactly synchronise 7 4 request to send (RTS)
the clocks between the transmitter and receiver. Data is trans- 8 5 clear to send (CTS)
9 22 ring indicator (RI) *only for modems*
mitted from 1 computer to another, not necessarily running at
exactly at the same clock speed. Details of the pins follows:
Standard An Electronics Industry Standard (EIS) #232. Defines DTS data terminal ready– This pin is a master control for the ex-
how the connectors should physically look, specifies voltage ternal device. When this pin is 1 the external device will not
levels, and defines what signals should do. transmit or receive data.

There are 2 types of RS-232 devices.
DTE Data Terminal Equipment and a common example is a com-
puter. (Originally PCs used to be thought of as terminals to real
computers such as IBM mainframes)
DCE Data Communications Equipment and a common example is
a mainframe or modem. The 8051 may be either a DTE or DCE
device.
and there are now two types of connectors:
DSR data set ready– Usually external devices have this pin as a
permanent 0 and the plc basically uses it to determine that the
external device is powered up and ready.
RTS request to send– This is part of hardware handshaking. When
the 8051 wants to send data to the external device it sets this
pin to a 0. In other words, it sets the pin to a 0 and basically
says “I want to send you data. Is it ok?” The external device
says it’s OK to send data by setting its clear to send pin to 0.
The 8051 then sends the data.

1. The older 25 pin D-shell (DB–25) CTS clear to send- This is the other half of hardware handshaking.
As noted above, the external device sets this pin to 0 when it is
2. The newer 9pin (DB–9), since most of the connections on the 25 ready to receive data from the 8051.
pin version were never used.

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 Ref: Sargent & Shoemaker, p655 Connecting two DCE devices (such as say two computers) will not
work very well, (since they are both DCEs, rather than one DCE and
The DB 9pin male conector as seen looking at the computer’s serial
one DTE) so we must reverse two of the pins.
port. This is smaller & has less pins than the 25pin version, but still
carries all the necessary infomation.

computer #1 computer #2
DB-9 male connector & pin assignments DTE device DTE device
2 receive data 2 receive data
Data carrier detect (DCD) 1 3 transmit data 3 transmit data
6 Data set ready
Receive data (RxD) 2 Will not work !
7 request to send (RTS)
Transmit Data (TxD) 3
8 clear to send (CTS)
Data terminal ready (DTR) 4 DTE device DTE device
9 Ring indicator (RI) 2 receive data 2 receive data
Signal ground 5
3 transmit data 3 transmit data

Null modem cable

DB–25 pin connections for RS232 lines.

RS232 signal Direction DTE DCE

It is easy to swap over 2 of the lines of the cable to make a Null
Signal ground 1 1
Modem Cable.
Transmit Data (TxD) Out 2 3
Receive Data (RxD) In 3 2
Request to Send (RTS) Out 4 5
Clear to Send (CTS) In 5 4
Data Terminal Ready (DTR) Out 20 6
Data Set Ready (DSR) In 6 20
Ring Indicator (RI) 22 22

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 Serial RS232 protocol But this brings in a ambiguity regarding the start of the transmis-
So to transmit the letter ‘A’, ASCII code (41h), we must send sion. (We could tune in half-way through.)

‘A’  01000001 What happens if the transmission starts with a 1?

where: Start bit Add a zero to the front of each character transmitted. (This
1 = high voltage, ( > +5V), but less than +15V is obviously not part of the information content of the signal.) So
0 = low voltage, ( < ,5V ), but greater than ,15V now ‘A’ is sent as: 0 01000001
| {z }.
A
Noise in telephone lines is very common.
So the serial transmission of ‘A’ is
 Data can get corrupted by random signals
Serial
 Need a redundancy check. (Will not be fool proof, but reduces
‘A’ the probability of a mistaken signal)
z }| {
 This will further lengthen the code, and reduce the ‘informa-
tion concentration’
10000010
direction of time  Odd Parity. A cheap redundancy check. Count how many 1s we
have in our character, and if the number of ones is:

Without any transmission is kept at a high voltage.

Even, then add a one to the code
Odd, then add a zero to the code

This ensures that each transmission segement (character) has an odd

number of ones. Even parity is possible, and in this case all charac-
ters have an even # of ones.

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 Using Odd parity, to transmit the character B 21 Interfacing with the outside world
01000010
| {z } For the computer to measure ‘real-world’ signals such as tempera-
2ones ture, pressure, humidity, and for it to write out voltages to control
which has an even number of ones, we must append after the last the speed on motors, brightness of lights etc, it must have both a
bit a single 1 to get:
parity
z}|{
 D/A (Digital to analogue converter)
1 01000010
| {z }
B  A/D (Analogue to digital converter)
Now to transmit C =

8-bit Digital to Analogue conversion

8 --
< --
8 bit binary value -- D/A - voltage out
: --

8-bit Analogue to Digital conversion

-
--- 9=
- A/D -- ; 8 bit (1 byte) to computer
voltage in
--

More expensive 12 & 16 bit converters are also possible.

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 Ref: Ogata, DCE, p32

An alternative scheme for a D/A converter that uses resistors of

D/A converters are easier to fabricate and cheaper than A/Ds. The only size R and 2R is a ladder scheme.
D/A takes a binary stream, and converts this to a single continuous Ladder D/A converter
voltage.
D/A converter 3R

R0 2R R R R 2R
, Vout
+

, 2R 2R 2R 2R
+ Vout

8R 4R 2R R b0 b1 b2 b3
,Vref
b0 b1 b2 b3
,Vref

In this scheme, all the resistors (except for the feedback resistor)
are either R or 2R which means a high level of accuracy can be
The D/A converter outputs a voltage, Vout given a binary number achieved.
b3b2b1b0, where each of the bs can be either 1 or 0, A/D converters are more complicated and use internally a D/A
R b b b! converter coupled with a successive approximation register (SAR).
Vout = 0 b3 + 2 + 1 + 0 Vref
R 2 4 8 Details given in electronic handbooks.
As we increase the # of bits, the range of matched resistors becomes
large, and the accuracy becomes poor.

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 22 8052: Extending the 8051 family 23 8051 conclusions
The 8051 is just the first member of a series of micro-controllers. The
most common “big brother” is the 8052.

 adds another 128 bytes of internal RAM (indirectly addressable)

 increases the onboard ROM from 4K to 8K.
 Adds another timer, T2, (to make three; T0,T1 and T2), and
associated new SFRs.

 T2 is a capture timer.
 No new op-codes, but does have new SFRs
Since the I NTEL designers of the original 8051 left ample room in
the SFR space for future functions, Philips Semiconductor designers
can add another timer with special functions, without adding new op-
codes.
SFR Address
T2H 0xCD
T2L 0xCC
RCAP2H 0xCB
RCAP2L 0xCA
T2CON 0xC8
You should consult the relevant manufacturer’s documentation for
these extra functions, (such as Phillips Semiconductor).

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