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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 53, NO. 6, DECEMBER 2006

Research on Hybrid-Clamped Multilevel-Inverter Topologies


Alian Chen and Xiangning He, Senior Member, IEEE
AbstractThe concept of hybrid clamped is proposed in multilevel-inverter topologies, and a hybrid-clamped multilevelinverter topology comprising active and passive clamping devices is presented in this paper. In this topology, the dc-link capacitor voltages can be balanced without additional circuitry or separated dc voltage sources, regardless of load characteristics. It can be used in real and reactive power conversion applications. The topology structure, operating principle, and self-voltage balancing ability are analyzed. In addition, the validity is conrmed by simulations and experiments based on a ve-level inverter. Finally, the functions of different clamping devices are compared. Index TermsHybrid clamped, multilevel inverter, neutralpoint voltage balancing, topology.

I. I NTRODUCTION ULTILEVEL inverters have been a research hotspot in high-voltage and high-power applications in recent years. Generally speaking, diode-clamped, ying-capacitor, and cascaded multilevel converters are three basic multilevel topologies [1], [2]. To synthesize multilevel output, voltage clamping is one of the most important issues. The meaning of clamping is to limit the switchs terminal voltage in a suitable range by using clamping devices. In the three existing multilevel-inverter topologies, it can be seen through their names that voltages are clamped by diodes in the diode-clamped multilevel inverter, by capacitors in the yingcapacitor multilevel inverter, and by separated voltage sources in the cascaded multilevel topology with separated voltage sources. However, the three topologies have some disadvantages in real applications. The diode-clamped multilevel inverter needs separated dc sources or complex control methods when a real power is delivered [2], [3]. Although the ying-capacitor inverter can be used in both real and reactive power conversions, it is difcult to balance the capacitor voltages when it is used for reactive power compensation [4]. The cascaded multilevel inverter needs separated voltage sources; therefore, they are more suitable for renewable energy sources such as fuel cell, photovoltaic, biomass, etc. To overcome the above disadvantages, it is an instructive idea to nd new multilevel-inverter topologies with higher perfor-

Fig. 1.

Five-level circuit proposed in [5].

mance by changing clamping devices. All the three existing multilevel inverters use only one type of clamping devices in one topology. If two or more types of clamping devices are used in one topology, a series of new multilevel-inverter topologies can be derived. This is also the concept of the hybrid-clamped method. II. E XISTING H YBRID -C LAMPED M ULTILEVEL -I NVERTER T OPOLOGIES A topology clamped by diodes and capacitors was proposed in [5], and one leg of a ve-level topology is shown in Fig. 1. The purpose of the topology is to solve the problems of dc-link capacitor voltages unbalancing and higher blocked voltages of the inner switches in traditional diode-clamped multilevel inverters. Compared with the diode-clamped multilevel-inverter topology, the functions of the added clamping capacitors are as follows: 1) providing blocked voltages for the inner switches at turn-off; 2) providing bidirectional current paths; and 3) realizing the dc-link capacitor voltage balancing. This topology is similar to the ying-capacitor topology in which the clamping capacitors contribute to the voltage synthesis. Both of the two topologies use redundant switching states of the middle voltage levels to balance the capacitor voltages. For the same reason as the ying-capacitor multilevel converter, this hybrid-clamped multilevel converter topology cannot keep the

Manuscript received December 23, 2004; revised June 14, 2005. Abstract published on the Internet September 15, 2006. This work was supported by the National Nature Science Foundation of China (50277035). Parts of this paper were presented at IEEE PESC, Aachen, Germany, June 2004. The authors are with the College of Electrical Engineering, Zhejiang University, Hangzhou 310027, China (e-mail: chenalian@zju.edu.cn; hxn@zju.edu.cn). Digital Object Identier 10.1109/TIE.2006.885154

0278-0046/$20.00 2006 IEEE

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Fig. 2.

Generalized ve-level circuit proposed in [6].

capacitor voltages balancing in pure reactive conversions and is not suitable for reactive power compensation. A generalized multilevel converter topology with selfvoltage balancing shown in Fig. 2 was proposed in [6]. This topology is clamped by active and passive devices, and it can be used in real and reactive power conversions regardless of load characteristics. However, it requires a large number of devices. A novel topology with neutral-point voltage balancing ability is proposed in this paper, which has the same advantages as the topology shown in Fig. 2, but requires much fewer devices. Fig. 3 shows one leg of the proposed ve-level topology. This paper analyzes the structure characteristics and operating principle of the proposed topology in detail and discusses the realization of the neutral-point voltage balancing. Also, the clamping mechanism of switching devices and diodes is analyzed. Finally, the functions of different clamping devices are summarized. III. S TRUCTURE C HARACTERISTICS AND O PERATING P RINCIPLE A. Structure Characteristics Fig. 3 shows one leg of the proposed hybrid-clamped velevel inverter. In this topology, switching devices Sa1Sa4 and Sa1 Sa4 are the main switching devices used to produce the desired output voltage. Sc1Sc6 are the clamping switching devices, and Dc1Dc12 are the clamping diodes. The switching devices Sc1Sc6 and the auxiliary capacitors C5C7 maintain the dc-link capacitor voltages in balance. It can be seen from Fig. 3 that only the clamping devices nearest to the dc side are

Fig. 3. One leg of the proposed hybrid-clamped ve-level inverter.

active switches with antiparalleled diodes, while others are only diodes. Also, only the ying capacitors nearest to dc side are remained. This topology is easy to be expanded to any voltage levels. For one leg of this M -level topology, (M 1) dc-link

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TABLE I RELATIONSHIP BETWEEN OUTPUT VOLTAGE UO AND SWITCHING STATES

capacitors, 2(M 1) main switching devices, 2(M 2) clamping switching devices, (M 1) (M 2) clamping diodes, and (M 2) auxiliary capacitors are needed. All the capacitors sustain the same voltage, and all the switching devices and diodes have the same voltage stresses. B. Multilevel Synthesis Principle Similar to the topology in Fig. 2, redundant switching states exist for middle voltage levels in the proposed hybrid-clamped topology. The multilevel synthesis principle is explained with a ve-level circuit as an example. The dc bus negative point is taken for reference. Five voltage levels are produced by the following switching states correspondingly. 1) For voltage level U1 = 0Udc, turn on four main switches Sa4 , Sa3 , Sa2 , Sa1 and three clamping switches Sc1, Sc3, Sc5. 2) For voltage level U2 = 1Udc, the following are the two switching states. a) Turn on four main switches Sa4, Sa4 , Sa3 , Sa1 and three clamping switches Sc1, Sc3, Sc5. b) Turn on four main switches Sa1, Sa4 , Sa3 , Sa2 and three clamping switches Sc2, Sc4, Sc6. 3) For voltage level U3 = 2Udc, the following are the two switching states. a) Turn on four main switches Sa3, Sa4, Sa4 , Sa1 and three clamping switches Sc1, Sc3, Sc5. b) Turn on four main switches Sa1, Sa4, Sa4 , Sa3 and three clamping switches Sc2, Sc4, Sc6. 4) For voltage level U4 = 3Udc, the following are the two switching states. a) Turn on four main switches Sa2, Sa3, Sa4, Sa1 and three clamping switches Sc1, Sc3, Sc5. b) Turn on four main switches Sa1, Sa3, Sa4, Sa4 and three clamping switches Sc2, Sc4, Sc6. 5) For voltage level U5 = 4Udc, turn on four main switches Sa1, Sa2, Sa3, Sa4 and three clamping switches Sc2, Sc4, Sc6.

Because (Sa1, Sc1), (Sc1, Sc2), (Sc2, Sc3), (Sc3, Sc4), (Sc4, Sc5), (Sc5, Sc6), and (Sc6, Sa1 ) are in parallel with capacitors C1, C5, C2, C6, C3, C7, and C4, respectively, they should be complementary switching pairs, i.e., when one switch is on, the other is off, and vice versa. The relationship between output voltage uo and switching states is shown in Table I. Fig. 4 shows bidirectional current paths corresponding to each voltage level (only one switching state is given for redundant switching states). It can be seen from the above analysis that the switching operation of a hybrid-clamped ve-level inverter must comply with the following rules. 1) For each switching state, there must be four main switching devices and three clamping switching devices on. 2) Sa1 is complementary with Sa1 . Except for Sa1 and Sa1 , any three adjacent main switching devices are on or off simultaneously. Therefore, (Sa1, Sa1 ), (Sa2, Sa4 ), (Sa3, Sa3 ), and (Sa4, Sa2 ) are the complementary switching pairs, i.e., if one is on, the other must be off and vice versa. 3) Sa1 and Sc1 are complementary. 4) Any two adjacent clamping switching devices Sc1Sc6 are complementary. IV. R EALIZATION OF DC-L INK C APACITOR S ELF -V OLTAGE B ALANCING The self-voltage balancing ability of the proposed topology is realized through clamping switching devices and auxiliary capacitors. Its principle is similar to the method used in Fig. 2. When the multilevel converter switches from one state to another, two different groups of capacitors are connected through clamping switching devices. The difference between the two topologies is that there are multiple capacitors in parallel for the topology in Fig. 2, and only two capacitors in parallel for the proposed topology. Correspondingly, the number of clamping switches in the proposed topology is less than that in the topology of Fig. 2. Also, all the states of the clamping

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Fig. 4.

Bidirectional current paths corresponding to each voltage level. (a) U1 = 0Udc. (b) U2 = 1Udc. (c) U3 = 2Udc. (d) U4 = 3Udc. (e) U5 = 4Udc.

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Fig. 5. Carriers and modulation signals in subharmonic PWM.

Fig. 6.

Geometrical relationship between carriers and modulation signals.

switching devices can be determined from Sa1. It can be seen from Table I that there are two switching states for each of the middle voltage level: In one state, Sa1 is on, and in the other state, Sa1 is off. For the state that Sa1 is on, Sc2, Sc4, and Sc6 should also be on according to the above switching operation rules. Then, capacitors C1 and C5, C2 and C6, C3 and C7 are in parallel, respectively, so the two parallel capacitors will be charged and discharged to keep their voltages equal: Uc1 = Uc5, Uc2 = Uc6, Uc3 = Uc7; for the other state that Sa1 is off, capacitors C2 and C5, C3 and C6, C4 and C7 are in parallel, respectively, so the two parallel capacitors will be charged and discharged to keep their voltages equal: Uc2 = Uc5, Uc3 = Uc6, Uc4 = Uc7. That is to say, the clamping capacitors can be charged or discharged according to the voltage difference between the two parallel capacitors. In addition, the objective of the clamping capacitor voltage is to be a stable voltage level. Then, all the dc-link capacitors can keep their voltages balance through the auxiliary capacitors C4, C5, and C6. This voltage balancing method is different from the one that utilizes redundant switching states. The redundant-switchingstate method means that by selecting two or more switching states in one period to produce one neutral-point voltage, in some switching states, the dc-link capacitors are charged and in other states are discharged. Then, in one period, the capacitor voltages can keep their balance by charging and discharging. The typical application of this method is the phaseshift pulsewidth modulation (PWM) used in ying-capacitor multilevel converters [7]. However, it is difcult for the dc-link capacitor voltages to be balanced in pure reactive applications. In the proposed topology, the auxiliary capacitors act as intermedia, which are in parallel with different dc-link capacitors in different switching states. Therefore, the neutral-point voltages can be kept balance regardless of the load characteristics. In addition, this topology can be used in real and reactive power applications with simple control. When the inverter works at low modulation index, the velevel PWM may change to three-level PWM. In this case, the capacitor voltages can also be kept balance. To indicate the different ranges of modulation index corresponding to different voltage levels, the subharmonic PWM is taken as an example (Fig. 5). The four carriers are corresponding to the switching states of Sa1, Sa2, Sa3, and Sa4, respectively from top to bottom. This modulation is one of the switching states in Table I.

In an M -level inverter, the amplitude modulation index ma and the frequency ratio mf are dened as ma = mf = Am (M 1)Ac fc fm (1) (2)

where Ac is the amplitude peakpeak value of triangle carriers, Am is the amplitude peakpeak value of sinusoidal waveform, fc is the carrier frequency, and fm is the modulation signal fm , the turn-on time of Sa1 in one frequency. When fc carrier period can be obtained with average model. Because fm , the sinusoidal signal may approximates to a constant fc in one carrier period. Then, Fig. 5 can be redrawn as Fig. 6. Considering the simple geometrical relationship, the following equation can be obtained:
tc 2 Tc 2

ug 3Ac = Ac =

Am 2

sin m t + 2Ac 3Ac Ac (3)

Am sin m t 1. 2Ac

For ve-level inverter, ma = (Am /4Ac ), then from (3), the turn-on time of Sa1 in one carrier period can be seen as tcSa1 = (2ma sin m t 1)Tc . (4)

By using the same method, the turn-on time of Sa2, Sa3, and Sa4 in one carrier period is thus expressed as tcSa2 = (2ma sin m t)Tc tcSa3 = (2ma sin m t + 1)Tc tcSa4 = (2ma sin m t + 2)Tc . (5) (6) (7)

In (4), when sin m t = 1, tcSa1 , then ma = 0.5. This shows that when ma 0.5, Sa1 is off all along and only three voltage levels can be produced, when ma > 0.5, all the voltage levels can be produced. This case can be seen in Fig. 5, where ma = 0.8 is at high modulation index, ma = 0.33 is at low modulation index, and ma = 0.5 is at critical case. For an M -level inverter, the turn-on time of Sa1 in one carrier period

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Fig. 7.

Carriers combined two switching states. (a) Carriers of Sa1. (b) Carriers of Sa2. (c) Carriers of Sa3. (d) Carriers of Sa4.

tc can be obtained according to the same method, and also the critical value of modulation index tc = = = = mac = ug (M 2)Ac Tc Ac
Am 2

sin c t +

M 1 2 Ac

(M 2)Ac Tc Tc

Ac

Tc

Am sin c t M 3 2Ac 2

M 1 M 3 ma sin c t 2 2 M 3 . M 1

(8) (9)

Up to now, only one switching state is discussed. The other switching state can also be obtained. According to Table I, the four carriers in Fig. 5 are corresponding to the switching states of Sa2, Sa3, Sa4, and Sa1, respectively, from top to bottom. By combining the two switching states together, the carriers are arranged as in Fig. 7. From the above carriers, it can be seen that even at low modulation index, Sa1 can switch from on to off when the inverter changes from one state to another. According to the above analysis, the capacitor voltages can be balanced. The simulated and experimental results in the following part veried the validity. The method proposed in [8] is also suitable for this hybrid-clamped multilevel inverter at low modulation index. V. C LAMPING M ECHANISM OF S WITCHING D EVICES AND D IODES In the proposed topology, all the main switches are clamped to the corresponding dc-link capacitors by active clamping switches and passive clamping diodes, so the hybrid-clamped

multilevel inverter is called in this paper. Not only the main switches are clamped to 1Udc, but also the clamping switches and clamping diodes are clamped to 1Udc. For convenient analysis, the topology is split into two parts, which are the shadows shown in Fig. 8(a) and (b). The shadow in Fig. 8(a) is an improved diode-clamped four-level inverter, which has been analyzed in detail in [3]. Each of the main switches and clamping diodes are clamped to C5, C6, and C7, and then they are clamped to the corresponding dc-link capacitors according to the switching states of clamping switches. For example, if Sc1, Sc3, and Sc5 are on, the main switches and clamping diodes are clamped to C2, C3, and C4; if Sc2, Sc4, and Sc6 are on, the main switches and clamping diodes are clamped to C1, C2, and C3. For the whole topology, the devices shown in Fig. 8(a) are all clamped to the corresponding dc-link capacitors indirectly. For the devices shown in the shadow of Fig. 8(b), they are all clamped to the corresponding dc-link capacitors directly. When Sa1 turns off, it is clamped to C1 directly by Sc1; when Sc1, Sc3, and Sc5 turn off, they are clamped to C1, C2, and C3, respectively, by Sa1, Sc2, and Sc4; when Sc2, Sc4, and Sc6 turn off, they are clamped to C2, C3, and C4, respectively, by Sc3, Sc5, and Sa1 ; when Sa1 turns off, it is clamped to C4 directly by Sc6. Thus, all the devices are clamped to the corresponding dc-link capacitors by active switches and passive diodes. VI. S IMULATIONS AND E XPERIMENTS To verify the validity of the proposed topology, both simulations and experiments were carried out based on a ve-level single-phase half-bridge inverter. The circuit conguration of the experiment is the same as in Fig. 3. The neutral point of dc-link capacitors is taken as the reference point, and the output terminal uo connects with load. The dc input voltage is supplied by a booster/rectier and set to 200 V. The ac output frequency is set to 50 Hz. All the capacitors have the same capacitance

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Fig. 8. Split of the hybrid-clamped ve-level inverter. (a) Indirect clamping devices. (b) Direct clamping devices.

Fig. 9. PWM generation block diagram.

of 1100 F. All the switching devices and diodes have the same rated voltage 200 V and rated current 20 A. Subharmonic PWM is used, and the carriers are set according to Fig. 7. In practical realization, one switching state is produced rst and then the different signals are selected and combined in different switching periods. The gate signals are produced by an FPGA embedded board. The PWM generation block diagram is shown in Fig. 9. Fig. 10 shows the simulated waveforms with different loads and at different modulation indexes. In Fig. 10(a)(d), a 50- resistor was used, and in Fig. 10(e)(h), a 15-mH inductor in series with a 20- resistor was used. Fig. 11 shows the experimental results corresponding to the similar load conditions. It can be seen that the simulated and experimental results are almost identical, which demonstrates the validity of the topology and its neutral-point voltage balancing ability. By combining three similar one-leg circuits, a three-phase topology

can easily be formed. Fig. 12 shows the simulated phase and line voltages of a three-phase inverter. VII. D ISCUSSION AND C ONCLUSION By far, active switching devices, diodes, and capacitors, all can be used for clamping. The main functions of the clamping devices are summarized as follows. Diodes have the characteristics of unidirectional conduction, so they can be used for unidirectional clamping. Active switches are controllable devices, so they are more exible than diodes for clamping. A switching device with a parallel diode can provide a bidirectional path by itself, and it can realize main switch and ying-capacitor clamping. Capacitors are electrical energy storage passive components, so they can participate in voltage synthesizing and sustain the main switch blocking voltage. Also, they can be used for dc-link

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Fig. 10. Simulated results of the hybrid-clamped ve-level inverter. (a) Output voltage and current for resistive loads (ma = 0.8). (b) DC-link capacitor voltages for resistive loads (ma = 0.8). (c) Output voltage and current for resistive loads (ma = 0.33). (d) DC-link capacitor voltages for resistive loads (ma = 0.33). (e) Output voltage and current for inductive loads (ma = 0.8). (f) DC-link capacitor voltages for inductive loads (ma = 0.8). (g) Output voltage and current for inductive loads (ma = 0.33). (h) DC-link capacitor voltages for inductive loads (ma = 0.33).

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Fig. 11. Experimental results of the hybrid-clamped ve-level inverter. (a) Output voltage and current for resistive loads (ma = 0.8). (b) DC-link capacitor voltages for resistive loads (ma = 0.8). (c) Output voltage and current for resistive loads (ma = 0.33). (d) DC-link capacitor voltages for resistive loads (ma = 0.33). (e) Output voltage and current for inductive loads (ma = 0.8). (f) DC-link capacitor voltages for inductive loads (ma = 0.8). (g) Output voltage and current for inductive loads (ma = 0.33). (h) DC-link capacitor voltages for inductive loads (ma = 0.33).

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R EFERENCES
[1] J.-S. Lai and F. Z. Peng, Multilevel convertersA new breed of power converters, IEEE Trans. Ind. Appl., vol. 32, no. 3, pp. 509517, May/Jun. 1996. [2] F. Z. Peng, J.-S. Lai, J. McKeever, and J. A. VanCoevering, Multilevel voltage-source converter system with balanced DC voltages, in Proc. IEEE PESC, 1995, pp. 11441150. [3] X. Yuan and I. Barbi, Fundamentals of a new diode clamping multilevel inverter, IEEE Trans. Power Electron., vol. 15, no. 4, pp. 711718, Jul. 2000. [4] X. Yuan, H. Stemmler, and I. Barbi, Investigation on the clamping voltage self-balancing of the three-level capacitor clamping inverter, in Proc. IEEE PESC, 1999, pp. 491496. [5] B.-S. Suh and D.-S. Hyun, A new N-level high voltage inversion system, IEEE Trans. Ind. Electron., vol. 44, no. 1, pp. 107115, Feb. 1997. [6] F. Z. Peng, A generalized multilevel inverter topology with self voltage balancing, IEEE Trans. Ind. Appl., vol. 37, no. 2, pp. 611618, Mar./Apr. 2001. [7] T. A. Meynard and H. Foch, Multi-level conversion: High voltage choppers and voltage-source inverters, in Proc. IEEE PESC, 1992, pp. 397403. [8] L. M. Tolbert, F. Z Peng, and T. G. Habetler, Multilevel PWM methods at low modulation indices, IEEE Trans. Power Electron., vol. 15, no. 4, pp. 719725, Jul. 2000.

Fig. 12. Simulated results of the three-phase hybrid-clamped ve-level inverter. (a) Phase voltages. (b) Line voltages.

capacitor voltage balancing by charging and discharging or clamping. All the three types of devices can be used for clamping. With the different places in the topology, they may change their effects correspondingly. Considering the functions replacement among different clamping devices and based on the concept of hybrid clamped, a series of novel multilevel converter topologies can be deduced. The concept of hybrid clamped provides a new clew for constructing more multilevel converter topologies. A novel hybrid-clamped multilevel inverter with self-voltage balancing is proposed and researched in detail in this paper, which is clamped together by active and passive devices. Although some clamping switching devices are needed, the novel topology can be used in real and reactive power conversions with easy control and without any additional circuits. The operating principle and dc-link capacitor voltage-balancing ability are studied, and the validity is proved by simulated and experimental results. ACKNOWLEDGMENT The authors would like to thank L. Hu for his valuable suggestions and discussions as well as the help in experimental work.

Alian Chen was born in Shandong Province, China, in 1976. She received the B.Sc. and M.Sc. degrees from Shandong University, Jinan, China, in 1998 and 2000, respectively. She is currently working toward the Ph.D. degree in power electronics at Zhejiang University, Hangzhou, China. Her research interests are in power electronics and their industrial applications.

Xiangning He (M96SM96) received the B.Sc. and M.Sc. degrees from Nanjing University of Aeronautical and Astronautical, Nanjing, China, in 1982 and 1985, respectively, and the Ph.D. degree from Zhejiang University, Hangzhou, China, in 1989. From 1985 to 1986, he was an Assistant Engineer with the 608 Institute of Aeronautical Industrial General Company, China. From 1989 to 1991, he was a Lecturer with Zhejiang University. In 1991, he obtained a Fellowship from the Royal Society of U.K., and conducted research in the Department of Computing and Electrical Engineering, Heriot-Watt University, Edinburgh, U.K., as a Postdoctoral Research Fellow for two years. In 1994, he joined Zhejiang University as an Associate Professor. Since 1996, he has been a Full Professor with the Department of Electrical Engineering. He is the Director of the Power Electronics Research Institute, Zhejiang University. His research interests are in power electronics and their industrial applications. Dr. He received the 1989 Excellent Ph.D. Graduate Award, the 1995 Elite Prize Excellence Award, and the 1996 Outstanding Young Staff Member Award from the Zhejiang University for his teaching and research contributions. He received three Scientic and Technological Progress Awards (two in 1998 and one in 2002) from the Zhejiang Provincial Government and the State Educational Ministry of China, respectively, and four Excellent Paper Awards. He is a Fellow of the Institution of Electrical Engineers (IEE), U.K.

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