Professional Documents
Culture Documents
Hercules Family
Suited for applications with IEC 61508 SIL-3 and other standards Hardware safety functions
Processor BIST Memory Protection ( MPU + ECC/ Parity )
Roadmap
Families
TMS470M Family
Cortex M3 @ 80 MHz Value ( ABS, Passive Safety )
ARM Cortex-R4
Thumb-2 instructions MPU with 12 regions Optional Parity and ECC on all RAMs Launched in May 2006 Binary compatibility with ARM9 &ARM11 320DMPIS@200Mhz 8 Stage Pipeline http://www.arm.com/products/processors/corte x-r/cortex-r4.php
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Architecture RM48Lx30
3MB Flash 256KB RAM 2 N2HET ( Next Generation End Timer ) 44 IO / 2 x 24 Channel 12 Bit ADC I2C, DCANs SPI, MibSPI, LIN, SCI
Safety Architecture
Dual CPUs in lockstep CPU and Memory BIST ECC Flash & SRAM Parity on peripheral memories Loop back capability on Ios ECLK frequency external indicator MPU built into DMA ESM Error Signaling Module
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http://www.ti.com/lit/an/spna121a/spna121a .pdf
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Bibliography
http://focus.ti.com/mcu/docs/mcuprodovervi ew.tsp?sectionId=95&tabId=2835&familyId=1 931 http://www.wittenstein-us.com/EmbeddedRTOS/SAFERTOS.html http://www.ti.com/lit/wp/spry180/spry180.p df http://www.arm.com/products/processors/co rtex-r/cortex-r4.php
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