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IV B.Tech II Semester Supplementary Examinations, June 2007
VLSI DESIGN
(Electrical & Electronic Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
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Figure 1b
[10+6]
2. (a) With neat sketches explain how resistors and capacitors are fabricated in p-
well process.
(b) With neat sketches explain how resistors and capacitors are fabricated in n-
well process. [8+8]
3. Design a stick diagram for the NMOS logic shown below Y = (A + B).C [16]
4. Design a layout diagram for the CMOS logic shown below Y = (A + B + C) [16]
7. What are the different inputs that are provided to the place and route tool and
explain the significance of each input. [16]
1 of 2
Code No: RR420203 Set No. 1
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2 of 2
Code No: RR420203 Set No. 2
IV B.Tech II Semester Supplementary Examinations, June 2007
VLSI DESIGN
(Electrical & Electronic Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆
1. (a) With neat sketches explain the formation of the inversion layer in n-channel
enhancement MOSFET.
(b) A PMOS Transistor is operated in the triode region with the following para-
meters. VGS = −4.5V ; Vtp = −1V ; VDS = −2.2V ; W/L = 95; µnCox =
95 µA/V 2
Find its drain current and drain source resistance. [8+8]
2. With neat sketches explain how npn transistor is fabricated in Bipolar process. [16]
3. Design a stick diagram for the CMOS logic shown below Y = (A + B).C [16]
4. Design a layout diagram for the NMOS logic shown below Y = (A + B + C) [16]
Figure 5
6. Differentiate between CPLD and FPGA with neat sketches explain the architecture
of any one of the CPLD. [16]
7. What are the different inputs that are provided to the place and route tool and
explain the significance of each input. [16]
1 of 2
Code No: RR420203 Set No. 2
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2 of 2
Code No: RR420203 Set No. 3
IV B.Tech II Semester Supplementary Examinations, June 2007
VLSI DESIGN
(Electrical & Electronic Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆
3. Design a stick diagram for the CMOS logic shown below Y = (A + B + C) [16]
5. Calculate ON resistance from VDD to GND for the given inverter circuit shown in
Figure 5, If n-channel sheet resistance is 104 Ω per square. [16]
Figure 5
6. Clearly discus about the following FPGA Technology
7. Clearly explain each step of high level design flow of an ASIC. [16]
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1 of 1
Code No: RR420203 Set No. 4
IV B.Tech II Semester Supplementary Examinations, June 2007
VLSI DESIGN
(Electrical & Electronic Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆
2. With neat sketches explain how Diodes and Resistors are fabricated in CMOS
process. [16]
3. Design a stick diagram for the PMOS logic shown below Y = (AB + CD) [16]
4. Design a layout diagram for two input nMOS NOR gate. [16]
5. Derive an equation for the propagation delay from input to output of the pass
transistor chain shown in Figure 5. [16]
Figure 5
6. Implement Full-adder circuit using PAL. [16]
7. Clearly explain each step of high level design flow of an ASIC. [16]
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