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I"';;: I--.
t---.
0
'00
'\ i"'-..
.....
a p(V(Mle,dl/VIIC?'9JI
Fig.S Simulated transfer function of amplifier
Magnitude (dB) and phase (degree)
Noise analysis
The input-referred noise voltage of CMOS amplifier is
dominated by flicker (lit) noise at low frequencies and
thermal/shot noise at higher frequencies. The frequency at
which the noise tail intersects the noise floor is called the
flicker-noise corner frequency. By representing the noise
sources of each transistor by a voltage source at its input,
the total input-referred noise contribution can be calculated
by considering the voltage gains from the device to the
amplifier output.
In order to examine the noise performance of neural
amplifier was simulated using the Pspice. Fig.6 shows the
input-referred noise voltage versus frequency.
\
...
'----k
Fig.6 : Simulated input-referred noise voltage [V/sqrt(Hz)]
The Root Mean Square (RMS) of the input-referred noise
voltage: Vni,nns = 14.8 calculated for a frequency
range 100Hz - 10KHz. This value is competitive compared
with other developed recording amplifiers reported in the
literature [10], [13].
Noise Efficiency Factor
We are interested in minimizing noise within a strict
power budget; we must consider the tradeoff between power
and noise. To compare the power-noise tradeoff among
amplifiers, we adopt the noise efficiency factor (NEF)
which is widely used to compare neural amplifier designs.
The noise efficiency factor is expressed as:
(12)
Where Vni,nns is the total input-referred noise, ltot is the
total supply current, and BW is the -3 dB bandwidth of the
amplifier.
r
is the thermal voltage, is the Boltzmann
constant and is the temperature.
Authorized licensed use limited to: CNUDST. Downloaded on October 3, 2009 at 08:29 from IEEE Xplore. Restrictions apply.
[1]
[3]
[4]
[7]
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Ming Yin; Ghovanloo, M., "A Clockless Ultra Low-Noise Low-
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Ming Yin; Ghovanloo, M., "A Low-Noise Preamplifier with
Adjustable Gain and Bandwidth for Biopotential Recording
Applications Circuits and Systems", 2007. ISCAS 2007. IEEE
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Page(s):321 324. Digital Object Identifier
10.1109IISCAS.2007.378400
R. R. Harrison and C. Charles, "A low-power low-noise CMOS
amplifier for neural recording applications," IEEE 1. Solid-State
Circuits, vol. 38, pp. 958 965, June 2003.
1. Parthasarathy et aI., "An Integrated CMOS Bio-potential
Amplifier with a Feed-Forward DC Cancellation Topology," Froc.
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Roy H. Olsson III, and Kensall D. Wise, "A Three-Dimensional
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T. Horiuchi, T. Swindell, D. Sander, and P. Abshire, "A low-power
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[9]
[8]
[11]
[12]
[10]
Parameters Value
Gain G = 43.95 dB
Phase margin Mq>=64.6
Gain-BandWidth GBW= 1.1294 MHz
Power Consumption Ptot= 9.22 I..l W
Total Current absorbed Itot=4.617 I..lA
Common Mode Rejection CMRR=113.27dB
Ratio CMRR> 92dB @ f 10KHz
Power Supply Rejection PSRRYss=73.11dB
Ratio
PSRR =75.29dB
Output-voltage swing
CMR+=806mV
CMR-=992mV
DC Offset 196uV
Input Referred Noise Vni,rms = 14.8 I..lVrms
Noise Efficiency Factor NEF=13,22
IV. CONCLUSION
This paper presents the design of an integrated micro-
power amplifier for neural recording signal. The architecture
of the neural recording system was discussed and followed
by the theoretical study of the neural amplifier.
Furthermore, PSpice simulation which using a real transistor
model was presented. In particular, the transfer function of
amplifier and the noise analysis were presented. A power
dissipation of about 9.22 and an input referred noise
about 14.8fJ.Vrms were achieved. Future work will focus on
the study of closed-loop amplifier with adjustable gain and
low cut off frequency.
SIMULATED PERFORMANCE CHARACTERISTICS OF NEURAL AJ\.1PLIFIER
Summary table
Table III summarizes the simulation results of the neural
recording amplifier.
For U
T
=25mV, T=27C=300oK, K
B
=I.3806.10-
23
I
tot
=4.617fJ.A, Vni,nns = 1,4888E-05 Vrms and BW= [100Hz,
10KHz].
We obtain NEF=13,22 which is competitive compared
with [7].
Authorized licensed use limited to: CNUDST. Downloaded on October 3, 2009 at 08:29 from IEEE Xplore. Restrictions apply.
Authorized licensed use limited to: CNUDST. Downloaded on October 3, 2009 at 08:29 from IEEE Xplore. Restrictions apply.