Freescale Semiconductor Data Sheet: Technical Data

An Energy Efficient Solution by Freescale

Document Number: MC9S08QE128 Rev. 7, 10/2008

MC9S08QE128 Series
Covers: MC9S08QE128, MC9S08QE96, MC9S08QE64

MC9S08QE128
80-LQFP Case 917A 14 mm2 48-QFN Case 1314 7 mm2 32-LQFP Case 873A 7 mm2 64-LQFP Case 840F 10 mm2 44-LQFP Case 824D 10 mm2

8-Bit HCS08 Central Processor Unit (CPU) Up to 50.33-MHz HCS08 CPU above 2.4V, 40-MHz CPU above 2.1V, and 20-MHz CPU above 1.8V, across temperature range HC08 instruction set with added BGND instruction Support for up to 32 interrupt/reset sources On-Chip Memory Flash read/program/erase over full operating voltage and temperature Random-access memory (RAM) Security circuitry to prevent unauthorized access to RAM and flash contents Power-Saving Modes Two low power stop modes; reduced power wait mode Peripheral clock enable register can disable clocks to unused modules, reducing currents; allows clocks to remain enabled to specific peripherals in stop3 mode Very low power external oscillator can be used in stop3 mode to provide accurate clock to active peripherals Very low power real time counter for use in run, wait, and stop modes with internal and external clock sources 6 s typical wake up time from stop modes Clock Source Options Oscillator (XOSC) Loop-control Pierce oscillator; Crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz Internal Clock Source (ICS) FLL controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation; supports CPU freq. from 2 to 50.33 MHz System Protection Watchdog computer operating properly (COP) reset with option to run from dedicated 1-kHz internal clock source or bus clock Low-voltage detection with reset or interrupt; selectable trip points Illegal opcode detection with reset Flash block protection Development Support Single-wire background debug interface Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints) On-chip in-circuit emulator (ICE) debug module containing two comparators and nine trigger modes.

Eight deep FIFO for storing change-of-flow addresses and event-only data. Debug module supports both tag and force breakpoints. ADC 24-channel, 12-bit resolution; 2.5 s conversion time; automatic compare function; 1.7 mV/C temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6V to 1.8V ACMPx Two analog comparators with selectable interrupt on rising, falling, or either edge of comparator output; compare option to fixed internal bandgap reference voltage; outputs can be optionally routed to TPM module; operation in stop3 SCIx Two SCIs with full duplex non-return to zero (NRZ); LIN master extended break generation; LIN slave extended break detection; wake up on active edge SPIx Two serial peripheral interfaces with Full-duplex or single-wire bidirectional; Double-buffered transmit and receive; MSB-first or LSB-first shifting IICx Two IICs with; Up to 100 kbps with maximum bus loading; Multi-master operation; Programmable slave address; Interrupt driven byte-by-byte data transfer; supports broadcast mode and 10 bit addressing TPMx One 6-channel and two 3-channel; Selectable input capture, output compare, or buffered edge- or center-aligned PWMs on each channel RTC 8-bit modulus counter with binary or decimal based prescaler; External clock source for precise time base, time-of-day, calendar or task scheduling functions; Free running on-chip low power oscillator (1 kHz) for cyclic wake-up without external components Input/Output 70 GPIOs and 1 input-only and 1 output-only pin 16 KBI interrupts with selectable polarity Hysteresis and configurable pull-up device on all input pins; Configurable slew rate and drive strength on all output pins. SET/CLR registers on 16 pins (PTC and PTE)

Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Freescale Semiconductor, Inc., 2008. All rights reserved.

Table of Contents
1 2 3 MC9S08QE128 Series Comparison. . . . . . . . . . . . . . . . . . . . .4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .12 3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .12 3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .13 3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . .14 3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .18 3.8 External Oscillator (XOSC) Characteristics . . . . . . . . .21 3.9 Internal Clock Source (ICS) Characteristics . . . . . . . . .22 3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 3.10.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.2 TPM Module Timing . . . . . . . . . . . . . . . . . . . . . 3.10.3 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11 Analog Comparator (ACMP) Electricals . . . . . . . . . . . 3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Device Numbering System . . . . . . . . . . . . . . . . . . . . . Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 26 27 30 30 33 34 34 34 35 49 49

4 5 6 7

MC9S08QE128 Series Data Sheet, Rev. 7 2 Freescale Semiconductor

HCS08 CORE
BKGD/MS CPU

RESET

TPM1CH2-0 MODULE (TPM1) ANALOG COMPARATOR (ACMP1) TPM1CLK ACMP1O ACMP1+ ACMP1EXTAL XTAL 3

BDC

BKP INTERNAL CLOCK SOURCE (ICS) OSCILLATOR (XOSC) 3-CHANNEL TIMER/PWM MODULE (TPM2) IRQ

PORT A

3-CHANNEL TIMER/PWM

PTA7/TPM2CH2/ADP9 PTA6/TPM1CH2/ADP8 PTA5/IRQ/TPM1CLK/RESET PTA4/ACMP1O/BKGD/MS PTA3/KBI1P3/SCL1/ADP3 PTA2/KBI1P2/SDA1/ADP2 PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+ PTB7/SCL1/EXTAL PTB6/SDA1/XTAL PTB5/TPM1CH1/SS1 PTB4/TPM2CH1/MISO1 PTB3/KBI1P7/MOSI1/ADP7 PTB2/KBI1P6/SPSCK1/ADP6 PTB1/KBI1P5/TxD1/ADP5 PTB0/KBI1P4/RxD1/ADP4 PTC7/TxD2/ACMP2PTC6/RxD2/ACMP2+ PTC5/TPM3CH5/ACMP2O PTC4/TPM3CH4/RSTO PTC3/TPM3CH3 PTC2/TPM3CH2 PTC1/TPM3CH1 PTC0/TPM3CH0 PTD7/KBI2P7 PTD6/KBI2P6 PTD5/KBI2P5 PTD4/KBI2P4 PTD3/KBI2P3/SS2 PTD2/KBI2P2/MISO2 PTD1/KBI2P1/MOSI2 PTD0/KBI2P0/SPSCK2 PTE7/TPM3CLK PTE6 PTE5 PTE4 PTE3/SS1 PTE2/MISO1 PTE1/MOSI1 PTE0/TPM2CLK/SPSCK1 PTF7/ADP17 PTF6/ADP16 PTF5/ADP15 PTF4/ADP14 PTF3/ADP13 PTF2/ADP12 PTF1/ADP11 PTF0/ADP10 PTG7/ADP23 PTG6/ADP22 PTG5/ADP21 PTG4/ADP20 PTG3/ADP19 PTG2/ADP18 PTG1 PTG0

HCS08 SYSTEM CONTROL

RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT COP INT LVD IRQ

TPM2CH2-0 TPM2CLK SCL1 SDA1 ACMP2+ ACMP2O ACMP2TPM3CH5-0

IIC MODULE (IIC1) ANALOG COMPARATOR (ACMP2)

USER FLASH 128K / 96K / 64K

6-CHANNEL TIMER/PWM MODULE (TPM3) USER RAM 8K / 6K / 4K SERIAL COMMUNICATIONS INTERFACE (SCI1) TxD1 RxD1

6 TPM3CLK 10

DEBUG MODULE (DBG)

REAL TIME COUNTER (RTC)

SERIAL PERIPHERAL INTERFACE MODULE (SPI2)

SS2 MISO2 MOSI2 SPSCK2 TxD2 RxD2 SS1 MISO1 MOSI1 SPSCK1

VREFH VREFL VDDA VSSA

PTH7/SDA2 PTH6/SCL2 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0

SDA2 SCL2 PORT H

IIC MODULE (IIC2)

- VREFH/VREFL internally connected to VDDA/VSSA in 48-pin and 32-pin packages - VDD and VSS pins are each internally connected to two pads in 32-pin package

Figure 1. MC9S08QE128 Series Block Diagram

MC9S08QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 3

PORT G

PORT F

PTJ7 PTJ6 PTJ5 PTJ4 PTJ3 PTJ2 PTJ1 PTJ0

PORT J

SERIAL PERIPHERAL INTERFACE MODULE (SPI1)

24-CHANNEL,12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC)

PORT E

VDD VDD VSS VSS

VOLTAGE REGULATOR

SERIAL COMMUNICATIONS INTERFACE (SCI2)

PORT D

PORT C

PORT B

MC9S08QE128 Series Comparison

MC9S08QE128 Series Comparison

Table 1. MC9S08QE128 Series Features by MCU and Package
Feature Flash size (bytes) RAM size (bytes) Pin quantity ACMP1 ACMP2 ADC channels DBG ICS IIC1 IIC2 IRQ KBI Port I/O RTC SCI1 SCI2 SPI1 SPI2 TPM1 channels TPM2 channels TPM3 channels XOSC
1 1

The following table compares the various device derivatives available within the MC9S08QE128 series.

MC9S08QE128 131072 8064 80 64 48 44 80

MC9S08QE96 98304 6016 64 48 44 64

MC9S08QE64 65536 4096 48 44 32

yes yes 24 22 10 10 24 22 10 10 22 10 10 10

yes yes yes yes yes no no yes yes no no yes no no no

yes 16 70 16 54 16 38 16 34 16 70 16 54 16 38 16 34 16 54 16 38 16 34 12 26

yes yes yes yes yes 3 3 6 yes

Port I/O count does not include the input only PTA5/IRQ/TPM1CLK/RESET or the output only PTA4/ACMP1O/BKGD/MS.

MC9S08QE128 Series Data Sheet, Rev. 7 4 Freescale Semiconductor

Pin Assignments

Pin Assignments
PTC7/TxD2/ACMP2PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+ PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1-

This section describes the pin assignments for the available packages. See Table 2 for pin availability by package pin-count.

PTA5/IRQ/TPM1CLK/RESET PTC4/TPM3CH4/RSTO PTC5/TPM3CH5/ACMP2O

PTA4/ACMP1O/BKGD/MS

PTD1/KBI2P1/MOSI2 PTD0/KBI2P0/SPSCK2 PTH7/SDA2 PTH6/SCL2 PTH5 PTH4 PTE7/TPM3CLK VDD VDDAD VREFH VREFL VSSAD VSS PTB7/SCL1/EXTAL PTB6/SDA1/XTAL PTH3 PTH2 PTH1 PTH0 PTE6

PTE5 PTB5/TPM1CH1/SS1 PTB4/TPM2CH1/MISO1 PTC3/TPM3CH3 PTC2/TPM3CH2 PTD7/KBI2P7 PTD6/KBI2P6

Pins in bold are added from the next smaller package.

Figure 2. Pin Assignments in 80-Pin LQFP

MC9S08QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 5

PTD5/KBI2P5 PTJ7 PTJ6 PTJ5 PTJ4 PTC1/TPM3CH1 PTC0/TPM3CH0 PTF7/ADP17 PTF6/ADP16 PTF5/ADP15 PTF4/ADP14 PTB3/KBI1P7/MOSI1/ADP7 PTB2/KBI1P6/SPSCK1/ADP6

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

PTE0/TPM2CLK/SPSCK1 PTE1/MOSI1 PTG0 PTG1 PTG2/ADP18 PTG3/ADP19 PTE2/MISO1 PTE3/SS1 PTG4/ADP20 PTG5/ADP21 PTG6/ADP22 PTG7/ADP23 PTC6/RxD2/ACMP2+

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

PTA2/KBI1P2/SDA1/ADP2 PTA3/KBI1P3/SCL1/ADP3 PTD2/KBI2P2/MISO2 PTD3/KBI2P3/SS2 PTD4/KBI2P4 PTJ0 PTJ1 PTF0/ADP10 PTF1/ADP11 VSS VDD PTE4 PTA6/TPM1CH2/ADP8 PTA7/TPM2CH2/ADP9 PTF2/ADP12 PTF3/ADP13 PTJ2 PTJ3 PTB0/KBI1P4/RxD1/ADP4 PTB1/KBI1P5/TxD1/ADP5

Pin Assignments
PTC7/TxD2/ACMP2PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+ PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1-

PTA5/IRQ/TPM1CLK/RESET PTC4/TPM3CH4/RSTO PTC5/TPM3CH5/ACMP2O

PTA4/ACMP1O/BKGD/MS

PTE0/TPM2CLK/SPSCK1 PTE1/MOSI1 PTG0 PTG1 PTG2/ADP18 PTG3/ADP19 PTE2/MISO1 PTE3/SS1

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

PTC6/RxD2/ACMP2+

PTD1/KBI2P1/MOSI2 PTD0/KBI2P0/SPSCK2 PTH7/SDA2 PTH6/SCL2 PTE7/TPM3CLK VDD VDDAD VREFH VREFL VSSAD VSS PTB7/SCL1/EXTAL PTB6/SDA1/XTAL PTH1 PTH0 PTE6

Pins in bold are added from the next smaller package.

Figure 3. Pin Assignments in 64-Pin LQFP Package

MC9S08QE128 Series Data Sheet, Rev. 7 6 Freescale Semiconductor

PTD5/KBI2P5 PTC1/TPM3CH1 PTC0/TPM3CH0 PTF7/ADP17 PTF6/ADP16 PTF5/ADP15 PTF4/ADP14 PTB3/KBI1P7/MOSI1/ADP7 PTB2/KBI1P6/SPSCK1/ADP6

PTE5 PTB5/TPM1CH1/SS1 PTB4/TPM2CH1/MISO1 PTC3/TPM3CH3 PTC2/TPM3CH2 PTD7/KBI2P7 PTD6/KBI2P6

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

PTA2/KBI1P2/SDA11/ADP2 PTA3/KBI1P3/SCL1/ADP3 PTD2/KBI2P2/MISO2 PTD3/KBI2P3/SS2 PTD4/KBI2P4 PTF0/ADP10 PTF1/ADP11 VSS VDD PTE4 PTA6/TPM1CH2/ADP8 PTA7/TPM2CH2/ADP9 PTF2/ADP12 PTF3/ADP13 PTB0/KBI1P4/RxD1/ADP4 PTB1/KBI1P5/TxD1/ADP5

Freescale Semiconductor
PTD0/KBI2P0/SPSCK2 2 PTD1/KBI2P1/MOSI2 1 PTE7/TPM3CLK 3 VDDAD 5 VSSAD 8 VREFL 7 VDD 4 VREFH 6 VSS 9 PTB7/SCL1/EXTAL 10 PTB6/SDA11/XTAL 11 48 PTA4/ACMP1O/BKGD/MS 47 PTA5/IRQ/TPM1CLK/RESET 46 PTC4/TPM3CH4/RSTO 45 PTC5/TPM3CH5/ACMP2O 44 PTE0/TPM2CLK/SPSCK1 43 PTE1/MOSI1 42 PTE2/MISO1 41 PTE3/SS1 40 PTC6/RxD2/ACMP2+ 39 PTC7/TxD2/ACMP238 PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+ PTA1/KBI1P1/TPM2CH0/ADP1/ACMP137 PTA1/KBI1P1/TPM2CH0/AD 31 VSS 30 VDD 29 PTE4 32 PTD4/KBI2P4 33 PTD3/KBI2P3/SS2 34 PTD2/KBI2P2/MISO2 27 PTA7/TPM2CH2/ADP9 28 PTA6/TPM1CH2/ADP8 26 PTB0/KBI1P4/RxD1/ADP4 35 PTA3/KBI1P3/SCL1/ADP3 36 PTA2/KBI1P2/SDA1/ADP2 PTE6 12 PTE5 13 PTB5/TPM1CH1/SS1 14 PTB4/TPM2CH1/MISO1 15 PTC3/TPM3CH3 16 PTC2/TPM3CH2 17 PTD7/KBI2P7 18 PTD6/KBI2P6 19 PTD5/KBI2P5 20 PTC1/TPM3CH1 21 PTC0/TPM3CH0 22 PTB3/KBI1P7/MOSI1/ADP7 23 PTB2/KBI1P6/SPSCK1/ADP6 24 25 PTB1/KBI1P5/TxD1/ADP5

Figure 4. Pin Assignments in 48-Pin QFN Package

MC9S08QE128 Series Data Sheet, Rev. 7

Pin Assignments

Pin Assignments
PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+ 35

PTC6/RxD2/ACMP2+

43

42

41

44

40

39

38

37

36

PTC7/TxD2/ACMP2-

PTD1/KBI2P1/MOSI2 PTD0/KBI2P0/SPSCK2 PTE7/TPM3CLK VDD VDDAD VREFH VREFL VSSAD VSS PTB7/SCL1/EXTAL PTB6/SDA1/XTAL 11

34

PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1-

PTA5/IRQ/TPM1CLK/RESET

PTC5/TPM3CH5/ACMP2O

PTA4/ACMP1O/BKGD/MS

PTC4/TPM3CH4/RSTO

PTE0/TPM2CLK

PTE1

PTE2

1 2 3 4 5 6 7 8 9

33 32 31 30 29

PTA2/KBI1P2/SDA1/ADP2 PTA3/KBI1P3/SCL1/ADP3 PTD2/KBI2P2/MISO2 PTD3/KBI2P3/SS2 PTD4/KBI2P4 VSS VDD PTA6/TPM1CH2/ADP8 PTA7/TPM2CH2/ADP9 PTB0/KBI1P4/RxD1/ADP4 PTB1/KBI1P5/TxD1/ADP5

28 27 26 25 24 13 14 15 16 17 18 19 20 21 PTB3/KBI1P7/MOSI1/ADP7 22 PTB2/KBI1P6/SPSCK1/ADP6 23

10 12

PTB4/TPM2CH1/MISO1

PTB5/TPM1CH1/SS1

PTC3/TPM3CH3

PTC2/TPM3CH2

PTD7/KBI2P7

Figure 5. Pin Assignments in 44-Pin LQFP Package

MC9S08QE128 Series Data Sheet, Rev. 7 8 Freescale Semiconductor

PTC1/TPM3CH1

PTC0/TPM3CH0

PTD6/KBI2P6

PTD5/KBI2P5

Pin Assignments
PTA0/KBIP0/TPM1CH0/ADP0/ACMP1 26 PTA1/KBIP1/TPM2CH0/ADP1/ACMP1 25 24 23 22 21 20 19 18 17 9 PTB5/TPM1CH1/SS1 10 PTB4/TPM2CH1/MISO1 PTA2/KBIP2/SDA1/ADP2 PTA3/KBIP3/SCL1/ADP3 PTD2/KBI2P2/MISO2 PTD3/KBI2P3/SS2 PTA6/TPM1CH2/ADP8 PTA7/TPM2CH2/ADP9 PTB0/KBI1P4/RxD1/ADP4 PTB1/KBI1P5/TxD1/ADP5 16 PTB2/KBI1P6/SPSCK1/ADP6

PTA5/IRQ/TPM1CLK/RESET

PTA4/ACMP1O/BKGD/MS

PTC5/TPM3CH5/ACMP2O

PTC4/TPM3CH4/RSTO

PTC6/RxD2/ACMP2+ 28

32 PTD1/KBI2P1/MOSI2 PTD0/KBI2P0/SPSCK2 VDD VREFH/VDDAD VREFL/VSSAD VSS PTB7/SCL1/EXTAL PTB6/SDA1/XTAL 1 2 3 4 5 6 7 8

31

30

29

PTC7/TxD2/ACMP227 14 PTC0/TPM3CH0

11
PTC3/TPM3CH3

12 PTC2/TPM3CH2

13 PTC1/TPM3CH1

15 PTB3/KBI1P7/MOSI1/ADP7

Figure 6. Pin Assignments 32-Pin LQFP Package

MC9S08QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 9

Pin Assignments

Table 2. MC9S08QE128 Series Pin Assignment by Package and Pin Count

Pin Number 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PTB7 PTB6 PTH3 PTH2 PTH1 PTH0 PTE6 PTE5 PTB5 PTB4 PTC3 PTC2 PTD7 PTD6 PTD5 PTJ7 PTJ6 PTJ5 PTJ4 PTC1 PTC0 PTF7 PTF6 PTF5 PTF4 PTB3 PTB2 KBI1P7 KBI1P6 MOSI1 SPSCK1 TPM3CH1 TPM3CH0 ADP17 ADP16 ADP15 ADP14 ADP7 ADP6 TPM1CH1 SS1 TPM2CH1 MISO1 TPM3CH3 TPM3CH2 KBI2P7 KBI2P6 KBI2P5 SCL1 SDA1 Lowest Port Pin PTD1 PTD0 PTH7 PTH6 PTH5 PTH4 PTE7 TPM3CLK VDD VDDA VREFH VREFL VSSA VSS EXTAL XTAL Alt 1 KBI2P1 KBI2P0 SDA2 SCL2 Priority Alt 2 MOSI2 SPSCK2 Alt 3 Highest Alt 4

MC9S08QE128 Series Data Sheet, Rev. 7 10 Freescale Semiconductor

Pin Assignments

Table 2. MC9S08QE128 Series Pin Assignment by Package and Pin Count (continued)
Pin Number 80 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 64 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 48 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 44 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 32 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PTF1 PTF0 PTJ1 PTJ0 PTD4 PTD3 PTD2 PTA3 PTA2 PTA1 PTA0 PTC7 PTC6 PTG7 PTG6 PTG5 PTG4 PTE3 PTE2 PTG3 PTG2 PTG1 PTG0 PTE1 PTE0 PTC5 PTC4 PTA5 PTA4 MOSI1 TPM2CLK SPSCK1 TPM3CH5 TPM3CH4 RSTO IRQ ACMP1O TPM1CLK RESET BKGD MS ACMP2O SS1 MISO1 ADP19 ADP18 KBI2P4 KBI2P3 KBI2P2 KBI1P3 KBI1P2 KBI1P1 KBI1P0 TxD2 RxD2 SS2 MISO2 SCL1 SDA1 TPM2CH0 ADP1 TPM1CH0 ADP0 ADP3 ADP2 ACMP1ACMP1+ ACMP2ACMP2+ ADP23 ADP22 ADP21 ADP20 Lowest Port Pin PTB1 PTB0 PTJ3 PTJ2 PTF3 PTF2 PTA7 PTA6 PTE4 VDD VSS ADP11 ADP10 TPM2CH2 TPM1CH2 ADP13 ADP12 ADP9 ADP8 Alt 1 KBI1P5 KBI1P4 Priority Alt 2 TxD1 RxD1 Alt 3 Highest Alt 4 ADP5 ADP4

MC9S08QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 11

Electrical Characteristics

3
3.1

Electrical Characteristics
Introduction

This section contains electrical and timing specifications for the MC9S08QE128 series of microcontrollers available at the time of publication.

3.2

Parameter Classification
Table 3. Parameter Classifications P C T D
Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations.

The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:

NOTE
The classification is shown in the column labeled C in the parameter tables where appropriate.

3.3

Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 4 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pull-up resistor associated with the pin is enabled. Table 4. Absolute Maximum Ratings
Rating Supply voltage Maximum current into VDD Digital input voltage Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 Storage temperature range
1

Symbol VDD IDD VIn ID Tstg

Value 0.3 to +3.8 120 0.3 to VDD + 0.3 25 55 to 150

Unit V mA V mA C

Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to V SS and VDD.

MC9S08QE128 Series Data Sheet, Rev. 7 12 Freescale Semiconductor

Electrical Characteristics
3

Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption).

3.4

Thermal Characteristics

This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table 5. Thermal Characteristics
Rating Operating temperature range (packaged) Maximum junction temperature Thermal resistance Single-layer board 32-pin LQFP 44-pin LQFP 48-pin QFN 64-pin LQFP 80-pin LQFP Thermal resistance Four-layer board 32-pin LQFP 44-pin LQFP 48-pin QFN 64-pin LQFP 80-pin LQFP JA JA 54 46 26 50 47 C/W C/W JA JA 82 68 81 69 60 C/W C/W Symbol TA TJM Value 40 to 85 95 Unit C C

The average chip-junction temperature (TJ) in C can be obtained from: TJ = TA + (PD JA) where: TA = Ambient temperature, C JA = Package thermal resistance, junction-to-ambient, C/W PD = Pint + PI/O Pint = IDD VDD, Watts chip internal power PI/O = Power dissipation on input and output pins user determined Eqn. 1

MC9S08QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 13

Electrical Characteristics

For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K (TJ + 273C) Solving Equation 1 and Equation 2 for K gives: K = PD (TA + 273C) + JA (PD)2 Eqn. 3 Eqn. 2

where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA.

3.5

ESD Protection and Latch-Up Immunity

Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM) and the charge device model (CDM). A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table 6. ESD and Latch-up Test Conditions
Model Human Body Description Series resistance Storage capacitance Number of pulses per pin Series resistance Machine Storage capacitance Number of pulses per pin Latch-up Minimum input voltage limit Maximum input voltage limit Symbol R1 C R1 C Value 1500 100 3 0 200 3 2.5 7.5 V V pF Unit pF

Table 7. ESD and Latch-Up Protection Characteristics

No. 1 2 3 4
1

Rating1 Human body model (HBM) Machine model (MM) Charge device model (CDM) Latch-up current at TA = 85C

Symbol VHBM VMM VCDM ILAT

Min 2000 200 500 100

Max

Unit V V V mA

Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted.

MC9S08QE128 Series Data Sheet, Rev. 7 14 Freescale Semiconductor

Electrical Characteristics

3.6

DC Characteristics
Table 8. DC Characteristics

This section includes information about power supply requirements and I/O pin characteristics.

Num C 1 C 2 P T C 3 D C 4 P T C 5 6 D Output low current Output high current Output low voltage

Characteristic Operating Voltage Output high voltage All I/O pins, low-drive strength All I/O pins, high-drive strength

Symbol

Condition

Min 1.82

Typ1

Max 3.6

Unit V

1.8 V, ILoad = 2 mA VOH

VDD 0.5

0.6 1.4 2.16 2.21

100 0.5 0.5 0.5 0.5 100 0.35 x VDD 0.30 x VDD 1 1 52.5 0.2 5 8 1.0 1.79 2.22 2.27 mV A A k mA mA pF V V s V V mA V mA V

2.7 V, ILoad = 10 mA VDD 0.5 2.3 V, ILoad = 6 mA 1.8V, ILoad = 3 mA VDD 0.5 VDD 0.5 1.8 V, ILoad = 2 mA VDD > 2.7 V VDD > 1.8 V VDD > 2.7 V VDD >1.8 V 0.70 x VDD 0.85 x VDD 0.06 x VDD VIn = VDD or VSS VIn = VDD or VSS 17.5 0.2

Max total IOH for all ports All I/O pins, low-drive strength All I/O pins, high-drive strength

IOHT

VOL

2.7 V, ILoad = 10 mA 2.3 V, ILoad = 6 mA 1.8 V, ILoad = 3 mA

Max total IOL for all ports all digital inputs

IOLT VIH VIL Vhys |IIn| |IOZ| RPU

P Input high voltage C P Input low voltage C C Input hysteresis P P P Input leakage current Hi-Z (off-state) leakage current Pull-up resistors

7 8 9 10 11

all digital inputs

all digital inputs all input only pins (Per pin) all input/output (per pin) all digital inputs, when enabled Single pin limit Total MCU limit, includes sum of all stressed pins

12 13 14 15 16 17

DC injection 3, 4, 5 D current

IIC CIn VRAM VPOR tPOR VLVDH8

VIN < VSS, VIN > VDD

5 0.9 10

C Input Capacitance, all pins C RAM retention voltage C POR re-arm voltage6

D POR re-arm time P Low-voltage detection threshold high range7

VDD falling VDD rising

2.11 2.16

MC9S08QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 15

Electrical Characteristics

Table 8. DC Characteristics (continued)

Num C 18 19 20 21 22
1 2 3 4 5

Characteristic Low-voltage detection threshold low range7 Low-voltage warning threshold high range7 Low-voltage warning threshold low range7 Low-voltage inhibit reset/recover hysteresis7

Symbol VLVDL VLVWH VLVWL Vhys VBG

Condition VDD falling VDD rising VDD falling VDD rising VDD falling VDD rising

Min 1.80 1.86 2.36 2.36 2.11 2.16 1.15

Typ1 1.82 1.90 2.46 2.46 2.16 2.21 50 1.17

Max 1.91 1.99 2.56 2.56 2.22 2.27 1.18

Unit V V V mV V

P P P C

P Bandgap Voltage Reference9

6 7 8 9

Typical values are measured at 25C. Characterized, not tested As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above VLVDL. All functional non-supply pins are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). Maximum is highest voltage that POR is guaranteed.

Low voltage detection and warning limits measured at 1 MHz bus frequency.
Run at 1 MHz bus frequency Factory trimmed at VDD = 3.0 V, Temp = 25C
PULL-DOWN RESISTANCE (k) 40 PULL-UP RESISTOR TYPICALS 85C 25C 40C PULL-DOWN RESISTOR TYPICALS 85C 25C 40C

PULL-UP RESISTOR (k)

40 35 30 25 20 1.8

35 30 25 20 1.8

2.2

2.4

2.6 2.8 VDD (V)

3.2

3.4

3.6

2.3

2.8 VDD (V)

3.3

3.6

Figure 7. Pull-up and Pull-down Typical Resistor Values

MC9S08QE128 Series Data Sheet, Rev. 7 16 Freescale Semiconductor

Electrical Characteristics
TYPICAL VOL VS IOL AT VDD = 3.0 V
85C 25C 40C

1.2 1 0.8 VOL (V)

0.2 0.15 VOL (V) 0.1 0.05 0

TYPICAL VOL VS VDD

0.6 0.4 0.2 0 0 5 10 IOL (mA) 15 20

85C, IOL = 2 mA 25C, IOL = 2 mA 40C, IOL = 2 mA

VDD (V)

Figure 8. Typical Low-Side Driver (Sink) Characteristics Low Drive (PTxDSn = 0)

TYPICAL VOL VS IOL AT VDD = 3.0 V
85C 25C 40C

1 0.8 VOL (V) 0.6 0.4 0.2 0 0

TYPICAL VOL VS VDD 0.4 0.3 VOL (V) 0.2 0.1 0 IOL = 6 mA IOL = 3 mA 1 2 VDD (V) 3 4
85C 25C 40C

IOL = 10 mA

10 IOL (mA)

20

30

Figure 9. Typical Low-Side Driver (Sink) Characteristics High Drive (PTxDSn = 1)

TYPICAL VDD VOH VS IOH AT VDD = 3.0 V VDD VOH (V)
85C 25C 40C

1.2 VDD VOH (V) 1 0.8 0.6 0.4 0.2 0 0

0.25 0.2 0.15 0.1 0.05 0

TYPICAL VDD VOH VS VDD AT SPEC IOH

85C, IOH = 2 mA 25C, IOH = 2 mA 40C, IOH = 2 mA

10 IOH (mA))

15

20

VDD (V)

Figure 10. Typical High-Side (Source) Characteristics Low Drive (PTxDSn = 0)

MC9S08QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 17

Electrical Characteristics
TYPICAL VDD VOH VS VDD AT SPEC IOH
85C 25C 40C

0.4
0.8 0.6 0.4 0.2 0 0 5 10 15 20 IOH (mA) 25 30 TYPICAL VDD VOH VS IOH AT VDD = 3.0 V

VDD VOH (V)

85C 25C 40C

VDD VOH (V)

0.3 0.2 0.1 0 1

IOH = 10 mA IOH = 6 mA IOH = 3 mA 2 VDD (V) 3 4

Figure 11. Typical High-Side (Source) Characteristics High Drive (PTxDSn = 1)

3.7

Supply Current Characteristics

Table 9. Supply Current Characteristics

This section includes information about power supply current in various operating modes.

Num

C P P

Parameter Run supply current FEI mode, all modules on

Symbol

Bus Freq 25.165 MHz

VDD (V)

Typ1 16 16

Max 18 20 12.3

Unit

Temp (C) 40 to 25 85

T T T C Run supply current FEI mode, all modules off

RIDD

20 MHz 8 MHz 1 MHz 25.165 MHz

14.4 6.5 1.4 11.5

mA 40 to 85

T T T T

RIDD

20 MHz 8 MHz 1 MHz

9.5 4.6 1.0 152

mA

40 to 85

3 T

Run supply current LPS=0, all modules off

RIDD

16 kHz FBILP 16 kHz FBELP

3 115 21.9

40 to 85

T 4 T C 5 T T T

Run supply current LPS=1, all modules off, running from Flash Run supply current LPS=1, all modules off, running from RAM Wait mode supply current FEI mode, all modules off

0 to 70 40 to 85 A 0 to 70 40 to 85

RIDD

16 kHz FBELP

3 7.3

6 mA

25.165 MHz WIDD 20 MHz 8 MHz 1 MHz 3

5.74 4.57 2 0.73

-40 to 85

MC9S08QE128 Series Data Sheet, Rev. 7 18 Freescale Semiconductor

Electrical Characteristics

Table 9. Supply Current Characteristics (continued)

Num C P C 6 P C C C P C 7 P C C C
1

Parameter Stop2 mode supply current

Symbol

Bus Freq

VDD (V)

Typ1 0.35

Max 0.6 2.0 7.5 0.5 1.9 6.5 1.0 4.2 15.0 0.7 3.9 13.2

Unit

Temp (C) -40 to 25 70

3 S2IDD n/a 2

0.98 2.5 0.25 1.4 1.91

85 -40 to 25 70 85 -40 to 25 70

Stop3 mode supply current No clocks active S3IDD n/a

0.45 3 1.99 5.0 0.35 2 2.9 3.77

85 -40 to 25 70 85

Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value.

Table 10. Stop Mode Adders

Temperature (C) Num 1 2 3 4 5 6 7
1

C T T T T T T T

Parameter LPO ERREFSTEN IREFSTEN1 RTC LVD1 ACMP ADC1

1

Condition -40 50 RANGE = HGO = 0 1000 63 does not include clock source current LVDSE = 1 not using the bandgap (BGBE = 0) ADLPC = ADLSMP = 1 not using the bandgap (BGBE = 0) 50 90 18 95 25 75 1000 70 75 100 20 106 70 100 1100 77 100 110 22 114 85 150 1500 81 150 115 23 120

Units nA nA uA nA uA uA uA

Not available in stop2 mode.

MC9S08QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 19

Electrical Characteristics

18.00

16.00

14.00

12.00 FEI: 24 MHz FBELP: 24 MHz FEI: 8 MHz FBELP: 8 MHz FEI: 1 MHz FBELP: 1 MHz

IDD (mA)

10.00

8.00

6.00

4.00

2.00

0.00 1.8 2 2.2 2.4 VDD (V) 2.6 2.8 3

Figure 12. Typical Run IDD for FBE and FEI, IDD vs. VDD (ADC off, All Other Modules Enabled)

MC9S08QE128 Series Data Sheet, Rev. 7 20 Freescale Semiconductor

Electrical Characteristics

3.8

External Oscillator (XOSC) Characteristics

Table 11. XOSC and ICS Specifications (Temperature Range = 40 to 85C Ambient)

Reference Figure 13 and Figure 14 for crystal or resonator circuits.

Num

Characteristic

Symbol flo fhi fhi C1,C2

Min 32 1 1

Typ1

Max 38.4 16 8

Unit kHz MHz MHz

Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) Low range (RANGE = 0) C High range (RANGE = 1), high gain (HGO = 1) High range (RANGE = 1), low power (HGO = 0) D Load capacitors Low range (RANGE=0), low power (HGO=0) Other oscillator settings

See Note2 See Note3 10 1 0 100 0 0 0 200 400 5 15 0 10 20 40.0 50.33

Feedback resistor Low range, low power (RANGE=0, HGO=0)2 D Low range, High Gain (RANGE=0, HGO=1) High range (RANGE=1, HGO=X) Series resistor Low range, low power (RANGE = 0, HGO = 0)2 Low range, high gain (RANGE = 0, HGO = 1) High range, low power (RANGE = 1, HGO = 0) D High range, high gain (RANGE = 1, HGO = 1) 8 MHz 4 MHz 1 MHz Crystal start-up time 4 Low range, low power Low range, high power C High range, low power High range, high power D Square wave input clock frequency (EREFS = 0, ERCLKEN = 1) FEE or FBE mode FBELP mode

RF

RS

t CSTL t CSTH

0.03125 0

ms

6
1 2

fextal

MHz MHz

Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value. Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE=HGO=0. 3 See crystal or resonator manufacturers recommendation. 4 Proper PC board layout procedures must be followed to achieve specifications.

MC9S08QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 21

Electrical Characteristics

XOSC EXTAL XTAL RS

RF

C1

Crystal or Resonator C2

Figure 13. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain

XOSC EXTAL XTAL

Crystal or Resonator

Figure 14. Typical Crystal or Resonator Circuit: Low Range/Low Gain

3.9
Num 1 2 3 C P P T P 4 P P P 5 P P 6 7 C C

Internal Clock Source (ICS) Characteristics

Table 12. ICS Frequency Specifications (Temperature Range = 40 to 85C Ambient)
Characteristic Average internal reference frequency factory trimmed at VDD = 3.6 V and temperature = 25C Internal reference frequency user trimmed Internal reference start-up time Low range (DRS=00) DCO output frequency range trimmed 2 DCO output frequency 2 Reference = 32768 Hz and DMX32 = 1 Mid range (DRS=01) High range (DRS=10) Low range (DRS=00) Mid range (DRS=01) High range (DRS=10) fdco_res_t fdco_res_t fdco_DMX32 fdco_u Symbol fint_ft fint_ut tIRST Min 31.25 16 32 48 Typ1 32.768 60 19.92 39.85 59.77 0.1 0.2 Max 39.06 100 20 40 60 0.2 0.4 %fdco %fdco MHz MHz Unit kHz kHz s

Resolution of trimmed DCO output frequency at fixed voltage and temperature (using FTRIM) Resolution of trimmed DCO output frequency at fixed voltage and temperature (not using FTRIM)

MC9S08QE128 Series Data Sheet, Rev. 7 22 Freescale Semiconductor

Electrical Characteristics

Table 12. ICS Frequency Specifications (Temperature Range = 40 to 85C Ambient) (continued)
Num 8 9 10 11
1 2

C C C

Characteristic Total deviation of trimmed DCO output frequency over voltage and temperature Total deviation of trimmed DCO output frequency over fixed voltage and temperature range of 0C to 70 C

Symbol fdco_t fdco_t tAcquire CJitter

Min

Typ1 + 0.5 -1.0 0.5 0.02

Max 2 1 1 0.2

Unit %fdco %fdco ms %fdco

C FLL acquisition time 3 C Long term jitter of DCO output clock (averaged over 2-ms interval) 4

Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value. The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device. 3 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 4 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f Bus. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval.

0.60%

0.40%

0.20%

0.00% -40
% deviation

-20

20

40

60

80

100

120

-0.20%

-0.40%

-0.60%

-0.80%

-1.00% VDD

Figure 15. Deviation of DCO Output Across Temperature at VDD = 3.0 V

MC9S08QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 23

Electrical Characteristics

0.50%

0.40%

0.30%

0.20%

0.10%
% deviation

0.00% 2.1V -0.10%

2.4V

2.7V

3.0V

3.3V

3.6V

-0.20%

-0.30%

-0.40%

-0.50% VDD

Figure 16. Deviation of DCO Output Across VDD at 25C

3.10
3.10.1
Num

AC Characteristics
Control Timing
Table 13. Control Timing
C Rating Bus frequency (tcyc = 1/fBus) VDD 1.8V VDD > 2.1V VDD > 2.4V Internal low power oscillator period External reset pulse Reset low drive BKGD/MS setup time after issuing background debug force reset to enter user or BDM modes BKGD/MS hold time after issuing background debug force reset to enter user or BDM modes 3 width2 Symbol Min Typ1 Max 10 20 25.165 1300 Unit

This section describes timing characteristics for each peripheral system.

fBus tLPO textrst trstdrv tMSSU tMSH

dc

MHz

2 3 4 5 6

D D D D D

700 100 34 x tcyc 500 100

s ns ns ns s

MC9S08QE128 Series Data Sheet, Rev. 7 24 Freescale Semiconductor

Electrical Characteristics

Table 13. Control Timing (continued)

Num 7 C D IRQ pulse width Asynchronous path2 Synchronous path4 Keyboard interrupt pulse width Asynchronous path2 Synchronous path4 Port rise and fall time Low output drive (PTxDS = 0) (load = 50 pF)5 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) Port rise and fall time High output drive (PTxDS = 1) (load = 50 pF) Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) Voltage regulator recovery time Rating Symbol tILIH, tIHIL Min 100 1.5 x tcyc 100 1.5 x tcyc Typ1 Max Unit

ns

tILIH, tIHIL

ns

tRise, tFall

8 31

ns

tRise, tFall tVRR

7 24 4

ns

10
1 2

Typical values are based on characterization data at VDD = 3.0V, 25C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a reset or interrupt pin request. Shorter pulses are not guaranteed to override reset requests from internal sources. 3 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t MSH after VDD rises above VLVD. 4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 5 Timing is shown with respect to 20% V DD and 80% VDD levels. Temperature range 40C to 85C.
textrst RESET PIN

Figure 17. Reset Timing

tIHIL KBIPx

IRQ/KBIPx tILIH

Figure 18. IRQ/KBIPx Timing

MC9S08QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 25

Electrical Characteristics

3.10.2

TPM Module Timing

Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table 14. TPM Input Timing
No. 1 2 3 4 5 C D D D D D Function External clock frequency External clock period External clock high time External clock low time Input capture pulse width Symbol fTCLK tTCLK tclkh tclkl tICPW
tTCLK tclkh TCLK tclkl

Min 0 4 1.5 1.5 1.5

Max fBus/4

Unit Hz tcyc tcyc tcyc tcyc

Figure 19. Timer External Clock

tICPW TPMCHn

TPMCHn tICPW

Figure 20. Timer Input Capture Pulse

MC9S08QE128 Series Data Sheet, Rev. 7 26 Freescale Semiconductor

Electrical Characteristics

3.10.3

SPI Timing
Table 15. SPI Timing

Table 15 and Figure 21 through Figure 24 describe the timing requirements for the SPI system.

No.

C D

Function Operating frequency Master Slave SPSCK period Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SPSCK) high or low time Master Slave Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Slave access time Slave MISO disable time Data valid (after SPSCK edge) Master Slave Data hold time (outputs) Master Slave Rise time Input Output Fall time Input Output

Symbol fop

Min fBus/2048 0 2 4 1/2 1 1/2 1 tcyc 30 tcyc 30 15 15 0 25 0 0

Max fBus/2 fBus/4 2048 1024 tcyc 1 1 25 25 tcyc 25 25 tcyc 25 25

Unit Hz Hz tcyc tcyc tSPSCK tcyc tSPSCK tcyc ns ns ns ns ns ns tcyc tcyc ns ns ns ns ns ns ns ns

tSPSCK

tLead

tLag

tWSPSCK

tSU

6 7 8 9

D D D D

tHI

ta tdis tv

10

tHO

11

tRI tRO tFI tFO

12

MC9S08QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 27

Electrical Characteristics
SS1 (OUTPUT) 2 SPSCK (CPOL = 0) (OUTPUT) SPSCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT) MSB OUT2 6 MSB IN2 BIT 6 . . . 1 9 BIT 6 . . . 1 LSB OUT LSB IN
10

1 4 4

11

12

NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 21. SPI Master Timing (CPHA = 0)

SS(1) (OUTPUT) 1 2 SPSCK (CPOL = 0) (OUTPUT) SPSCK (CPOL = 1) (OUTPUT) MISO (INPUT) 9 MOSI (OUTPUT) PORT DATA MASTER MSB OUT(2) 4 4
11 12 12 11

6 MSB IN(2) BIT 6 . . . 1

10

LSB IN

BIT 6 . . . 1

MASTER LSB OUT

PORT DATA

NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 22. SPI Master Timing (CPHA =1)

MC9S08QE128 Series Data Sheet, Rev. 7 28 Freescale Semiconductor

Electrical Characteristics
SS (INPUT) 1 SPSCK (CPOL = 0) (INPUT) 2 SPSCK (CPOL = 1) (INPUT) 7 MISO (OUTPUT) SLAVE 5 MOSI (INPUT)
NOTE:

12

11

11

12

8 9 MSB OUT 6 MSB IN BIT 6 . . . 1 LSB IN BIT 6 . . . 1

10 10

SLAVE LSB OUT

SEE NOTE

1. Not defined but normally MSB of character just received

Figure 23. SPI Slave Timing (CPHA = 0)

SS (INPUT) 1 SPSCK (CPOL = 0) (INPUT) SPSCK (CPOL = 1) (INPUT) MISO (OUTPUT) SEE NOTE 7 MOSI (INPUT) 2
12

3
11

11

12

9 SLAVE 5 MSB IN MSB OUT 6

10

8 SLAVE LSB OUT

BIT 6 . . . 1

BIT 6 . . . 1

LSB IN

NOTE: 1. Not defined but normally LSB of character just received

Figure 24. SPI Slave Timing (CPHA = 1)

MC9S08QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 29

Electrical Characteristics

3.11
C D C D C C P C

Analog Comparator (ACMP) Electricals

Table 16. Analog Comparator Electrical Specifications
Characteristic Supply voltage Supply current (active) Analog input voltage Analog input offset voltage Analog comparator hysteresis Analog input leakage current Analog comparator initialization delay Symbol VDD IDDAC VAIN VAIO VH IALKG tAINIT 3.0 Min 1.80 VSS 0.3 Typical 20 20 9.0 Max 3.6 35 VDD 40 15.0 1.0 1.0 Unit V A V mV mV A s

3.12
C D D D D D C C

ADC Characteristics
Table 17. 12-bit ADC Operating Conditions
Characteristic Conditions Absolute Delta to VDD (VDD-VDDAD)2 VSS (VSS-VSSAD)2 Symb VDDAD VDDAD VSSAD VREFH VREFL VADIN CADIN RADIN 12 bit mode fADCK > 4MHz fADCK < 4MHz 10 bit mode fADCK > 4MHz fADCK < 4MHz 8 bit mode (all valid fADCK) RAS Min 1.8 -100 -100 1.8 VSSAD VREFL fADCK 0.4 0.4 Typ1 0 0 VDDAD VSSAD 4.5 5 Max 3.6 +100 +100 VDDAD VSSAD VREFH 5.5 7 2 5 k 5 10 10 8.0 4.0 MHz Unit V mV mV V V V pF k External to MCU Comment

Supply voltage

Ground voltage Ref Voltage High Ref Voltage Low Input Voltage Input Capacitance Input Resistance Analog Source Resistance

Delta to

D
1

ADC Conversion High Speed (ADLPC=0) Clock Freq. Low Power (ADLPC=1)

Typical values assume VDDAD = 3.0V, Temp = 25C, fADCK=1.0MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 DC potential difference.

MC9S08QE128 Series Data Sheet, Rev. 7 30 Freescale Semiconductor

Electrical Characteristics
SIMPLIFIED INPUT PIN EQUIVALENT ZADIN CIRCUIT ZAS RAS VADIN VAS Pad leakage due to input protection SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN

ADC SAR ENGINE

CAS

RADIN INPUT PIN

RADIN

INPUT PIN

RADIN CADIN

INPUT PIN

Figure 25. ADC Input Impedance Equivalency Diagram Table 18. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)
Characteristic Supply Current ADLPC=1 ADLSMP=1 ADCO=1 Supply Current ADLPC=1 ADLSMP=0 ADCO=1 Supply Current ADLPC=0 ADLSMP=1 ADCO=1 Supply Current ADLPC=0 ADLSMP=0 ADCO=1 Supply Current ADC Asynchronous Clock Source Stop, Reset, Module Off High Speed (ADLPC=0) Low Power (ADLPC=1) Conditions C T Symb IDDAD Min Typ1 120 Max A Unit Comment

IDDAD

202

IDDAD

288

IDDAD

0.532

1 mA

P P P

IDDAD fADACK

2 1.25

0.007 3.3 2

0.8 5 3.3

A MHz tADACK = 1/fADACK

MC9S08QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 31

Electrical Characteristics

Table 18. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued)
Characteristic Conditions C P C P C T P T T P T T T T T P T T P T D EQ EFS EZS INL DNL ETUE tADS Symb tADC Min D EIL D m D VTEMP25 Typ1 20 40 3.5 23.5 3.0 1 0.5 1.75 0.5 0.3 1.5 0.5 0.3 1.5 0.5 0.5 1.0 0.5 0.5 -1 to 0 2 0.2 0.1 1.646 1.769 701.2 Max 2.5 1.0 1.0 0.5 1.0 0.5 1.5 0.5 1 0.5 0.5 0.5 4 1.2 mV mV/C LSB2 Pad leakage4 * RAS LSB2 LSB2 VADIN = VDDAD LSB2 VADIN = VSSAD LSB2 LSB2 Unit ADCK cycles ADCK cycles LSB2 Comment See the ADC chapter in the MC9S08QE128 Reference Manual for conversion time variances Includes Quantization

Conversion Time Short Sample (ADLSMP=0) (Including Long Sample (ADLSMP=1) sample time) Sample Time Short Sample (ADLSMP=0) Long Sample (ADLSMP=1) Total Unadjusted 12 bit mode Error 10 bit mode 8 bit mode Differential Non-Linearity 12 bit mode 10 bit mode3 8 bit mode3 Integral Non-Linearity 12 bit mode 10 bit mode 8 bit mode Zero-Scale Error 12 bit mode 10 bit mode 8 bit mode Full-Scale Error 12 bit mode 10 bit mode 8 bit mode Quantization Error 12 bit mode 10 bit mode 8 bit mode Input Leakage Error 12 bit mode 10 bit mode 8 bit mode Temp Sensor Slope Temp Sensor Voltage
1

-40C to 25C 25C to 85C 25C

Typical values assume VDDAD = 3.0V, Temp = 25C, fADCK=1.0MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (V N REFH - VREFL)/2 3 Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes 4 Based on input pad leakage current. Refer to pad electricals.

MC9S08QE128 Series Data Sheet, Rev. 7 32 Freescale Semiconductor

Electrical Characteristics

3.13

Flash Specifications

This section provides details about program/erase times and program-erase endurance for the flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see the Memory section of the MC9S08QE128 Reference Manual. Table 19. Flash Characteristics
C D D D D P P P P Characteristic Supply voltage for program/erase -40C to 85C Supply voltage for read operation Internal FCLK frequency1 Symbol Vprog/erase VRead fFCLK tFcyc tprog tBurst tPage tMass RIDDBP RIDDPE 10,000 tD_ret 15
3

Min 1.8 1.8 150 5

Typical

Max 3.6 3.6 200 6.67

Unit V V kHz s tFcyc tFcyc tFcyc tFcyc

Internal FCLK period (1/FCLK) Byte program time (random location)(2) Byte program time (burst Page erase Mass erase time2 time(2) mode)(2)

9 4 4000 20,000 4 6 100,000 100

Byte program current3 Page erase current C C

1 2

mA mA cycles years

Program/erase TL to TH = 40C to + 85C T = 25C Data retention5

endurance4

The frequency of this clock is controlled by a software setting. These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 3 The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures with VDD = 3.0 V, bus frequency = 4.0 MHz. 4 Typical endurance for flash was evaluated for this product family on the HC9S12Dx64. For additional information on how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. 5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.

MC9S08QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 33

Ordering Information

Ordering Information
Table 20. Ordering Information
Freescale Part Number1 MC9S08QE128CLK MC9S08QE128CLH MC9S08QE128CFT MC9S08QE128CLD MC9S08QE96CLK MC9S08QE96CLH MC9S08QE96CFT MC9S08QE96CLD MC9S08QE64CLH MC9S08QE64CFT MC9S08QE64CLD MC9S08QE64CLC 64K 4K 96K 6K 128K 8K Memory Flash RAM Temperature range (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 Package2 80 LQFP 64 LQFP 48 QFN 44 LQFP 80 LQFP 64 LQFP 48 QFN 44 QFP 64 LQFP 48 QFN 44 QFP 32 LQFP

This section contains ordering information for MC9S08QE128, MC9S08QE96, and MC9S08QE64 devices.

1 2

See the reference manual, MC9S08QE128RM, for a complete description of modules included on each device. See Table 21 for package information.

4.1

Device Numbering System

MC 9 S08 QE 128 C XX Status (MC = Fully Qualified) Memory (9 = Flash-based) Core Family

Example of the device numbering system:

Package designator (see Table 21) Temperature range (C = 40C to 85C) Approximate flash size in Kbytes

Package Information
Table 21. Package Descriptions
Pin Count 80 64 48 44 32 Package Type Low Quad Flat Package Low Quad Flat Package Quad Flat No-Leads Low Quad Flat Package Low Quad Flat Package Abbreviation LQFP LQFP QFN LQFP LQFP Designator LK LH FT LD LC Case No. 917A 840F 1314 824D 873A Document No. 98ASS23237W 98ASS23234W 98ARH99048A 98ASS23225W 98ASH70029A

The below table details the various packages available.

MC9S08QE128 Series Data Sheet, Rev. 7 34 Freescale Semiconductor

Package Information

5.1

Mechanical Drawings

The following pages are mechanical drawings for the packages described in Table 21. For the latest available drawings please visit our web site (http://www.freescale.com) and enter the packages document number into the keyword search box.

MC9S08QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 35

Package Information

4X

4X 20 TIPS

X
X= L, M, N

0.20 (0.008) H LM N
80 1 61 60

0.20 (0.008) T LM N C L AB AB M VIEW Y B V J

PLATING

3X

VIEW Y B1

V1

BASE METAL

20 21 40

41

N A1 S1 A S

0.13 (0.005)

SECTION ABAB

ROTATED 90 CLOCKWISE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE H IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS L, M AND N TO BE DETERMINED AT DATUM PLANE H. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE T. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.460 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). DIM A A1 B B1 C C1 C2 D E F G J K P R1 S S1 U V V1 W Z 0 01 02 MILLIMETERS MIN MAX 14.00 BSC 7.00 BSC 14.00 BSC 7.00 BSC 1.60 0.04 0.24 1.30 1.50 0.22 0.38 0.40 0.75 0.17 0.33 0.65 BSC 0.09 0.27 0.50 REF 0.325 BSC 0.10 0.20 16.00 BSC 8.00 BSC 0.09 0.16 16.00 BSC 8.00 BSC 0.20 REF 1.00 REF 0 10 0 9 14 INCHES MIN MAX 0.551 BSC 0.276 BSC 0.551 BSC 0.276 BSC 0.063 0.002 0.009 0.051 0.059 0.009 0.015 0.016 0.030 0.007 0.013 0.026 BSC 0.004 0.011 0.020 REF 0.013 REF 0.004 0.008 0.630 BSC 0.315 BSC 0.004 0.006 0.630 BSC 0.315 BSC 0.008 REF 0.039 REF 0 10 0 9 14

C H T
SEATING PLANE

8X

0.10 (0.004) T

VIEW AA (W) C2 0.05 (0.002)

S

1
2X R R1

0.25 (0.010)
GAGE PLANE

(K) C1 E (Z)

VIEW AA

DATE 09/21/95

CASE 917A-02 ISSUE C

Figure 26. 80-pin LQFP Package Drawing (Case 917A, Doc #98ASS23237W)

MC9S08QE128 Series Data Sheet, Rev. 7 36 Freescale Semiconductor

D U
M

T LM

Package Information

Figure 27. 64-pin LQFP Package Drawing (Case 840F, Doc #98ASS23234W), Sheet 1 of 3
MC9S08QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 37

Package Information

Figure 28. 64-pin LQFP Package Drawing (Case 840F, Doc #98ASS23234W), Sheet 2 of 3
MC9S08QE128 Series Data Sheet, Rev. 7 38 Freescale Semiconductor

Package Information

Figure 29. 64-pin LQFP Package Drawing (Case 840F, Doc #98ASS23234W), Sheet 3 of 3
MC9S08QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 39

Package Information

Figure 30. 48-pin QFN Package Drawing (Case 1314, Doc #98ARH99048A), Sheet 1 of 3

MC9S08QE128 Series Data Sheet, Rev. 7 40 Freescale Semiconductor

Package Information

Figure 31. 48-pin QFN Package Drawing (Case 1314, Doc #98ARH99048A), Sheet 2 of 3

MC9S08QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 41

Package Information

Figure 32. 48-pin QFN Package Drawing (Case 1314, Doc #98ARH99048A), Sheet 3 of 3

MC9S08QE128 Series Data Sheet, Rev. 7 42 Freescale Semiconductor

Package Information

Figure 33. 44-pin LQFP Package Drawing (Case 824D, Doc #98ASS23225W), Sheet 1 of 3

MC9S08QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 43

Package Information

Figure 34. 44-pin LQFP Package Drawing (Case 824D, Doc #98ASS23225W), Sheet 2 of 3

MC9S08QE128 Series Data Sheet, Rev. 7 44 Freescale Semiconductor

Package Information

Figure 35. 44-pin LQFP Package Drawing (Case 824D, Doc #98ASS23225W), Sheet 3 of 3

MC9S08QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 45

Package Information

Figure 36. 32-pin LQFP Package Drawing (Case 873A, Doc #98ASH70029A), Sheet 1 of 3
MC9S08QE128 Series Data Sheet, Rev. 7 46 Freescale Semiconductor

Package Information

Figure 37. 32-pin LQFP Package Drawing (Case 873A, Doc #98ASH70029A), Sheet 2 of 3

MC9S08QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 47

Package Information

Figure 38. 32-pin LQFP Package Drawing (Case 873A, Doc #98ASH70029A), Sheet 3 of 3

MC9S08QE128 Series Data Sheet, Rev. 7 48 Freescale Semiconductor

Product Documentation

Product Documentation
Reference Manual (MC9S08QE128RM) Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information.

Find the most current versions of all documents at: http://www.freescale.com

Revision History
http://www.freescale.com

To provide the most up-to-date information, the revision of our documents on the World Wide Web are the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: The following revision history table summarizes changes contained in this document. Table 22. Revision History
Revision 4 Date 9 Nov 2007 Description of Changes Replaced 44 QFP package with 44 LQFP package. Changed ACMP electricals, VAIO specifications test category from P to C. Updated the tables Thermal Characteristics, DC Characteristics, Supply Current Characteristics, XOSC and ICS Specifications (Temperature Range = 40 to 85C Ambient), ICS Frequency Specifications (Temperature Range = 40 to 85C Ambient), Control Timing, and Analog Comparator Electrical Specifications, 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) Updated the figures Typical Run IDD for FBE and FEI, IDD vs. VDD (ACMP and ADC off, All Other Modules Enabled), Deviation of DCO Output from Trimmed Frequency (50.33 MHz, 3.0 V), and Deviation of DCO Output from Trimmed Frequency (50.33 MHz, 25C) Updated the table Thermal Characteristics Updated the row corresponding to Num 18 in the table DC Characteristics Updated the tables MC9S08QE128 Series Features by MCU and Package, DC Characteristics, Supply Current Characteristics, Thermal Characteristics, Control Timing, and Ordering Information Updated the figures Typical Run IDD for FBE and FEI, IDD vs. VDD (ADC off, All Other Modules Enabled), Deviation of DCO Output Across Temperature at VDD = 3.0 V, and Deviation of DCO Output Across VDD at 25C Updated the Stop2 and Stop3 mode supply current in the Supply Current Characteristics table. Replaced the stop mode adders section from the Supply Current Characteristics with its own Stop Mode Adders table with new specifications.

28 May 2008

24 Jun 2008

2 Oct 2008

MC9S08QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 49

How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Document Number: MC9S08QE128

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Rev. 7 10/2008