Chapter

ding block for digital circuit design. As Fig. 11.1 the inverter paforms the logic operation of A to When the input to the is connected to ground, the output, in accord with the digital models in the last pchannel transistor. When the input terminal is through the n-channel MOSPET. The characteristics that a addressed in this chapter: m to ground unlike other logic families that never atic power dissipation of the CMOS inverter is be sized to give equal sourcing and sinking Id can be set by changing the size of the

A.

s chapter coneentram on the DC switching characteristics of the inverter and on times associated with driving capacitive loads and RC transmission lines, addnsses other types o inverters available in t eCMOS process. f h

-e r

1 . IheCMOS invcrta, schtmatie, and logic symbol. 11

204

Part Il CMOS Digital C i

-1

NMH = VOH VIH and the noise margin for the low logic levels is given by NML = Vn. VOL

For VDD = 5 V the ideal noise margins are 2 5 V;that is, NM, = NM, = VDDf2.. .

Example 1 . 12

For the minimum-size invertw in Ex. 11.1 detennine the noise

Comment on making the noise. margins closer to ideal. UsingEqs. (11.1) and(lI.Z),NM,=S-2A=2.6andNML= 1.7-O= 1.7 high noise margin is almost a whole volt greater than the lower noise n This is mainly because the inverter switching point, V,, is approximatel instead of the ideal case of 2.5 V or VDDn. This is discussed further in don. ximately unity. lbat is,
WI w 2 B.=$P=KP,,-=KP LI PL2 KP, = 3KP,, the width of the pchannel transistor must be three times the of the n-chanael, assuming equal-length MOSPETs. For V, = 2.5 V , this

111 Inverter Swltchlng Point 0 Consider the tmn

wz = 3w,

a channel length of 2 pm for the ratio of 3 W,= W,= 3 pm (one for the ratio of 1, set W,= 3 pm and W,= 9 p;for the ratio of In.

tching Characteristics
inverter can be genecdized by examining the parasitic sociated with the inverter. Consider the invertw.shown 1tP equivalent digital model. Although the model is shown with both in practice one of the switches is closed, lieepinp the output conoectsd to Notice that the effective input capacitance of the inverter is
Flpre 11A Transfer chara*cristics of the inverter showing the s ~ i

cfa= 3

+cod = chn + c p n i

(11.5)

output capacitance of the inverter is simply Solving for V , give3

11 The Inverter

207

c propagation delays of the inverter are

and simulate the inttinsic propagation delays of the minimum-size

the gtbdnin c a ~ a Input pulse rsedingthrough

Ftgarr 11.7 Inhinsic inverter delay.

I.
tpg~ =

R ~ I C a = R n l . (Cow + Clod .

.,I,

'

3-

I.

(11.10)

208

Part I1 CMOS Digital Cil

11 The Inverter

Example 11.6 Estimate and simulate the propagation delay of a minimum-size inverter dri a 100 fF capacitor.

ce that in the simulations, a zero risetime input results in delays somewhat than hand calculations indicate. W

The schematic of the minimum-size inverter driving a 100 f load and the l F d symbol of the inverter are shown in Rg. 11.8. The sizes adjacent to the in1 correspond to the ratio of the pchannel width to the n-channel width, assu the lengths of the MOSFETs are te same size. Usually, the lengths m h. minimum size available, which for CN20 is 2 pun. The total capacitance, on the output of the inverter is the sum of C,, the load capacitance am interconnecting capacitance. In this case C = 109.6 fF, assumin , = interconnecting capacitance. The propagation delay time8 arc then tPHL B and tpM= 2.63 ns. This can be compared to the simulation results of fig. 11 1

ered. If R,, = R,, ,the delay time8 are equal. This is equivalent to making W = , ch was the same requirement used in the previous section for making V = , The Ring O~ollfator number of inverters of the circuit shown in Fig. 11.10 fams a closed loop with feedback and is called a ring oscillator. The willation fnquency is given by
n . (tm +~PLH) the inveTters are identical and n is the number (odd) of inverters in the ring . Since the ring oscillator is self-starting, it is often added to a test portion of a
fm=

(11.11)

give an indication of the sped of a particular run.

Cm, = 2C, =2pn.3pm.C&,sothat

Figure 11.8 Inverter driving a 100 t load capacitsllcein Ex. 11.6. T
6.OV.

cw

+ 3C,

c,

= 5Cm

~PHL ~PLH (Rnl +Rpz)Cm =

2 = (12k + 36k)-. SCm= lMlk .Car (11.13) 3 nsider the case when the inverters are sized to give equal propagation delays to be identical, W must equal 3W,, which leads to a larger oxide ,

4.0V.

Ca.2 = 3C,1
c a m

(11.14)

2.0v.

C, = 4C, agation delays are given by

+ 6c,

c.

= lOC,
10C, = 160k. C ,

0. v-

-2.ov.

ens 1on

. .

~(voutf V(2)

1ms

14-

16na
Time

1811s

Figure 11.9 Sirnulatian results o minimum-silr inv&CY drivitl8 100 f

same as that given in Eq. (11.13). Although the e M v e resistance ofthe d u c a l by a factor of three, the capacitance of M, was increased by a In general, the ring oscillator fkquency is dependent on W,although one would expect Also note that only five invertem were used. In ta keep the oscillation frequency in the tens of MHz range. the number is31 (for-.

Part II CMOS Digital C

11 The Inverter

211

haracterize the speed of a digital process, a tenn called the power delay P) is often used The PDP, measured in joules, is detined by

(11.19) terms can be detamined from the ring oscillator circuit of the previous section. frequently used to compare different tectechogica o device sizss, for r have a lower propagation delay, the pow= dissipation may be larger

PDP= P ,

.(tm+t m )

the PDP of CN20, using hand analysis of a five-stage ring oscillator = W, = 10 pm. Simulate the oscillator with SPICE and compare the

rim CMOS inverter driving a capacitive load shown in Fig. 11.11, chaages states, it must either supply a charge to C,, or sin! to the input of the inll ,fa, the average amount of current that the invcurrent is king supplied from VDD only when the

tive resistances of the n- and p-channel MOSPETs are

R.1= 12k .-21un - 2 . 4 M 10 CIrn Rpz=361(.-2CIrn -7.2kn 10 CLm t capacitance of any inverter is

.--dynamic

power dissipated by the inverter is

Cow = Corn+ Cow= CI,(W"Ln + WpLp)=32 f P

dissipation is a function of the clock ffquency. A cing the power dissipation in CMOS circuits. One narmc logic (Ch. 15) is its lower power dissipation. capacitance on the output of any inverter is the sum of its own output ce and the input capacitance of the next (Identical) stage. This is given

C,=C.,+C*=80E

frequency,fromJ3q. (11.11),is then

sizei devices are specified. ,18),is (11,

I

Part 1 CMOS Digital ( 1

11 The Inverter

213

m average power dissipated per inverter, using e

(512 . (260 MHz) = 520 pW

The power delay product, using hand calculations, is 400 fJ (femto-joules). SPICE simulation gives a PDP of 330 fJ.

Figure 11.13 Two inverter layout styles.

-2.0~1
0s

5ns v(2)

1Ons

15ns

2011s

25

Time

Figure 11.12 SPICE simulation of the five-stage ring oscillator of Ex. 11.7.

11.3 Layout of the Inverter

If care is not taken when laying out CMOS circuits, the parasitic devices p cause a condition known as latch-up. Once latch-up occurs, the inverter outp change with the input; that is, the output may be stuck in a logic state. To problem, the power must be removed. Latch-up is especially troubling circuits. Manufacturers of integrated circuits often use NMOS inverters in this chapter) for output drivers, thus eliminating the possibility of latch-up.
11.3.1 Latch-up

1 and RW2 represent the effects of the resistance of the n-well, and 1 and RS2 represent the resistance of the substrate. The capacitors C1 and t the drain implant depletion capacitance, that is, the capacitance between of the transistors and the source and substrate. The parasitic circuit resulting inverter layout is shown in Fig. 11.15. output of the inverter switches fast enough, the pulse fed through C2 (for g inputs) can cause the base-ernitter junction of 4 2 to become forward s then causes the current through RW2 and RW1 to increase, causing Q1 to en Q1 is turned on, the current through RS1 and RS2 increases, causing n harder. This positive feedback will eventually cause Q2 and Q1 to turn and remain that way until the power is removed and reapplied. A similar can be made for negativegoing inputs feeding through C1.
a1 techniques reduce the latch-up problem. The first technique is to slow

Figure 11.13 illustrates two methods of laying out a minimum-size inv cross-sectional view in Fig. 11.14 shows both the n-channel and th MOSFETs that make up an inverter. Notice first that in Fig. 11.7, the feeds through the gate-drain capacitance. This causes the output to change in direction as the input before the inverter starts to switch. This feedthrou parasitic bipolar transistors cause the latch-up.

falltimes of the logic gates, reducing the amount of signal fed through C1 =@educing the areas of M1 find M2's drains lowers the size of the depletion d the amount of signal fed through. Probably the best meiod of up effects is to reduce the parasitic resistances RW1 and RS2. If these zero, Q1 and 4 2 never turn on. The value of these resistances, as seen

216

Part II CMOS Digital C

e help of Eq.(1 1.22):

11.4 Sizing for Large CapciUve Loads

Designing a circuit to drive large capacitive loads with minimum delay

when driving off-chip loads. Consider the inverter string driving a load
labeled C,, and shown in Fig. 11.17. If a single inverter were to drive Cw , times would be
~PHL

+t p w = (Rn +Rp) .(Cmr + C r d )

If, moving toward the load, cascading N inverters are used, each inverter previous by a factor A (that is, the width of each MOSFET is multip minimum delay can be obtained as long as A and N are picked inverter's input capacitance is also larger than the previous inverter's by a factor of A. If the load capacitance is q u d to the input capacitance o f inverter multiplied' by A, then Input C of final in-

term in this equation is the intrinsic delay of the fust inverter in our cascade of If we assume that this delay is small, solving thjs equation for Ngives
ld N=ln- co cl h

= C,, .AN= C W Z

( 1 1.27)

where C,,, is the input capacitance of the fmt inverter. Rearranging E .(11.20 q

and (11.22) are used to design a cascade of invertem in order to drive a

The total delay of the inverter string is given by

Rpt)

.(ACwI +AZ

acuaMwdd.y

where R,, and R,, are the effective resistances of the first inverter and capacitance of the first inverter. As the inverters are increased in 8 capacitances, both input and output, increase by A while their resistances factor A. The equation ( 1 1.23) can be written as
N

( t p + ~PLH)~,,,, ~ ~ =

(Rnl+RP~)(CwrlA c i d ) E N(R-I +Rpt)(Coutl+ A C d +

b l

Figure 11.17 Cascade ofinvcItem used to drive a Large load capaciuln

Consider this as if the load capacitance were simulating the input capacitance of inverter (if there was another invertn).

'

Designing a buffer begins with determining C,,. For the present case 28.8 fE The number of inverter6 using Bq. (1 1.27) is

seven inverters is negligible. If we did not want a logic inversion, we wa six stages. The areafa& is then

The total &lay, using Bq. (1 125, is then ..) (tpm +t p ~=7(16k)(19.2 F+2.55 .28.8 F) 10 ) ~ = or over 30 tifaster. SSincc the pchannel width is thne times that n-channel width, the pmpagation May times,,t and,t are equal, or tpm = tpui = 5.2 ns
A schematic of the design i shown in Fig. 11.18. The actual siec s changed to a number close to that given using the value of A calculated a make the layout easier. N&CCthat the first invatsr is the same inVer(8 above. m e SPICE simulation results are shown in Fig. 11.19. Note 1 unbuffered inverter does not fully charge the capacitor since the inpar inverter changes back to zero vls 15ns after it changes to VDD. ot

Figme 11.19 Simulaticm results from Ex. 11.8.

kn the buffer of Ex. 11.8 s that the delay, tP8' + t,m, o

w delay was 10.4 ns in Ex. 113.) u m

ple 11.9

is less than 15 ns.

maintain the logic invasion, either three or five stages should be 's begin by trying three stages. ' b e erea Eactor for thne stages is given A=[-Im=8.86 28.8 F is calculated using Eq. (11.25) and is given by
t m t m = 3(16k)(19.2 81+8.86.28.8

t ) 13.2 ns T=

Figure 11.18 Buffsr designed in Ex. 11.8.

= tpm = ~PLH 6.6 ns is shown in Fig. 11.20. The layout size of this buffer is er than the buffer designed iq E . 11.8, while the increase in x

It should be clear that, although this technique &ts in driving the 20pF load, the MOSPBTs needed are v w large. In many . minimum delay through a buffer is not requind. A specification that than some value is given. Consider the following example.

b e and efi
btly

it takes to lay out the large MOSFETs used in an output buffer can using cell hienuthy. As a simple example, let's lay out a 25Qn

77n

Part I CMOS Digital Cipq t

The Inverter

Input

++-hzopp
n
Output

Flwn 11.U) Buffer design of Ex. 11.9. -

n-channel MOSFET. We begin by creating a cell, called NAA25X2 (n-activ by 2), with a rank of 1 and shown in Fig. 11.21.

. . . . . . . . . . . . . . . . . . . . . .. .. .. .. . . . . .. .. .. .. .. .. . .. .. .. .. . . .... .................. ................... ................... ........... ........... Dt . . . . . . . . . . . . . . . . . . . . ........... ........... ............. . . . . . . . . . . . ............. ........... ...........

...........
. . . . . . . . . . .

. . . .

........... ...........

. . . .

. . . .

........ ........ ........ ........

............. ............. . . . . , . . . . . . . . ., ............. .............

F'lacing basic cells t f a m a large MOSFBT. o

........... ........... ........... ........... ........... ........... . . . . . . . . . . ........... ........... ........... . . . . . . . . . . . ........... . . . . . . . . . . . ..................

......... ............. ............. .............

. . . . . . . . . . . . . ............. ............. ............. .............

.......

MOSR rank of

is a f l m layout em.) Since the standard-cell frame,SPRAME (with a the CN20 setups provided with LASI, pmvides these connections, we could to our basic layout. The result is shown in Fig. 11.23b. ver circuit shown in Fig. 11,24a containing 11 inverters. If all of the in the figure are the same size, the delay from the input to the output is (1 1.28) the circuit shown in Fig. 11.24b with 13 invuters. Again, assuming all same size, the delay from the input t the output is o
~PRL ~PuI=(& + +Rp)(Co*r+10Cd

...................

............. .............

Flpn 11.21 Layout of an n-channel MOSFET measuriag 25 p (width) by 2 W

(Rn+Rp)[(Car+2Ch) +(Car +5Ch)l= (Rn +Rp)[2Cwr + 7 C d (11.29)

8 delay than the circuit with

cell. The "trick" when placing the NAA25X2 cells is to overlap

11 inverters. Often, distributing the signal into U can reduce the pmpagation delay. At this point we can ask the question, ILe the Ent inverter in the circuits of Fig. 11.24 really large so that it has tances for driving the ten invertem quickly?" The answer is simply the size of an inverter, we also increase its input capacitance. In e ust idral voltage sources to drive the first gate in our circuit. In is driven fmm another gate somewhere on the chip. Increasing propagation delay-time of the gate driving this inverter.

CMOS -

J U U L L i C

Figure 1 . 3 (3Layout of 12

using a

224

P r II CMOS Digital at

11 The Invmer

225

k N-Channtrl Only Output D r k m

,,MI M 4 to turn on pulling the & p u t to and b a l amolihlde is VDD.
Plgmc 11.25 hiving an RC aansmisaian line.

VDD-

put drivers sic "NMOS mdM3are the h~rffer =.... -V,,,,,, assuming the inp~. It

11.5 Other Inverter Configurations

Three other inverter conf1gurati0118are shown in Fig. 1126. 1 . 6 is an NMOS-only invntcr, useful in avoiding latch 12a Fig. 11.26b and c use a p-channel load, which is, in with a large number of inputs (more on this in se1ection of the MOSFET sizes follows the 4 to 1 of the load is made four times larger than the resistance of MI. will never reach 0 V for these inverters, and thus basic CMOS i n v e of Fig. 1 11 Also. DC power will be .. logic level is a low since a drain cumnt will fl high level o the invntcr of Fig. 1 . 6 Will reach f 12c that the power dissipation of the invextern s CMOS inverter. However, since the input capacitance basic CMOS inverter and the output voltage swing is reduced, the greatest power dissipation is determined by rhe opcratiag fresuewy. frequencies, the basic CMOS inverter dissipates the most pow=.Fimm 11.27 NMOS aumx buffer.
- .--- -. -- -.P DC voltage of nominally VDD + 2 V . This allows the out~ut sienal to reach
"" . .. -a

--

--" -.

- out

(*)

@)

Plgure 11.26 Other inverter c a n f i ~ ~ .

I=

FbPre 11.28

Alternative output buffer.

VDD

*
S
Figure 11.29 Circuits and lc@c symbol f the the-state inwter. a

11.5.3 The Bootstrapped NMOS Inverter Consider the modified version of the NMOS invatw of fig. 1126 shown This inverter configuration is called the bootsttapp~d NMOS inverter. It the output voltage must swing up to VDD. To understand the operation, the case when input to the inverter is a logic high. 'Ihe MOSFET M1 output is pulled down to appmximately

W o n nsults are shown in fig. 11.32. Notice how the output doesn't go ay to ground ot VDD. We can decrease the size (WIL) M2 (increase of

part n CMOS Digital 9

229

R. L. Geiger, P. E. Allen and N. R. Strader, VLSI-Desrgn TechniquesforAnalog and Digital Circuits, McGraw-HiU Publishing Co.. 1990. ISBN
N. H E. Weste. and K. Eshraghian, Principles o CMOS VLSI Design, f Addison- Wesley, 2nd ed,1993. ISBN 0-201-533766. CN20 process for the followingproblems unless otherwise stated.

eat Ex. 11.6 for MOSFETs with W = 10 pn and a load capacitance of 1pF. nimum-size inverters. out the standard-cell frame of Fig. 11.16. Explain how the added implants However, since this capacitor is charged through M3, t h ~ charging time will cause the maximum practical operating frequency to decrease.

m an inverter with size of 1U)IM. Ihe t,,

sign and simulate the operation of a buffer to drive a 50 pF capacitive load + t,, should be less than 10 ns.
t Ex. 11.9, using a minimum delay of 20 ns, where the first inverter in the

is minimum size, that is, 312 @channel) and 3/2 (n-channel). ign and simulate the &lay of a minimum-size inverter driving a 1 mm poly terminated with a 1pF capacitor. out an inverter with a size of 4501150 using the standard-cell frame of C . h ate the operation and explain the results for the NMOS super buffer shown

Ex. 11.10 if M4's size is inmmed to 20/20.

Ex. 11.5 using minimum-size (0.910.6) MOSFBTs in the CMOS14TB

h. using minimum-size MOSFETs in CMOS14TB. 11.6

h the cross-sectional views, at the positions indicated, for the layout shown

Chapter

Logic Gates
er we discuss the DC characteristics, dynamic behavior, and layout of logic gates. Static logic means that the output of the gate is always a tion of thc inputs and always available on the outputs of the gate regardless e begin with the NAND and NOR gates.

BC Characteristics of the NAND and NOR Gates

ic input NAND and NOR gates are shown in Rg. 12.1. Before we get into on, notice that each input into the gate is connected to both a p- and an transistor similar to the inverter of the last chapter. We will make use of the :h. 11 to exvlain the operation of these gates. .

Characteristics o the NAND Gate l

D gate of Fig. 12.1 requires both inputs to be high before the output will

. Let's begin our analysis by determining the voltage transfer curve of a gate
.

MOSFETs that have. W = W,, L = L ,and n-channel MOSFETs with W , If both inputs of the gate are tied together, the gate behaves l i e an

'determine the gate switching point voltage, V ,we must remember that two , in parallel behave like a single MOSFET with a width equal t the sum of o widths. For the two parallel pchannel MOSFETs in Kg. 12.1, we can

w3+w,=2wp

(12.1)

ng that all p-channel transistors are of the same size. The eters can also be combined into the transconductance parameter

83+84=2pp

(12.2)

part n CMOS DigitJ

Transeonductancc ratio of NAND gate =

233

B. -

4 8 ~

(12.5)

switching point voltage, with the help of 4.(11.4). of the two-input NAND gate is

g m d for an winput NAND gate (pee Rg.12.2). we get

it should be remembered that we have neglected the body effect (an increase in hold voltage with increasing V A . Voltage transfer curves using one input, othas tied t VDD, will give slightly diffacnt results becauseof this effect. o

NAND and NOR gate drade md losic rymhok.

FLgnre 123 Schematic o an n-input NAND gate. f

hand calculations and compare to a SPICE simulation for a using minimum-site devices.

The switching point voltage is determined by calculating the transcondu ratio of the gate, or

and then using Eq.(12.7).

= VSP

0.572 (0.83)+ (5 - 0.92) = 2.9 1.572

The SPICE simulation results are shown in Fig. 12.3. The simulatio Vspof approximately 3.1 V. W

Yin
1 1
8

Figure 12.4 Schematic of an n-input NOR gate.

switching point voltage of a three-input NOR gate made from MOSFETs to that of the three-input NAND gate of Ex. 12.1. which gate is closer to ideal, that is, V = VDDl2. , the minimum-size three-input NOR gate is 1.35 V, while the Vspof -size three-input NAND gate was calculated to be 2.9 V. For an = 2.5 V, so that the NAND gate is closer to ideal than the NOR ses because the transconductance (actually the mobility) of the larger than that of the p-channel. In CMOS digital design, the is used most often. This is due partly to the DC characteristics, ns, and the dynamic characteristics. We will also see shortly has better transient characteristics than the NOR gate. W

.O

0.5

1.0

1.S

2.0

2.5

3.0

3.8

4.0

ug

Pllpvc 123 Voltage trans& charoctaistiics of the tberrpat

12.18 D C C h a r a c t s r l ~ d t h . N O R ~

ofthe NOR and NAND Gates

1 three-input minimum-size NOR

and NAND gates is shown in Fig. 12.5 I1 frame. MOSFETs in series, for example, the n-channel ate are laid out using a single-drain and a single-source n the gate poly is shared between two devices. This has arasitic drainlsource implant capacitances. MOSFETs in n-channel MOSFETs in the NOR gate, can share a drain area inputs and outputs of the gates are on poly.

Static Logic Gates

237

mn i this equation represents fht intrinsic swirchtng time of the sdm n r O F T ,while the rcolld tam teprrscnts R de&y eard by R* lSBs e C For the case wbm N = I, ttds limply nbcato a$-. Wt an external , ~h stance, the high to low &ray-time becomes
t~rn=N.R..(++Cw +0.35.R.Ch(N-1)2 (1213)

m1 MOSFETs in serieb, a smlranalysis vields e iia

238

part n ~

O Digital S

itance is much greater than the output capacitance of the gate,the low to high n time can be estimated by
?~LH'

RP cld -.

(12.16)

In

to low propagation time. using Eq. (12.13). is given by

is much larga than the output capacitance of the gate

e intrinsic propagation delays, t , + t , of a thre~input NAND gate h minimum-site lransistors. Estimate and simulate the delay when g is driving a load capacitance of 100 f. Assume that inputs are tied P input NAND gate, the thne p-channel MOSFPTs in parallel are the output high. Since they are minimum-size

Rp=24LnaodCow=4.8fF a low-to-high propagation time. using Eq. (12.15). with C, = 0, of

Flpm 12.7 Serb d

m of MOSPEl's and equivalmt digital

Thtse quations are approximatim for the propagation delays giving within a factor of hvo of the mtasunmcnts.

123.1 NAND Obtr

Consider the n-input NAND gate of Rg. 12.8 driving a capacitive low-&hi& propagation time, usin$ Eq.(12.10), is
of 100 fP, the propagation delays become, t,, = 928 ps and t,,, = PICE simulation results are shown in Fig. 12.9 followed by the Helping wt convergmce. the .OFTIONS statement was used, ih at 0.1 ns instead of the UlllCaliStic conditions of 1 ps.

where. h e C represents the capacitaace external to , CM rYmsented t e capacitance exUmal to the @ h

240

m n CMOS Dgtl iia

&lay equations derived in Ibis section are useful in understanding the on the nutnba of M O S m s used in a NAND gate for high-speed d d g a
60
50

10 $0

20
10
00

N Ra. C w (12.19) when the output of the NAND gate changes from a low to a high is nt then the high-to-low case. Refening to Fig. 12.6, we see that if one s turns on, it can pull the output to VDD independent of the number of in parallel. Under these circumstarres, Eq. (12.16) can be used with N = 1 the low-to-high delay-time, or for a parallel connection of N p-channel
tpm.
I""

-1 0

tm-R..Cw

(12.20)

Flgure 129 Output of the minimum-size NAND gars driving a LOO tP

m T a p L s v e l ~ ~ ~ 1 2 S * * C1

MI
M2
M3 M4 M5 MB v1 V2

501001 5120CMOSNBGhlW.SumPSJdpPWP8Q(U 2 1 4 0 CMOSNB M u w - 3 ~ AD=sBp Ak36p P W UPS-24 41OOCMWBIBuW~ASP9BpPL)Sa4uP~ ~ ~ V W V ~ ~ ~ B L = ~ U W ~ U A D J B P ~ P W C ~ ~ 51VddVddCMOSPBG2uW*ADJBPA&38pmfi 5 1 V d d V d d C M O S P B L b U W 9 u ~ ~ ~ vddo DC5 10 DCO PULSE(O55n .In .In Ion)

$10 Ruther simpliflcDtim of digital models not showing input capacitsna.

I

mnSpioemodeloandmaeromdels"'" MODEL CMOSNB NMOS LEV+VFBPB.T91)20EOl, LVFBc3.6745BEOl,WVF&4.7234aE-02 s e 8 m m i I i x A f w a ~ ~

oaing Eqs. (12.19) and (12.20). the propagation delays for the
R minimum-sizeNAND gate, with only m e input switching driving a itancc. Compare your results to SPICE.

delay-times arc given by

~PHL

= 3.8k 1 0 W 2.4ns

tm = 24k .lOOffi 2.4 ns

simulption reaults gave tw- tpm 9 2.3 as with one input had used Eqs. 12.19 and 12.20 in Ex. 12.3 where all inputs U tho rpme h e , the calculated t, would have given an

242

Part I1 CMOS Digital

underestimate (but not by much), while the calculated t,, would overestimated the &lay. Also note that since the effective resistance p-channel Is three times greater than that of the n-channel, the seri of three NMOS devices gives approximately the same resistance PMOS. The mult is equal switching times and the reason the N generally prefemd over the NOR gate in CMOS circuit design.
12.3.2 Number of Inputs

mplex CMOS Logic Gates

on of compIex logic functions in CMOS uses thc basic building blocks

As the number of inputs. N,to a static NAND (or NOR) gate increases, shown in F4g. 12.2 (Fig. 12.4) becomes difficult to realize. Consider a NO 100 inputs. This gate requires 100 p-chrnncl MOSFETs in series and a MOSFETs (2N MOSFETs). The delay associated with the series pchanae charging of a load capacitance is too long for most p a c t i d situations.

VDD

Assuming that the maximum V , allowed (the more inputs at VDD th 500 mV and that the n-channels have W = 3 pm and L = 2 pm results and an L of 3 prn for the p-channel. In practice, the length of the p-c increased beyond this size to lower VOL further. The static power dis when the output is high, neglecting leakage currents, is zero. When static power is dissipated due to both a- and p-channels conducting. flows under this condition with the above sizes is 150 pA. Decreasin p-channel lowers power draw at the price of increased tpm.

VDD

FIpre 1 . 2 Logic implementation in CMOS. 21

% 4 !
h ~ g i cimplement the following logic functions: ,
r

Z = ~ + B C and .

Z=A+&+CD

Figure 1 . 1 NOR ccdlguration b e d for a 21

ntrmbm &

Chapter 12 Static Logic Gates

/

245

the The implementation of the first function is shown in Fig. 12.13a. Notice that we p-channel configuration is the dual of the n-channel circuit. The function :r is obtain is the complement of the desired function, and therefore an inverte and used to obtain Z. Using an inverter is, in general, undesirable if both true a to complements of the input variables are available. Applying Boolean algebr the logic function, we obtain

The second logic function is given by

Z=A+BC+CD=A+C(B+D)~Z=A+C(E+D)=A.(~+B~)
or

z=;~+Bc*Z=A+BC=A.(E+Q

= _ .

*Z=A.(E+G

the The A01 implementation of the result is shown in Fig. 12.13b. Logically. .13b circuits of Figs. 12.13a and b are equivalent. However, the circuit of Fig. 12mce is simpler and thus more desirable. Note that to reduce the output capacit;
VDD

1
I

z=~.(?+E@
The logic implementation is given in Fig. 12.14.

VDD

Fimre 12.14 Second logic gate of Ex. 12.5.

Example 12.6

UcV logic, implement an exclusive OR gate (XOR). A01

lopic symbol and truth table for an XOR gate are shown in Fig, 12.15
Frnrn the truth table. the l p i c function for the XOR gate is given by

Figure 12.13 First lo& gate of Ex. 12.5.

Cllnpter 12 Static Logic Gates

247

and finally i ; = z

(12.23)

The CMOS A 0 1 implementation of an XOR gate is shown in Fig. 12.16.

carry-in

.;"j.
+ I.

Cany-out

Full adder

0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 I 1 1

1 1 0 1 0 0 1

0 0 I 0 I 1 1

sn

Sumat

Figure 12.17 Full adder Figure 12.15 Exclusive OR pate

The logic expression for the sum can be rewritten as a sum of products

s. = A.B,c.
nr since

+Z.B,?,

+A.B,F.+A,B.c,

VDD

the sum of products can be rewritten as

The A01 implementation of the full adder is shown in Fig. 12.18.

12.4.1 C a s c o d e Voltage Switch Logic

Figure 12.16 CMOS A 0 1 XOR gatC.

Cxcode voltage switch logic (CVSL) or differential cascode voltage switch logic IDVSL) is a differential output logic that uses positive feedback to speed up the '";itching times (in some cases). Figure 12.19 shows the basic idea. A gate CrW-connected load is used instead of using p-channel switches, as in the A01 logic, to Pllll the output high. Consider the implementation of z = ~ + B c . (This logic function "as "plemented in A 0 1 in Fig. 12.13.) N-channel MOSFETs are used to implement Z as shown in Fig. 12.20. Figure 12.21a shows the implementation of a two-input X o R m gate using CSVL, while Fig. 12.21b shows a CSVL three-input ~ ~ ~ X O R I Xgate~useful in adder design. ~ ~ Differentla! Split-Level Loqic

Example 12.7 Desipn aCMOS full adder using CMOS A01 logic. The lopic symbol and truth table for a full adder circuit are shown in Fig. 1 2 ' 7 ' The lopic functions for the sum and carry outputs can he written as

split-level logic (DSL logic) is a scheme wherein the load is used to reduce swing and thus lower gate delays (at the cost of smaller noise margins). 'llc hasic idea is shown in Fig. 12.22. The reference voltage V,,,is set to VDD12 + V , , T h l r ha< the effect of limiting the output voltage swing to a maximum of VDD and a of VDDI2. The main drawback of this logic implementation is the increased P[I!v,-~ djcalpation resulting from the continuous power draw through the output leg at a . nf L'DD12. The output leg at VDD draws no DC power.
''"'pllt

'

248

part 11 CMOS Digital Circuits

Chapter 12 Static Logic Gates

249

VDD

0 Q
Output Inputs

block

&
block

Output

Figure 12.19 CSVL block diagram.

*
VDD

Figure 12.20 CSVL logic gate.

Figure 12.18 A01 implementation of a full adder

250

PIW n CMOS Digital

C 12 Static Logic Gats

25 1

FWn?1255 Tri-amte buffer.

252

1 Part 1 CMOS Digital Circuits

Chapter 12 Static Logic Gates

/

253

12.4.3 Tri-State Outputs

A final example of a static logic gate, a tri-state buffer, is shown in Fig. 12.23. When

PROBLEMS
LTSC the CN20 process unless otherwise specified.

the Enable input is high, the NAND and NOR gates invert and pass A (VDD or ground) to the gates of MI and M2. Under these circumstances, M1 and M2 behave as an inverter. The combination of M1 and M2 with the inversion NANDMOR gate causes the output to he the same polarity as A. When Enable is low, the gate of MI is held at ground and the gate of M2 is held at VDD. This turns both M1 and M2 off. Under these circumstances, the output is said to be in the high-impedance or Hi-Z state. This circuit is preferable to the inverter circuits of Fig. 11.29 because only one switch is in series with the output to VDD or ground. An inverting buffer configuration is shown in Fig. 12.24.
VDD

:sign, lay out, and simulate the operation of a CMOS AND gate with a V, of proximately 1.5 V. Use the standard-cell frame discussed in Ch. 4 for the 'Out. 12.2 De:sign and simulate the operation of a CMOS A01 half adder circuit using static logic gates. peat Ex. 12.3 for a three-input NOR gate. peat Ex. 12.4 for a three-input NOR gate. :tch the schematic of an OR gate with 20 inputs. Comment on your design.
Skc:tch the schematic of a static logic gate that implements ( A + B . ? ] . I. Est imate the worst-case delay through the gate when driving a 50 fF load caplacitance.

12.6

~ i g n simulate the operation of a CSVL OR gate made with minimum-size and lices.

Enable 1

h g i c symbol

Figure 12.24 Tri-state inverting buffer.

REFERENCES
[I]
[21

M. I Elmasry, Digital MOS Integrated Circuits 11, IEEE Press, 19920-87942-275-0, IEEE order number: PC0269-1.
Publishers, 1992.

rSBN

1. P. Uyemura, Circuit Design for Digital CMOS V a l , Kluw~rAcadenuC

M
Qhnii P M O S

[3]

ni~italCircuit Technology, Prentice-Hall, I

Design a tri-state buffer that has propagation delays under 20 ns 9 1 pF load. Assume that the maximum input capacitance of the buffer Sketch the schematic of a threeinput XOR gate implemented in A01

Chapter

What logic function dm the circuit of Fig. P12.10 implement?

Calculate the switching point voltage of the gate shown in Fig. ~d

e TG and Flip-Flops
ssion gate ( C ) is used in digital CMOS circuit design to pass or not pass a T3 schematic and logic symbol of the transmission gate (TG) shown in Fig. are up of the parallel connection of a p and an nchannel MOSFET. when S (for select) is high we observe that the transmission gate input to the output. The resistance between the input and the estimated as RJIR, . We begin this chapter with a description of the nass transistor.

logic function does this circuit implement? Estimate the minimum and maximum output voltages for tl P12.11.

.d

Pass Transistor
single nchannel MOSFET shown in Fig. 13.2a. Assume that the voltage itor (the output of the pass transistor) is initially 5 V. When the f the MOSFET is taken to VDD,the MOSFET turns on. In this assume that the drain of the MOSFET is connected to the load at the source (the input of the pass transistor) is connected to ground, the drain and source are interchangeable. The delay-time of the is simply

The circuit shown in Fig. P12.13 is an edge-triggered one-shot 4 output pulse, with width td , whenever the input makes a l
inverters for delay elements, design and simulate the opetr3 whose output pulse width is 10 ns. Comment on the resulting4 of the input pulse is less than td.

13.1 The transmission gate.

256

Figure 133 An n-channel pass transistor showing transmission of 0 V and

Now consider Fig. 13.2b where the capacitor is initially at 0 V. In this case, connected to VDD and the source is connected to the load capacitance. substrate, assumed at VSS = ground, is not at the same potential as the body effect present causing the threshold voltage to increase. What b q MOSFET is raised to VDD, the load capacitor charges to VDD - V , wbm Appendix A, is in the neighborhood of 1.5 V. llIaef~re, low-to-hlO$! the can be estimated by . '>, tpm = RnClwd a high voltage of VDD - V , for ib
SET. The In this derivation, we have neglected the parasitic capacitances of the following example illustrates the switching behavior of the n-channel pass tF(mistor.

'
7aSS

&tima% e and simulate the delay through mini transistors using the test setups of Fig. 13.2 driving a We know that for the minimum size (W= 3 pm and L = 2 p) effective resistance is 8 kR. Therefore, the propagation delays t , ps, remembering that the maximum high voltage is VDD approximately 3.5 V. The simulation results are shown in Fig. 13.3. A similar analysis of the p-channel MOSFET used as a pass
~ P H L Rp c w = ~ d

me1

800 or

tor turning on must discharge the charge stored on the output MOSFET through its own effective resistance.

and
~ P U I=lip

passes logic lows well and the pchannel passes logic highs well, lementary MOSFETs in parallel, as was shown in Fig. 13.1, es both logic levels well. lXe CMOS TO requires two control 13.4). llIe propagation delay-times of the CMOS TG are

- C w for alow
t of the TG is the input

The p-channeI pass transistor can pass a low results in a minimum low voltage transistor can pass a logic low without maximum high voltage of VDD - V,. One advan* is that it can be laid out, in an a-well process, with the eliminating body effect.

of the MOSFl3Ts

ng. Using a voltage source in

258

Part I1 CMOS Digital C q

1

SPICE for the select lines, which can supply infinite current to charge the capacitance of the TG,gives the designer a false sense that the delay through the limited by R, and R, . Often, when simulating logic of any kind, the SPICE-g control signals are sent through a chain of inverters so that the control sign;, closely match what will actually control the logic on die.

Figure 1 . The transmission gate w t control signals shown. 34 ih

13.2.2 Series Connection of Transmission Gates Consider the series connection of CMOS transmission gates shown in Fig. 1 equivalent digital model is also depicted in this figure. The output ca individual MOSFETs is not shown in this figure and will be neglected analysis. The delay through the series connection can be estimated by
t p

the number of inputs (outputs) to the MUX (DEMUX) and m is the number oe lines. A 4 to 1 MUXiDEMUX I8 shown in Fig. 13.10. N t Uu the MUX is nal; that is, it can be used as a MUX a a DEMUX. Thc logic quarjon the operation of the MUX is given by

= ~ p = N. (Rn IIRp)(Cload) 0.35 . (Rn IIRp)(Ctm C@)(N) t ~ ~ +

The first term in this equation is simply the sum of the TG effective resis the second tern in the equation describes the RC transmission line effects.

A1

A2

A3

I.PU~

t +

A A A

7 - 1 7 A3 A1 A2

...
S
Figure 13.8 Path selector.

Figure 13.7 Series connection of transmission gates with digital model.

13.3 Applications of the Transmission Gate

In this section, we present some of the applications of the n? [I. 21.
Path Selector The circuit shown in Fig. 13.8 is a two-input path selector. Logically, tht circuit can be written as
Out

Z=AS+BS
When the selector signal S is high. A is passed to the output while a low to the output. This same idea can be used to implement multiplexetsl$j (MUXIDEMUX). Consider the block diagrams of a MUX and DEMUX 8 13.9. The number of control lines is related to the number of input lines &
Figwe W.9 BImk diagram o MUXlDBMUX, f

Figure 13.12 TG-based OR gate.

Truth tabk

~ R Q Z ~
0 0 1 10 1 0 1 0 1 l Q

1 0 1 G

Truth table

S R O O Q 10 1 01 0 1 1 0

Q ~ G 0 1 0

268

Part I1 CMOS Digitakii

FF,consider the data or D FF shown in Fig. 13.18 with associated logic symbol. the clock signal is high, the D input can pass directly to the SR FF. If D i is CLK is high, the output, Q, a 1, while if D is low the output is a low.
any time while the CLK input is high, the output will follow. When goes low, the current logic level of D is latched into the SR FF. an edge-sensitive FF because the output changes at other times time.

Edge-Triggered Flip-Flops
The JK master-slave F , F shown in Fig. 13.19, is an example of an edge-a31 F When the CLK signal goes high, the master JK F is enabled. Since ms' cannot change states when CLK is high. the clock pulse width does not have than the propagation delay of the FF. When CLK goes low, the mu* transferred to the slave. If both J and K are low, the output of the mum unchanged, and therefon so does the output of the slave. If J = 1 and K= 0 CLK pulse goes low, the master output, Q,goes high. When the CLK gool high output of the master is transfemd to the slave. The master-slave JK A just like the JK FF of the previous section except for the fact that the di available until CLK goes low and then is no restriction on the pulse width (ic., the FF is falling edge triggered). Adding reset or set capability to the accomplished by adding logic gates between the NAND and the SR FF of The logic gates simply enswe that the SR FF are placed into a certain I application of a reset or set signal.

implementation of the positive edge-triggered D FF is shown in Fig. 13.20a. made using NAND gates. When the CLK input is low, the outputs of the are both high, keeping the SR FF in the "no change mode." When CLK ,the logic value on the D input of the FF is transferred to the S input and the transferred to the R input of the SR FF. The CLK input of the NAND three inverter delays after CLK goes high. This forces both R and S the flip-flop in the no change mode. The only time that CLK and CLK the condition required to transfer D to the input of the FF, is the time K going high and CLK going low. This time is determined by the delay of the inverters. In practice a single inverter, in place of the three, ide a sufficient delay to allow the inputs of the SR FF to fully charge to D ,there are minimum rise- and falltimes requirements for the clock.

implementation of the positive edge-triggered D FF using transmission in Fig. 13.20b. When the CLK input is low, the logic value at D is A and is on node B. Transmission gates T2 and T are off. The 3 C is available on the output of the FF and is the result of the previous nsition of the CLK input pulse. When CLK goes high, T1 and T4 turn and T3 turn on and the datum on node is C is transferred, with the inversion to the outputs. A D FF with set and clear inputs is shown in Fig.

a st be set up or present on the D input of the FF (see Fig. 13.20~) certain apply the clock signal. This time is defined as the setup time of the FF. the origin of this time, consider the time it takes the signal at D to

important comment regarding the clock input of a FF is in order. If slow, the FF will not function properly. There will not be an the sets of transmission gates turning on and off. The result

13 The T and Flip-Flops G

271

Figure 1331 Illustrating D FF setup time.

is to buffer the clock input through several inverters. This has the effect of up the leading and trailing edges of a slow input pulse and presenting a lower ance on the clock input to whatever is driving the FF. The main is the increase in delay times, tpmand tpw (defined by clock to output), of nerd, the FFs of Fig 13.20b and c should not be laid out without buffering imum pulse width of the clock, set, or clear inputs is labeled t, . The is determined by the delay through (refemng to Fig. 13.20) two NAND The last timing definition we will consider here is the recovery time, time between removing the set or clear inputs and a valid clock input. This

D inputs eitha a high w bw

Figure 13.22 Illustrating D FF hold time.

using inverters and TGs is shown in Fig. 13.23. The crosstoupled s o ~referzed to as a latch and is the basis for the static s sad furthcr in Ch. 17. To understand the operation of this case when CLK is low. The TGs are off, and the outputs do not CLK is high, provided the inverters are sized input is connected to Q and the 5 input is back low, the value of D is remembered and d be made regarding this flip-flop: (1) the outputs CLK is high, that is, it is not an edge-triggered inputs must supply a currtnt during switching.

Part I1 CMOS Digital

-Vefi, using SPICE, that the circuit of Fig. 13.13 operates as an XOR gate. Simulate the operation of an SR l made with NAND gates using T minimum-size MOSFETs. Show all four logic transitions possible for the FF. Simulate the operation of the clocked D FP of Rg. 13.23b using minimum-size MOSFJ~TS.Comment on.any glitches you encounter. Show the I clocking in T a logic 1 and 0. What are the setup and hold times for your design? Design and simulate the operation of the FF shown in Fig. P13.8.

CLK

/ \

Figure 1 . 3 Clocktd D flip-flop using the basic latch and TCis. 32

The input DC connected to each TG. In effective digital resistances of the invcrters shod TG resistance and the driver mistance. - - -of whatever gate is driving the TG.)In be lame. The length of the &vim used in the inverters can minimum length to reduce the input CUTTCU~.

REFERENCES
[I]
1 P. Uyemura, Circuit Design for Digiml CMOS V . Publishers, 1992.

. Klu

[2] [3]

M. I. Elmasry, Digital MOS Integrated C i ~ u i t 11, IEEE Pnss, s 0-87942-275-0, IEEE order number: PC0269-1.
M. Shoji, CMOS Digital Circuit Technology, Rentice-Hall, 1 0-13-138850-9.

shown in Fig. P13.8 has several practical problems. including not a purely capacitive load at the D-input and large layout size. The FF .9 is a different implementation of an inverter-based latch which does urely capacitive load to the D-input and a (possibly) smaller layout ate the operation of this F using the device sizes shown. F

PROBLEMS
Unless otherwise stated, use the CNU) process.

1. 31

Verify the simulation nsults shown in Fig. 13.3. If we i n-channel pass transistor, what happens to the delay-times transistor is driven from some other logic on the chip. i lrse capacitance seen by this logic when w?ce s the width of

133 Estimate and simulate the &lay through 10 TG8 (a connected to a 100 fF load capacitance. 1 . Sketch the schematic of an 8 to 1 DEMUX usi 34 Estimate the delay through the DEMUX when load capacitance.

fi.13.1 using minimum-size (0.910.6) MOSFBh using the CMOS 14113

.13.2 using the CMOS14TB process.

274

Part 1 CMOS Digital 1

13-12 Estimate and simulate the delay through 1 TOI (assume m 0 i connected to a 100 f load capacitance using the CMOS14TB process. F 1 . 3 Using a SPICE DC sweep, plot the output voltage against the input vq(l 31 the circuit of Fig. P13.13 with the input varying from 0 to 5 V and --. . V to 0 cornmeit on the difference in the plots. .

Chapter

In

Out

or clocked logic gates are used to decreape complexity, increase speed, and
wer dissipation. The basic idea behind dynamic logic is to use the capacitive MOSFET to store a charge and thus remember a logic level for use later. tart looking into the design of dynamic logic gates, let's discuss leakage the design of clock circuits.

pdamentals of Dynamk Logic

*

-channel pass transistor shown in Fig. 1 . driving an inverter. If we 41 e pass transistor high, the logic level on the input, point A, will be of the inverter, point B. If this logic level is a "0," the input of the le a logic " 1 " will force the input of the inverter to goes low, the pass transistor shuts off and the input ic level. In other words, when the pass transistor Input capacitance of the inverter is charged to VDD - V , or ground, , pass transistor. As long as this charge is present, the logic value is What we are concerned with at this point is the leakage mechanisms I can leak the stored charge off the node. A node, such as the one labeled is called a dynamic node or a storage node. Note that this node is a node and is easily susceptible to noise (see Ex. 3 4 . .)

ample of a dynamic circuit and associated stotage capacitance.

fk.
I

.,*.I

276

14.1.1 Charge Leakap

Consider the expanded view of the charge storage node shown in Fig. 14.2. the only leakage path on this node is through the MOSmTs drain (or drain and source are interchangeable) n+ Ipsubstratc diode. I we consi& f the drain of the MOSFET, the current is given by ls(e-VdnVr 1) ID = 11-e

discharge rate of the 50 f capacitor shown below. Assume that the F n and source areas measure 6 pm by 6 pn.

where V,,is the voltage on the storage node to ground, assuming the ground potential. From the BSIM model parameters, the scale current is. , Is = A D . JS In order to simplify hand calculations we will assume that the leakage c to the scale current, or I m r = I s = A D . JS The rate at which the storage node discharges is given by dV -=-= I*akyld AD-JS dt Cnok Cn~d. The node capacitance is the sum of the input capasitarm of the inve-, to ground of the metal m p l y line connecting the inverter to the p l s capacitance of the drain implant to substrate (the depletion capaciuasc). applications, we assume that C d , = Ch of the inverter

trate
hv

BSIM model parameters, JS = lo-" Nm2;thcrcfm, the leakage current

Ir*=AD*JS=36p 104=360~ 1OW2'A

harge rate is estimated by

slow discharge rate. In practice, the MOSPET can have a nonzero oltage causing a subthreshold current to flow, incmshq the #rate. Also, the value of cumnt denslty given in the BSlM modal in A and used above, that is, JS = 10d Nma, is the SPICE default value. that the leakage current was not measured whem generating the indicating another possible source of error.
ng Dynamlc Clrculta

mely small lealcege currents involved, simulating dynamic circuits t, when SPICE simulates any circuit, it puts a resistor with a ven by the parameter GMIN across every pn junction and to source. The default value of GMIN is mhos or a 1M resistor. node at a potential of 5 V has a leakage current, due to GMIN,of 5 the node voltage starts to decrease, the leakage current decmscs as current calculated in Ex. 14.1 was 360 x 1 P ' A, or over a million the 5 pA flowing through the &fault value of GMIN. The value of sing the .OPTIONS command, at the cost of a longer or more time, to a smaller value, say 10-Is. t accuracy), RELTOL (relative accuracy). or VNTOL parameters can limit the accuracy of the simulation and t value of the current accuracy, ABSTOL, is 1 PA. Since

to determine if convergence has been reached WOUM nstd to be t~ get sma

278

Part I1 CMOS Digital Cil

Chapter 14 Dynamic Logic Gates

4

279

results closer to hand calculations. In addition, CHGTOL, the capacitance cl tolerance that defaults at 10 fC (1 V on a 10 fFcapacitor), would need reduction. In practice, we use the default values of SPICE, which give a pessir estimate for the discharge time of storage nodes in dynamic circuits. The le; current, for VDD = 5 V , is given by

14.1.3 Nonoverlapping Clock Generation

I I , ~ ~ , = 5 pA = VDD . GMIN ,,
and

(1

dV - 5 PA - VDD . GMIN dt Cno& Cno&

(1,

For C,, = 50 fF, it takes approximately 10 ms for the voltage on the charge st()rage node to fall 1 V, If 1 V is the most we will allow the node to fall before we : P P ~ Y ~ another clock signal, then the minimum clock frequency is 100 Hz. The following example illustrates the dominance of GMM in the simulation of a dynamic circuit.

consider the string of pass transistorshverters shown in Fig. 14.4. This circuit is a dynamic shift register. When @, goes high, the first and third stages of the ,@er are enabled. Data are passed from the input to point A0 and from point A1 to ,A>. If Q, is low while $, is high, the data cannot pass from A0 to A1 and from A2 to , p ~ .If Q,goes low and @ goes high, data are passed from A0 to A1 and from A2 to A3. , ~f both 4, and are high at the same time, the input of the shift register and the output are connected together, which is not desirable in a shift register application. The p q o s e of the inverter between pass transistors is to restore logic levels, since the n-channel pass transistor passes a high with a threshold voltage drop. Two inverters would be used to eliminate the logic inversion between stages. The clocks used in this dynamic circuit must be nonoverlapping, or logically

@,

Example 14.2 Simulate the circuit of Ex. 14.1. Estimate the discharge rate of the capacitor due to the default value of GMIN.
The discharge rate from Eq. (14.7) is 1 V per 10 ms for a GMIN of 10-12mhos. The SPICE simulation results are shown in Fig. 14.3. Notice how the leakage drain current is jagged. This is the result of the numerical iteration scheme used by SPICE. The simulation currents will vary by an amount less than ABSTOL, or 1 PA. In most simulations, we do not see the small current variations.

There should be a period of dead time between transitions of the clock signals, labeled A in Fig. 14.4. The rise- and falltimes of the clock signals should not occur at the same time. Since the design and layout of the dynamic shift register is straightforward let's concentrate on the generation of clock signals, @, and @,. Note that a simple logic inversion will not generate nonoverlapping clock signals.

time

..

Time

F i ~ u r14.4 Dynamic shift register with associated nonoverlapping clock signals. e

Figure 14.3 Simulation results showing discharge of a capacitor

MOS TO In Dynamk Clreulta

e IeaLage of charge off of or onto the input capacitance of the i n v e in Fig. be attributed to the drain-well diode of the p-chaanel MOSFET and the the n-chmwl MOSFET wed in the TO. If these leakage

nding on the size of the drain anas and the leaLage cmnts.

used in the clocking scheme. Additional MOSFETs can be used for helping the gate appear more static in operation.

nehanad drainhubs d i o d s 4

Subsmtc cauKcaon
piw
1 4 CMOS TO used in dynlmic losic ~

Pr 11 CMOS Digital at
output is in the Hi-Z state, or in other words a high-impedance node signal feedthrough. The layout of the CMOS gate is thus more cri gate. Because of this node, running signal lines above this nod definite problem. The output of the gate is not static. When the latch is enabl is high, the capacitance on the o u G node is charged. The same leakage me present in the CMOS TG latch are present here. This limits the minim1 frequency to about 100 Hz. Implementing a shift register requires nonov clocks for adjacent stages. The total number of clock signals needed for a C% register is four. The nonoverlapping clocks and 42and their complements.

ad
3

4 Dynamic Logic Gates

VDD
Precharge

283

+A1 -A2+A3 A4

@,

PE Logic
This section discusses precharge-evaluate logic, or PE logic. Consider th NAND gate shown in Fig. 14.8. The operation of this gate relies on a input. When 4, is low, the output node capacitance is charged to VDD During the evaluate phase, 0, is high. MI is on, and if A , Al, and A2 O output is pulled low. The logic output is available only when 4, is high. logic one when 4, is low. One disadvantage of PE logic is that the gate lo available part of the time and not all of the time as in the static gates. Several important characteristics of the PE gate should be pointed input capacitance of the PE gate is less than that of the static gate. connected to a single MOSFET where the static gate inputs are tied to Potentially the PE gate is then faster and dissipates less power.

4'1

Ngore 14.9 A complex PE gate.

The size of the MOSFETs used in a PE gate does not need d o i n g for a1 switching point voltage. The absence of complementary devices and the the output is pulled hiah during each half cycle makes the gate V , ess. ~owevcr, m y need to size the devices to attain a certain speed f o f i we a d capacitance. If the sizes of all NMOS transistors used in Fig. 14.8 are equal, t,,, is approximately 3R& and the t,, is R,C,, where C,, is the total n the output node. ?his may include the interconnecting capacitance and acitance of the next stage. Hae we have neglected both the transmission a series connection of MOSFETs and the intrinsic switching speeds. gic function, F = AO+ A1 A2 +A3 A4, implemented in PE logic is

m.

a& of PE gates shown in Fig. 14.10. During the precharge phase of output of each PE gate is a logic high. T i high-level output is %s e input of the next PE gate, Suppose the logic out of the first PE gate uate phase is a low. This output will turn off any MOSFETs in the However, during the p h a r g e phase, those same MOSFETs in the -te will be turned on. The delay between the clock pulse going high and the d the first gate will cause the second gates output to glitch or show an autput. If we can hold the output voltage of fhe PE gate low, instead of this racecondition. Upon adding an inverter to the PE gate (Fig. glitch-ftse operation is met. The PE gate with the addition of logic. The name Domino coxlles fnnn the fact that a gate gates cannot change output states until the previous gate in output of the gates occurs similar to a series of falling in the Domino gate has the added advantage that it can be loads.

ter 14 Dynamic Logic Gates

285

One problem does exist with this scheme, however, referring to Fig. 14.11, note during the precharge phase, node A is charged to VDD. If the NMOS logic results logic high on node A during the evaluate phase, then that node is at a high ce with no direct path to VDD or ground. The result is charge leakage off of A when the PE output is a logic high. The circuit of Fig. 14.12 eliminates this em. A "keeper" p-channel MOSFET is added to help keep node A at VDD when OS logic is off. The WIL of this MOSFET is small, so that it provides enough to compensate for the leakage but not so much that the NMOS logic can't drive

behind implementing a logic function using NP logic is shown in Fig. 14.13.

Figure 14.10 Problems with a cascade ofPE @tee.

,
1

r used in Domino logic, making higher speed operation possible. A circuit easily be implemented in IW logic is the full adder circuit of Fig. 12.18. The ction of the carry circuit is implemented in the first section of the IW logic, PMOS section of the sum circuit is implemented in the PMOS section of the

c adder just described performs one two-bit addition with carry during each e. Adding two-four bit words requires the use of pipelining [4]; see Fig. e bits of the word are delayed, both on the input and output of the adder, so of the sum reach the output of the adder at the same time. Note, however, words can be input to the adder at the beginning of each clock

Figure 14.11 Domino logic gate.

where two numbers are not added continuously can result in longer

14.12 Kce r MOSPET used to hold node A in when FB prts atput is high. at

Figure 14.13 NP logic.

z . A u - * 21

Aca

Part 11 CMOS Digital Circuits

288

14.9

sketch the implementation of an NP logic half adder cell.

Chapter

14-10 Design (sketch the schematic o f ) a full adder circuit using PE logic. -

14.11 Simulate the operation of the circuit designed in Problem 14.10. 14.12 Figure P14.12 shows one bit of a shift register implemented in the so-called ratioless NMOS logic. W e term ratioless results from the fact that the MOSFET sizes do not affect the switching point voltages. Also, this gate can be laid out in a very small area and the outputs can swing down to gmund Discuss and simulate the operation of this circuit. Keep in mind that Q, and b, are nOnoverlapping clock signals. What is the maximum output voltage of this circuit?

VLSI Layout
The past chapters have concentrated on basic logic-gate design and layout. In this chapter we discuss the implementation of logic functions on a chip where the size and or~mization the layouts are of importance. The number of MOSFFTs on a chip, of tiepending on the application, can range from tens (an op-amp) to hundreds of millions (a 2 0 MEG DRAM). Designs where thousands of MOSFETs or more are integrated o n n single die are termed very-large-scale-integration (VLSI) designs.
To help us understand why chip size is important, examine Fig. 15.1. The dark ( k i n d i c a t e a defect that will lead to a chip which doesn't function properly. Figure I(.lr shows a wafer with nine full die. The partial die around the edge of the wafer are \ v s t d Five of the nine die do not contain a defect and thus can be packaged and sold. Next 'conrider a reduction in the die size (Fig. 15.lb). We are assuming each die.

All MOSFETs are minimum size.

Figure P14.12

14.13 Show that the dynamic circuit shown in Fig. P14.13 is an edge-triggered flip-flop 151. Note that a single-phase clock signal is used.

whether discussing the die of Fig. 15.la or b, performs the s m fu ae reduction can be the result of having better layout (resulting in a smaller fabricating the chips in a process with smaller device dimensions (e.g., pm process to a 0.5 pn process). The total number of die lost (see Fig. defects is five; however, the number of good die is significantly larger than die of Fig. 15.la. The yield (number of good didtotal number of die on. increased with smaller die size. The result is more dietwafer av& Another benefit of reducing die size comes from the realization wafer are constant and increasing the number of die on a wafer die.

point, we may ask the question, "How do we determine the size of the blocks in ,2?" The answer to this question leads us into the design and layout of the cells implement each of the logic blocks in Fig. 15.2. cells are layouts of logic elements including gates, flip-flops, and ALU t are available in a cell library for use in the design of a chip. Custom to the design of cells or standard cells using MOSFETs at the lowest level. cell design refers to design using standard cells; that is, the designer comects n standard cells to create a circuit or system. The difference between the design can be illustrated using a printed circuit board-level analogy. A 11 design is analogous to designing with packaged parts. The design is hed by connecting wires between the pins of the packaged parts. Custom analogous to designing the "insides" of the packaged parts themselves. e 15.3 shows an example of an inverter [2]. In addition to keeping the as small as possible, an important consideration, when laying out a standard routing of signals. Keeping this in mind, we can state the following general for standard-cell design: inputs and outputs should be available, at the same relative horizontal ce. on the top and bottom of the cell. ntal runs of metal are used to supply power and ground to the cell, a.k.a. r and ground busses. Also, well and substrate tie downs should be under height of the cells should be a constant, so that when the standard cells are end to end the power and ground busses line up. The width of the cell be as narrow as the layout will allow. However, the absolute width is not t and can be increased as needed. layout should be labeled to indicate power, ground, input, and output ons. Also, an outline of the cell, useful in alignment, should be added to

15.1 Chip Layout

VLSI designs can be implemented using many different tecM gate-arrays, standard-cells, and fullcustom design[l]. Since gatearrays are, in general, used where low volume and fast o required and the chip designer need h o w little t nothing implementation of the CMOS circuits, we will concentrate on fullc, &sign using standard cells.
Regularity

An important consideration when implementing a VLSI chip desi

layout should be an orderly mangement of cells. Toward this designing a chip is drawing up a chip (or section of the chip) flow shows a simple floor plan for an adder data-path. This f l m plan floor plan of an overall chip, which includes output buffers, control

Fun-aMa cells
> II

outpUtlrrtchc8

15.4 illustrates the connection of standard cells to a bus. Note that mlv. vertically, can cross the metall lines, which run horizontally without t. This fact is used to route signals and interconnect standard cells in a Also, in this figure, note how the two inverter standard cells are placed e result is that power and ground are automatically routed to each cell.
.r

'lack

Figme 15.2 Floor plan fa an adder.

'

At many universities, progtammablc-logic-arrays am Digital Logic Design, while design using a herdw~vc field-programmablegate arrays (FPGAs)is discussed in
Design.

m)

les of static standard cells are shown in Fig. 15.5. A double is shown in Fig. 15.5a while NAND, NOR, and transmission gate wn in Figs. 15.5b, c, and d.
.6 shows the layout of a NAND-based SR flip-flop. This layout differs

we have discussed. All layouts discussed so far have metal1 and

IN

OUT

,,

7;.

p+ aubsmtc tie down

! IN WT

GNI

Figure 1. Standardall layout o an inverter. 53 f

Control 6

IN WT

294

Part I1 CMOS Digital

is longer than the adjacent MOSFET. This additional width is of little ce and has little effect on the DC and transient properties of the gate. Figure ws the NOR implementation of an SR flip-flop.

Q ' R

Figure 15.6 SR flip-flop using NAND gates.

contacts adjacent to the gate ply. Also, the gate p l y has been 1 bends. The expanded view of a pchannel MOSFET used in the S R in Fig. 15.7. Keeping in mind that whenever p l y crosses active (n+ o r is formed, we see that the .murceof the MOSFET is connected to contacts, while the p+ implant forms a resistive connection to remainder of the device. The layout size, in this case the width of the

Figure 15.8 SR flip-flop using NOR gates.

blems encountered when designing a chip can be related to distribution und. When power and ground an not distributed properly, noise can one circuit onto the power and ground conductors and injected into padframe shown in Fig. 15.9a power and ground shown. Approximately 600 standard cells are The space between the rows of standard cells is used for the s. A line drawing of a possible power and ground bussing architecture 15.9b. Coasidcr the section of bus shown in Fig. 15.9~. Wire A is while wire B is used for (VDD) returned on B is onductors B and C, which gives conductor. This coupling can be reduced by and C. This reduces the inductive and capacitive Another solution is to increase the capacitance &coupling capacitor (Fig. 15.10) can be used toward

, A 4 - 2

296

Part I1 CMOS Digital

al. The capacitor is placed in the middle of a standard-cell row. Also, the AC Fe drop effects discussed in Ch. 3 are greatly reduced by inclusion of this or.

VDD

GND

Figure 15.10 Decoupling capacitor.

pupling is a problem on signal busses as well. Figure 15.11 shows a simple Used to reduce coupling. The length of a section, where two wires are adjacent, Dd by routing the wire to other locations at varying distances along the bus. The o capacitive coupling between two conductors is directlv related to the length r

P r II CMOS Dig at
298
An Adder Example

15 VLSI Layout the FF is shown in Fig. 15.12b. The layout size and the size of the these examples are larger than what would be used in practice to and viewing the layouts easier. , . e layout of the static adder is shown in Fig. 15.13. This is the on, using near miniplum-size MOSFETs, of the AOI' static adder of Fig. e carry-out and sum-out logic functions are imp1emcnted in this cell.

A another example, let's consider the implementation of a four-bit a s floorplan for this adder was shown in Fig. 15.2.) The first components 1 designed are the input and output latches. Figure 15.12. shows the schem flip-flop used in the latches. This FF is the level-triggered type dilauv chapter. When CLK is high, the output, Q changes states with the i q . inverter, 14, is used m provide positive feedback and i sized with a small s that 11 does not need m supply a large aamunt of DC current to force the lal

I
I

Figure 1 . 3 Layout of the static adda of Fig. 12.18. 51

lete layout of the adder is shown in Fig. 15.14. The two four-bit d Word-B, are input to the adder on the input bus. These data are input latch when CLK is high, while the results of the addition are output latch when CLK is low. The inverter standard cell of Fig. 15.3 end of the output latches and is used to generate CLK for use in the The inputs and outputs of the adder cells are run on p l y because of the involved. The carry-in of the adders is co~ected ground, as shown in to

4 to 1 MUX/DEMUX is shown in Fig. 15.15 (based on the circuit .11). This layout is different from the layouts discussed so far since require power and ground connections and the input/output signals
be connected to the output, the signals S1 and S2 should be the prapagation delay through the n+ should be considered.

Figare 15.12 Schematic and layout of a D P' F.

Layout Step8 by Dean Moriarty, Crystal Semiconductor

Input bus

mps involved in rendering a schematic diagram into its physical layout are: plan, h connect, polish, and verify. Let's illustrate each of these steps in some detail rgh the use of examples.
&g and Stick Diagrams

ng steps start with paper and pencil. Colored pencils are useful for ng one object from another. You can use gridded paper to help achieve a roportion in the cell plan but don't get too bogged down in the details of l i e widths at this point; we just want to come up with a general plan. A " is a paper and pencil tool that you can use to plan the layout of a cell. agram resembles the actual layout but uses "sticks" or lines to represent the When used thoughtfully, it can reveal any special hook-up ut, and you can then resolve them without wasting any time. e 15.16a shows the schematic of an inverter. In order to realize the layout , it is first necessary to define the direction and metalization of the power and output. Since the standard-cell template "sframe" in the for us, we'll use it. Power and ground run horizontally in metal1 7 microns wide. The input and output are accessible f o the top or rm cell and will be in metal2 running vertically. Figure 15.16b shows the k diagram. Note the use of "X" and "0"to denote contacts and vim, ly. The stick diagram should be compared to the resulting layout of Fig.

Figure 15.14 Layout of the complete adder.

S1

S l n o t S 2 S2not

Figure 15.17 Layout of the inverter shown in Pig. 15.16.

@ = 3612, n = 12/2). Furthemore, let's assume that the maximum rec gate width is 20 pn (due to the sheet resistance of the poly) and th

,I,

Suppose the device sizes of the inverter circuit in Figure 15.16a were

maximum could introduce significant unwanted RC &lays. Let's also su are to optimize the layout for size and speed (as most digital circuits are). criteria, it will be necessary to split transistors M1 and M2 in half and lay two parallel "stripes" of 18/2 for the p-channel and two parallel "stripes" n-channel. Figures 15.18a-d show the schematics, stick diagram, and 1 scenario. The output node (drain of M1 and M2) is shared between the minimize the output capacitance. Taking the output in metal2 also h Notice that the stick diagram for this circuit looks like the previous mimw image along the output node. Also observe that the layout o mirrored as shown in the stick diagram. This is a common layout t
Incidentally, LASICKT will need a schematic similar to Fig. 15.1 connectivity of the layout. More sophisticated (and much more e i. software could use the schematic of Fg 15.18a Figure 15.19 shows stick diagrams and layouts for two more the two-input NAND and the two-input NOR. Compare the stick 15.19a and c to the layouts of Figs. 15.19b and d. Observe that the the active area just as in the previous example. Also note that the spaclag gates of the series-connected &vices is minimum (for the CN20process).

VDD

W.18 (a) blwmr* stid diagram used for layout, (c) @) layout, and

(dl Equivalent schematic.

Part II CMOS ~ g i t a
Take another look a the two circuits from a geometrical rather than t viewpoint. Compare the NAND gate layout to the NOR gate layout. Do each can be created from the other by simply "flipping" the metal and p l y about the x-axis?

15 VLSI Layout

305

VDD

k 7
CLK
CLK-

Figure 1520 Schematic of a dynamic register cell.

s the schematic of a dynamic register cell, while Figs. 15.21 a-c show and layout for a dynamic register. Compare the schematic of Fig. of Fig. 15.21a We have labeled this stick diagram will soon become apparent. Notice that there is a break ch will form our n-channel devices. Also note that the "cnwsco~ccted" r mone side of the layout to fo this through very far to notice that, with this clock signals is going fo be very difficult. Now in Fig 15.21b. Notice that we have rearranged the continuous unbroken line. Normally. this "unbroken p r e f d . It usually results in the most workable We say "usually" because at times your layout has to fit in an area ocks around it and you have no control over it. Also observe from clock signal hook-up is more straightforward Compare this stick the layout of Fig. 15.22~. Obviously, the device sizes used for this circuit e is merely to illustrk a layout concept. We can also see 1s a useful tool throughout the layout process.

t t is basically finished, it is time to step back and take a look a it from a of view. Is it pleasing to the eye? Is the hook-up as r ble, o is it "busy" and hard to follow? Are the spaces between 7 What about the space between diffusions? Are there
Figwe 15-19 (a) NAND stick diagram, (b) l a m (c) NOR stick &&
--

- -

3M

Part I1 CMOS Digital Cells Versus Full-Cumom Layout

307

T K

CLK

dard-cell approech to physical design usually dictates that cell height be fixed width be variable when implementing the circuit. Furthermore, standard cells ed to abut on two sides, usually left and tight, and that abutment scheme must regular so that any cell can residc next to any other cell without creating a e violation. The standarden appronch to layout is very useful and is always place to start. However, in the nal world, area on a wafer translates as tinhtly pwked with circuitry as possible. Therefore, it follows that we want -t that is as d l as possible that there can be as many die per wafer as These are the economics of the situation. 'Ihere are also technical advantages from having as small a layout as possible: intercomting wires can be as ible, thereby reducing parasitic loading and d k effects.

so

gure 15.22 shows a typical standardcell block that has been placed and routed c tool. M a t of the individual cells have been omitted for clarity. Notice ect channels between the rows of standard cells. Power, ground, and clock run vertically to both sides of the block by means of a special cell called an ell rows are connected to power and ground through horizontal busses that cells thunselvcs. Al remaining Connections are made via the l standard-cdl l a m are designed to acconnnadate metal2 run vertically through each cell. The autorouter makes use of this ghs aswedadinoEdato~~nmctorpass signalsfromone muting channels and their associated intercomecting forboththe~tysladcircuitperf~ofthistypeof

continue our.discussionof relative layout densiq, we need Eo define a h to quantify the matter. It is customray to use the number of are millimeter of area for this purpose. Because it 4 a raw number s of all circuit layouts, we can use it even when comparing ven unlike pwxsses. of the standard41 route shown in Fig. 15.22 h appmximately millhem. Tbis is faitly represantative of the possible approach and the process used (0.8 pm). Figure a digital filta. The circuit area is approximately The density is approximately 17,500 traasistars per square a 3.5-fold inmase. This circuit, too,is fairrly repnsentative of full-custwm layout using this particular 0.8 pm proWs. Both process, and in fact they are from the same would probably average out to minimum or affecting density is the interconnect wiring. with intercoane!ct wiring is commonly referred t as the o "J'he designer must bcar this burden in terms of both physical

Figun 15.21 Laywt of a dynamic register c l . el

enough contacts? Did you share all of the some and drain shared? Are there sufficient well and substrate ties? If followed the plan described here, you shouldn't run into too

Part 1 CMOS 1

15 VLSI Layout
and electrical parameters (parasitic loading). Let us examine one method high-density custom layout that will minimize interconnect burden and res 15.24 a-c show a small section of the interpolation filter from Fig. 15.23.
.24a, we see an explodeQ view of four cells that form part of a data-path: an

register, a t-gate, a full adder, and an output data register. These are (placed as a cell) twice, creating a view of eight cells. The two adder cells different: the carry inputs and outputs are on opposite sides, so that the ade to the carry-in of the next adder by abutting (placing next to one . Unlike standard cells, the height and width constraints placed on are contextual. In other words, a cell's aspect ratio depends on that of its this case, the width of each cell depended on the maximum allowable idest cell in the group: the data register. Notice the top, bottom, left, and s of each cell in Fig. 15.24a Data enter the register cell from the top t the bottom. Clocks, power, ground, and control signals route across e adder receives its A and B inputs from the top and outputs their SUM As already mentioned, carry-out and carry-in are available on the left f the adder, respectively. Figure 15.24b shows a two-bit slice of this connections made by cell abutment. Figure 15.24c illustrates how all o cell join together t complete the hook-up. e seen how circuits can be implemented by means of standard cells or The time needed to produce a standard-cell route is far less than that of

Rmg h m tr

310

Part 11 CMOS Di

ter 1 VLSI Layout 5 Repeat Problem 1 . for a hvo-input NAND gate. 51 Repeat Problem 1 . for a two-input NOR gate. 51

311

a fullcustom implementation. The trade~ffs area and performance. 4 are place and route tools based on routing area rather than routing channeh coming into use. These promise a compromise solution between the density of their results rivals that of full-custom layout. Perhaps full-custom layout will someday become a thing of the past. Nev technology will continue to advance, circuit &signets will continue that test the outermost limits of this technology, and the marketplace demanding ever cheaper, more powerful, and faster products. It will all still have the opportunity to "push a polygon" or two for There remains no doubt that the future will bring us ever more po that will take over the tedious aspects of placing and connecting layouts the more creative aspects of planning and polishing them.

transmission gate (with the same functionality as Fig. Repeat Problem 1 . for &NAND-basedSR flip-flop. 51

51 Repeat Problem 1. for a NOR-based SR flipflop.

Design, lay out, and simulate the operation of a D R to replace the one described in Fig. 15.12. Assume that the FF uses mainly minimum-size MOSFETs and that a pass transistor is used for the clocking element. , h y out the two-input MUX using TGs shown in Fig. P15.8.

REFERENCES
[I] [2] [3]
[4]

N. H. E. Weste and K. Eshraghian, Principles of CMOS Addison-Wesley, 2nd ed., 1993. ISBN 0-201-53376-6. D. V. Heinbuch, CMOS3 Cell Library, 0-201-1 1257-4. Addison-Wesley, 1

Kerth, Donald A. "Floorphing-LectureNotes" Crystal Semi Kerth, Donald A. "Analog Tricks of the Trade-Lecture Semiconductor, Inc.
J. Uyemura, Physical Design of CMOS Integrated Circuits Using Publishing Co., 1995.ISBN 0-534-94326-8.
SI II

[5]

PROBLEMS 1 . The standard-cell height can be reduced to make standard51 smaller (Fig. P 5 1 . Using this cell as an approximate height 1.) a double inverter.

standard-cell frameheight described in Problem 15.1,lay out s of fig. P15.9. Assume that both the inputs and outputs to

EMUX based on the layout topology given in Fig. to 1 MUX/DEMUX in as small an area as possible.
T. 55 stick diagram for the layouts of F g 1 . .

the high-hpakpce nodes for the schematic of Fig. 1 . 0 Discuss the 52. one must consider when laying out a circuit with high-impedance
s three reasons to have small layout size.

D FP shown in Fig. P15.14. Show the stick diagram for your layout.

part 11 CMOS Digital Circuits 312

Chapter

BiCMOS Logic Gates

E

XNOR
Figure P15.9

Modern BiCMOS technology began in the early 1980s with high expectations [I]. ' I name BiCMOS comes from the fact that the logic is made using CMOS and bipo junction transistors (BJT). The BJTs are used for their high-current capability, wh CMOS is used because of its small layout size and ease of implementing logic. With t best of both worlds on a single substrate, high-speed, high-current-driving bipo transistors and low-power, high-impedance CMOS devices, every major semiconduc~ foundry now possesses some form of BiCMOS process. Strategies for developi BiCMOS have evolved from the bipolar and the CMOS directions, with advantages a disadvantages associated with each. Bipolar device capabilities have been added some CMOS processes to improve speed, while CMOS device capabilities have be added to some bipolar processes to minimize power dissipation. A chart compari CMOS, BiCMOS, and bipolar (with l2L) technologies can be seen in Fig. 16.1 [2,: This chapter focuses on the CMOS process with bipolar capabilities. Although t CN20 process is not a true BiCMOS process, it does contain some BJT options that w allow demonstration of basic digital BiCMOS circuit design. It should be noted that t CMO~14TB process contains no provisions for BJT devices. Microprocessors are particularly well suited for BiCMOS technology. Typical generic categories limit microprocessor performance [I]: (1) Instructions F task3 (2) cycles per instruction, and (3) time per cycle. The third category can be greal 'mproved by increasing the speed critical blocks. A PC microprocessor [41 using a bipolar-based BiCMOS process. Operating at 533 MHz, t micro~r~cessor high-density CMOS devices that were added to a bipolar proce used floor plan can be seen in Fig. 16.2 [S]in which the speed critical blocks such as t Integerand floating point units utilized BJT transistors, while power-consuming cac arrays and I/O cells (for system compatibility) were co&ucted using -CM( rechno~~m.

The