IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO.

7, JULY 2010 2297

Comparison of Neutral-Point-Clamped, Symmetrical,
and Hybrid Asymmetrical Multilevel Inverters
Diorge A. B. Zambra, Student Member, IEEE, Cassiano Rech, Member, IEEE, and
Jos Renes Pinheiro, Member, IEEE
AbstractThis paper presents a comparison of three topologies
of multilevel inverters applied to drive an induction motor of
500 kVA/4.16 kV rating. The multilevel inverters analyzed are
the following: a neutral-point-clamped inverter, a symmetrical
cascaded multilevel inverter, and a hybrid asymmetrical cascaded
multilevel inverter. The performance indexes used in the compar-
ison are total harmonic distortion, rst-order distortion factor,
second-order distortion factor, common-mode voltage, semicon-
ductor power loss distribution, and heat-sink volume. The multi-
level inverters are designed to present 99% efciency at the
nominal operating point, and the aforementioned performance
indexes are compared for distinct values of amplitude modulation
depth.
Index TermsInduction-motor drives, inverters, multilevel
systems, variable-speed drives.
I. INTRODUCTION
I
NDUSTRIES have increased the use of multilevel inverters
for high-voltage applications, such as static var compen-
sators [1], [2], active power lters [3], and adjustable-speed
drives (ASDs) for medium-voltage induction motors [4][6].
ASDs have been used in several industry sectors such as the
petrochemical, mining, water/waste, pulp and paper, cement,
chemical, power generation, metal, and marine sectors. They
are employed in equipment such as pumps, fans, compressors,
blowers, extruders, conveyors, crushers and mills, rolling mills,
mixers, propulsion, test beds, synchronous condensers, gas
turbine starts, hoists, and winders [7].
Nowadays, there are basically three topologies of multi-
level inverters manufactured by industries to be used in drive
systems: neutral-point-clamped (NPC), ying-capacitor, and
symmetrical cascaded multilevel inverters. However, other
topologies are presented in the literature and have interesting
features.
The selection of an adequate multilevel topology to supply a
specic load has been addressed by several researchers. Some
comparative studies regarding multilevel inverters have been
reported in the literature, such as a power loss comparison
between three and four-level diode-clamped inverters [8], and
involving a series-connected H-bridge cell inverter and a two-
Manuscript received March 15, 2009; revised July 19, 2009 and October 23,
2009; accepted November 19, 2009. Date of publication February 8, 2010; date
of current version June 11, 2010.
D. A. B. Zambra is with the Departamento de Cincias Exatas e Tecnologias,
Universidade de Caxias do Sul (UCS), Caxias do Sul 95070-560, Brazil (e-mail:
dabzambra@ucs.br).
C. Rech and J. R. Pinheiro are with the Power Electronics and Control
Research Group (GEPOC), Federal University of Santa Maria, Santa Maria
97105-900, Brazil (e-mail: cassiano@ieee.org; renes@ctlab.ufsm.br).
Digital Object Identier 10.1109/TIE.2010.2040561
level inverter [9]. In addition, there are comparisons among
diode-clamped, ying-capacitor, and cascaded multilevel in-
verters [10][12] and among the two-level, three-level NPC,
three-level and four-level ying-capacitor, and ve-level series-
connected H-bridge cells inverter [13]. Another study has com-
pared two hybrid multilevel inverters with the same number of
cells connected in series [14]. Symmetrical and hybrid asym-
metrical multilevel inverters with the same number of output
voltage levels are compared in [15], and three topologies of
multilevel inverters with the same output lter are compared
in [16].
A fair comparison should consider that all multilevel invert-
ers have the same efciency. Therefore, the main subject of
this paper is to compare symmetrical and hybrid asymmetrical
cascaded multilevel inverters with the same number of output
voltage levels and the NPC inverter, which is the most com-
monly employed multilevel inverter. Multilevel inverters are
designed to present 99% efciency at the nominal operating
point, and some performance indexes are compared for distinct
values of amplitude modulation depth.
The main contributions of this paper are the following:
1) to present a comparison methodology with some perfor-
mance indexes that can be applied to analyze distinct multilevel
congurations; 2) to apply this comparison methodology to
three well-known multilevel inverters; and 3) to indicate the
most attractive topology to use in a specic application.
This paper is organized as follows: Section II presents the
drive systems, and Section III shows the modulation applied to
each multilevel inverter. Section IV exhibits the performance
indexes that are used in the comparison analysis. Section V
shows the theoretical results of the comparative analysis.
Section VI presents some experimental results, and Section VII
presents the nal conclusions.
II. DRIVE SYSTEMS
The multilevel inverters shown hereinafter are designed to
supply an induction motor with the following specications:
1) line-to-line voltage: 4.16 kV;
2) input-voltage frequency: 60 Hz;
3) phase current: 68.4 A;
4) apparent power: 500 kVA;
5) power factor: 0.85.
The three multilevel inverters can be seen in Fig. 1, where
V
dc
is equal to 6800 V.
0278-0046/$26.00 2010 IEEE
2298 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 7, JULY 2010
Fig. 1. Multilevel inverters: (a) NPC; (b) 1-1-1-1; and (c) 1-1-2.
A. Three-Level NPC Inverter
One leg of an NPC inverter can be seen in Fig. 1(a). The
other legs of this inverter use the same dc link. The highest
voltage across the semiconductors is 3400 V. Therefore, the
devices used in this topology are modules of insulated gate
bipolar transistors (IGBTs)/diodes FZ200R65KF1 [17].
B. Nine-Level Symmetrical Inverter
One leg of a nine-level symmetrical inverter is shown in
Fig. 1(b). This inverter can be called 1-1-1-1, because it presents
four H-bridge series-connected cells with input dc voltage
sources with the same voltage amplitude. To generate a line-
to-neutral voltage with a peak value of 3400 V, the dc sources
must be equal to 850 V. The device used to implement the
H-bridge cells is the module BSM200GB170DLC [18].
C. Nine-Level Hybrid Asymmetrical Inverter
One leg of a nine-level hybrid asymmetrical inverter can be
observed in Fig. 1(c). This conguration can be called 1-1-2,
and it receives this name because the voltage amplitude of the
input dc voltage source that supplies cell 3 is twice the dc
voltage amplitude of cells 1 and 2. The dc voltage sources
of cells 1 and 2 are equal to 850 V, while the dc voltage
source of cell 3 is 1700 V. The devices used to implement
the highest power cell (cell 3) are the gate turn-off thyristors
(GTOs) DG408BP45 [19] and the diodes DSF8045SK [20],
while the module of IGBTs/diodes BSM200GB170DLC [18]
is employed in the lower power cells (cells 1 and 2).
III. MODULATION TECHNIQUES
Several modulation techniques can be applied to each multi-
level inverter topology. Sinusoidal pulsewidth modulation
(PWM) uses multiple triangular carriers compared with a si-
nusoidal reference. This technique is easily implemented and
has been extensively used for multilevel inverters [21], [22].
In addition, space vector modulation (SVM) has been used in
voltage-source inverters to decrease the number of commu-
tations, to decrease the harmonic content of output voltages,
and to increase the linear operation range [23], [24]. Due to
these features, SVM has been applied to distinct multilevel
Fig. 2. Modulation techniques: (a) Phase disposition. (b) Phase-Shift.
(c) Hybrid.
topologies, including NPC [25] and cascaded inverters [26],
[27]. However, the application of SVM in cascaded topologies
is usually limited to a small number of levels, due to the large
number of switching vectors.
In this paper, simple and efcient modulation techniques
were applied to each multilevel converter, which are presented
in this section.
A. Phase Disposition
The phase-disposition PWM technique was used with the
NPC inverter. The reference signal and the two carriers can be
veried in Fig. 2(a); these values are normalized, and therefore,
they are presented in per unit (p.u.) values. In this strategy, the
most signicant harmonic appears around the carrier frequency.
However, this component does not appear in the line-to-line
voltages. This technique guarantees only odd harmonics for odd
values of the frequency modulation depth (m
f
)[21].
B. Phase Shift
Phase-shift PWM technique [21], [22] was used with the
symmetrical multilevel inverter. To generate a line-to-neutral
voltage with m levels, this strategy uses (m 1) carriers with
the same voltage amplitude and with 360/(m 1) degrees
ZAMBRA et al.: COMPARISON OF NPC, SYMMETRICAL, AND HYBRID ASYMMETRICAL MULTILEVEL INVERTERS 2299
phase-shift among them. For an m-level converter, the most
signicant harmonics are located in lateral bands around
(m 1)f
p
, where f
p
is the carrier frequency. For even values of
m
f
, the waveforms synthesized present quarter-wave symme-
try, resulting in only even harmonics [22]. Thus, for a nine-level
symmetrical inverter, this strategy uses eight carriers with 45

phase-shift among them, as can be seen in Fig. 2(b).

C. Hybrid
The hybrid multilevel modulation technique is used to guar-
antee that some cells operate at low frequency and only one
cell operates at high frequency. This strategy associates the
stepped voltage waveform synthesis in higher power cells with
high-frequency PWM for the lowest power cell [28]. A block
diagram that describes this modulation strategy can be veried
in Fig. 2(c), where V
3
, V
2
, and V
1
are the normalized voltage
amplitude of the dc sources that supply each cell;
3
and
2
represent the comparison levels of cells 3 and 2, respectively;
r
3
(t), r
2
(t), and r
1
(t) are the reference signals; v
3
(t), v
2
(t),
and v
1
(t) are the output voltage of each cell; and v
out
(t) is the
output line-to-neutral voltage.
The comparison levels employed in the comparison are con-
stant:
3
= 2 p.u. and
2
= 1 p.u.
IV. PERFORMANCE INDEXES
The performance indexes used in the comparative analysis
are the following: total harmonic distortion (THD), rst-order
distortion factor (DF1), second-order distortion factor (DF2),
semiconductor power loss, heat-sink volume, and common-
mode voltage.
A. THD
The THD of a signal is the ratio of the sum of the powers
of all harmonic frequencies above the fundamental frequency
to the power of the fundamental frequency, and it can be
obtained by
THD% =
100
U
1

h=2
U
2
h
(1)
where U
1
is the rst harmonic of the signal analyzed, h is the
harmonic order, and U
h
is the harmonic that presents order h.
B. DF1
In induction motor applications, the leakage inductances
provide rst-order attenuation [21]. Therefore, DF1 represents
the rst-order attenuation of the harmonics in the output voltage
of the inverter, and it can be computed by
DF1% =
100
U
1

h=2
_
U
h
h
_
2
. (2)
C. DF2
A second-order attenuation in the harmonic voltages is ob-
tained using a second-order lter in the output of the converter
[21]. Consequently, DF2 is given by
DF2% =
100
U
1

h=2
_
U
h
h
2
_
2
. (3)
D. Common-Mode Voltage
Common-mode voltage v
cm
is dened as
v
cm
=
V
an
+V
bn
+V
cn
3
(4)
where V
an
, V
bn
, and V
cn
are the three line-to-neutral voltages.
Therefore, the rms value of the common-mode voltage (V
cm
)
can be found by using
V
cm
=
_
V
2
cm
1
+V
2
cm
2
+ +V
2
cm
h
(5)
where V
cm
h
is the hth harmonic of the common-mode voltage
waveform.
E. Semiconductor Power Losses
The semiconductor devices employed in each conguration
were dened from the voltage and current ratings of each
inverter, and they were dened in Section II.
The semiconductor power losses can be estimated from the
curves v
sat
() versus i
l
(), and E() versus i
l
(), presented
in the datasheet of each device, where v
sat
is the ON-state
saturation voltage (v
ce
() for the IGBT, v
F
() for the diode,
and v
TM
() for the GTO); E() represents the energy loss in
one commutation (E
on
() for a turn-on commutation, E
o
()
for a turn-off commutation, and E
rec
() for a diode reverse
recovery process); and i
l
() is the load current.
These curves are used in a Matlab script developed to com-
pute the power losses. This software uses the mathematical
models that best represent the functions v
sat
(i
l
()), E
on
(i
l
()),
E
o
(i
l
()), and E
rec
(i
l
()) for each semiconductor device.
The mathematical models are found using the points extracted
from the datasheets of each semiconductor and using the curve-
tting tool. The mathematical models obtained for the semicon-
ductor devices are presented in the Appendix.
Based on the models for each device, the conduction and
switching power losses are calculated for each semiconductor.
The sum of all losses is computed to obtain the total power
losses.
Conduction power losses are those that occur while the
semiconductor device is conducting current, and there is a
voltage between its terminals, v
sat
to the main switch and v
f
for
the diode. The conduction power losses of the main switches
(IGBTs or GTOs) and diodes are computed from (6) and (7),
respectively, i.e.,
P
cond
SW
=
1
2
2
_
0
v
sat
() |i
l
()| v
cmd_SWx
()d (6)
P
cond
D
=
1
2
2
_
0
v
F
() |i
l
()| v
cmd_SWx
()d (7)
i
l
() =m
a
I
max
sin( ) (8)
2300 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 7, JULY 2010
where m
a
is the amplitude modulation depth, is the load
displacement angle, and v
cmd_SWx
() is the command signal
of the switch SWx (0 or 1).
Therefore, the total conduction losses are obtained by adding
up the conduction losses of all semiconductors
P
cond
TOTAL
= P
cond
SW
+P
cond
D
. (9)
The switching losses are obtained by identifying every turn-
on and turn-off instant during one reference period (T). There-
fore, the turn-on, turn-off, and reverse-recovery losses can be
computed, respectively, from the following:
P
on
=
1
T

E
on
(i
l
()) (10)
P
o
=
1
T

E
o
(i
l
()) (11)
P
rec
=
1
T

E
rec
(i
l
()) . (12)
Then, the total switching losses are the sum of the turn-
on, turn-off, and reverse-recovery losses of all semiconductor
devices
P
comut
TOTAL
= P
on
+P
o
+P
rec
. (13)
The total losses are the sum of all conduction and switching
power losses, i.e.,
P
TOTAL
= P
cond
TOTAL
+P
comut
TOTAL
. (14)
F. Heat-Sink Design
The reliability and the life expectancy of any semiconductor
device are directly related to the maximum device junction
temperature [29].
The 1-D model depends on thermal resistance, which is de-
ned as the ratio of temperature variation to power dissipation
R
HSsw
=
T
HSsw
T
a
P
dsw
(15)
where P
dsw
is the average power dissipation, T
a
is the room
temperature, and T
HSsw
is the heat-sink temperature, given by
T
HSsw
= T
j max
P
dsw
(R
jc
+R
cs
). (16)
The advantage of the 1-D model is its simplicity. This model
supposes that all heat is transferred to the environment by
the nned heat sink. It also considers that the temperature is
constant over the entire heat-sink surface. Then, the application
of the 1-D model has some restrictions: junction temperature
is considered constant (steady state) and only one power-
dissipation device is placed at the center of the heat sink.
The traditional thermal equivalent circuit is shown in
Fig. 3(a), where R
jc
is the thermal resistance between the
junction and case, R
cs
is the thermal resistance between the
case and heat sink, R
sa
is the thermal resistance between
the heat sink and the environment, and R
ca
is the thermal
resistance between the case and the environment. This resis-
tance (R
ca
) is considered large by comparison with the other
model components and thus, it can be ignored.
Fig. 3(b) shows the model for one switch or diode. This
model was used to dene the heat-sink resistance for the
Fig. 3. Thermal equivalent circuits: (a) Traditional. (b) One switch or one
diode. (c) Module with one switch and one diode. (d) Module with two switches
and two diodes.
TABLE I
THERMAL RESISTANCES OF DEVICES AND MODULES
Fig. 4. Heat-sink prole: (a) HS21577. (b) HS125137. (c) HS125135L.
devices DG408BP45 and DSF8045SK. Fig. 3(c) shows the
circuit that represents a module with one switch and one
diode, and it is used to obtain the heat-sink resistance for
the module FZ200R65KF1. Fig. 3(d) shows the circuit that
represents a module with two switches and two diodes, and
it is used to obtain the heat-sink resistance for the module
BSM200GB170DLC. The two last models present only one
resistance between the case and the heat-sink because the
devices are packaged. The thermal resistances used in the
heat-sink design were extracted from the datasheet of each
device/module, and they are presented in Table I.
In accordance with the heat-sink design, it is necessary
to dene the heat-sink prole. Three heat-sink proles are
considered in order to select the one that presents the least
volume. The proles are the HS21577, the HS125137, and the
HS125135L [30], which can be seen in Fig. 4(a)(c).
ZAMBRA et al.: COMPARISON OF NPC, SYMMETRICAL, AND HYBRID ASYMMETRICAL MULTILEVEL INVERTERS 2301
Fig. 5. Heat-sink information: (a) Relation between thermal resistance and
cooler air speed. (b) Temperature variation correction factor. (c) Length correc-
tion factor.
The datasheet of the heat-sink manufacturer shows one curve
of thermal resistance as a function of airow speed. Fig. 5(a)
shows the points extracted from the datasheet of each heat-
sink prole and the curve obtained using the equations that best
describe these points, as given in the Appendix, (40), (41), and
(42), respectively, for HS21577, HS125137, and HS125135L.
One can see from Fig. 5(a) that the use of a cooler is necessary
because it signicantly decreases the thermal resistance when
the air speed is about 2 m/s. These curves consider T = 75

C
and a length of 4 in. For other Ts and lengths, the designer
needs to use the correction factor of the temperature (F
T
) and
the length (F
L
)
F
T
=0.6859 e
(0.04873T)
+ 1.183 e
(0.002477T)
(17)
F
L
=
R
HSsw
R
HS21577
F
T
. (18)
These correction factors are shown in Fig. 5(b) and (c).
Finally, the length correction factor is substituted in (19), and
then, it is possible to nd the heat-sink length
L =
_
8.239F
L
1.74
F
3
L
0.6121F
2
L
+ 0.2681F
L
0.056
_
10. (19)
The heat-sink volume is obtained through the product of all
dimensions; width (W), height (H), and length (L) of the heat
sink
V ol
HSsw
= WHL. (20)
V. COMPARATIVE ANALYSIS
The switching frequencies in which the three systems will
present 99% efciency must be found in order to carry out
the comparative analysis. The switching frequency obtained for
the NPC with phase-disposition modulation is 720 Hz, for the
symmetrical inverter with phase-shift modulation is 420 Hz,
and for the asymmetrical inverter with hybrid modulation is
7140 Hz for the lowest power cell. With these switching fre-
quencies, the efciencies of all inverters are around 99.1%. The
total power losses for one leg are 1475 W for the NPC inverter,
1484 W for the symmetrical inverter, and 1476 W for the hybrid
asymmetrical inverter.
This section presents all theoretical results for the switching
frequencies presented earlier. Initially, the results for the entire
operating range of the inverter (0.1 m
a
1) are presented.
Then, the results for the nominal condition (m
a
= 1) are
shown.
A. Entire Operating Range
This section shows the THD, DF1, and DF2 of the line-to-
line voltage and the power losses for the entire range of the
inverters, i.e., 0.1 m
a
1.
The variation of the line-to-line voltage THD for the three
systems is shown in Fig. 6(a). The line-to-line voltage THD for
the topology 1-1-1-1 is about 0.5 times higher than the THD
obtained with the topology 1-1-2 in almost the entire operating
range. The line-to-line voltage THD for the NPC inverter is
from 2.8 up to 4.7 times higher than the THD in the 1-1-2
inverter.
The variation of line-to-line voltage DF1 is shown in
Fig. 6(b). The DF1 of inverter 1-1-1-1 is approximately ve
times higher than the DF1 of the 1-1-2 inverter. The DF1 of the
NPC inverter is from 18 up to 55 times higher than the DF1
value found for the 1-1-2 inverter.
Fig. 6(c) shows the variation of the line-to-line voltage DF2.
Topology 1-1-1-1 presents a DF2 value ve times higher than
that obtained for the 1-1-2 topology. The NPC inverter presents
a DF2 value range from26 up to 100 times higher than the 1-1-2
topology.
The normalized rms values of the common-mode voltage
waveforms are shown in Fig. 6(d), where the base value is
V
dc
(6800 V). The 1-1-2 and 1-1-1-1 topologies present similar
values of common-mode voltage in the entire operating range,
whereas the NPC inverter has high common-mode voltage. At
m
a
= 0.6, the common-mode voltage of the NPC inverter is six
times higher than the values obtained with the 1-1-2 and 1-1-1-1
topologies.
Fig. 6(e) shows the power loss variation for the entire operat-
ing range of the inverters. As mentioned before, the switching
frequencies were obtained to result in the same efciency in
the nominal operating point. This fact is conrmed because all
inverters present the same power losses at m
a
= 1. In almost
the entire operating range, inverter 1-1-1-1 has the lowest power
losses, and the NPC inverter presents up to three times more
losses than the 1-1-2 topology.
B. Nominal Operating Point
This section presents the harmonic spectrum, the semi-
conductor power loss distribution, the heat-sink volume
2302 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 7, JULY 2010
Fig. 6. Results for all operation range: (a) THD. (b) DF1. (c) DF2. (d) Vcm.
(e) Power losses.
distribution for three heat-sink proles, and a summary table
with the main results computed for m
a
= 1.
Fig. 7 shows the harmonic spectrum of the line-to-line volt-
age waveform for the three multilevel inverters. The line-to-
line voltage spectra of the NPC and 1-1-2 inverters do not
present the most signicant harmonics that appear in the line-
Fig. 7. Harmonic spectrum of the line-to-line voltage waveforms.
Fig. 8. Semiconductor power loss distribution: (a) NPC. (b) 1-1-1-1. (c) 1-1-2.
to-neutral voltage waveforms. There are only lateral bands at
the frequencies of 720, 3360, and 7140 Hz, respectively, for the
NPC, 1-1-1-1, and 1-1-2 inverters. The frequency of the rst-
harmonic band directly affects the DF1 and DF2. These two
distortion factors reveal that the output lter of the NPC and
1-1-1-1 inverters will have greater volume, weight, and cost
than the lter used in the 1-1-2 inverter to obtain the same
output line-to-line voltage distortion.
Fig. 8(a)(c) shows the semiconductor power loss distribu-
tion for the NPC, 1-1-1-1, and 1-1-2 inverters.
In the NPC inverter, the semiconductor power losses are con-
centrated in the switches SW1 and SW4. This occurs because
switch SW2 does not commutate in the positive semicycle
to generate zero voltage. Therefore, this switch presents only
conduction losses. Similarly, this fact occurs in the negative
semicycle for switch SW3.
ZAMBRA et al.: COMPARISON OF NPC, SYMMETRICAL, AND HYBRID ASYMMETRICAL MULTILEVEL INVERTERS 2303
Fig. 9. Heat-sink volume distribution (a) NPC. (b) 1-1-1-1. (c) 1-1-2.
In the 1-1-1-1 inverter, all cells present approximately the
same semiconductor power losses, since all cells operate with
the same frequency. The conduction power losses are the most
signicant losses of this inverter because all switching devices
commutate at a low switching frequency.
In the 1-1-2 inverter, cell 3 has the lowest power losses
because it operates at a fundamental frequency. Cell 2 operates
at 180 Hz, and its power losses are small. In both cells the
conduction power losses are the most signicant losses. The
switching frequency of cell 1 is 7140 Hz, and the switching
losses are the most signicant losses for this cell.
Using the semiconductor power losses, the thermal models
of the semiconductors, and the heat-sink proles provided in
Section IV, it is possible to determine the heat-sink length
for each device/module. Fig. 9(a)(c) shows the heat-sink vol-
ume for each prole, for NPC, 1-1-1-1, and 1-1-2 inverters,
respectively.
The smallest heat-sink length was obtained with prole
HS21577. For this prole, the sum of all heat-sink lengths is
equal to 87.2 cm for the NPC inverter, 67.1 cm for the symmet-
rical inverter, and 60.4 cm for the hybrid asymmetrical inverter.
The sum of all heat-sink volumes is equal to 14 434 cm
3
for the NPC inverter, 11 100 cm
3
for the symmetrical inverter,
and 10 002 cm
3
for the asymmetrical inverter.
The NPC presents the highest heat-sink length and volume
because almost all power losses are concentrated in only two
devices, while the power losses of the cascaded topologies
are divided into four devices from each H-bridge cell. Conse-
quently, the variation of temperature and the thermal resistance
of these two devices of the NPC inverter present smaller values
than those obtained with the other topologies. As these quan-
tities are described by exponential equations, small values can
result in large differences.
Table II presents a summary of all performance indexes
analyzed in comparison with m
a
= 1. Items with interesting
features are in bold. On the other hand, Table III shows the
efciencies of the three topologies when they present the same
harmonic performance, i.e., the same THD, DF1, or DF2.
In these cases, the switching frequency needed to obtain the
same THD, DF1, and DF2 was determined. These analyses are
performed to the 100th harmonic. Topology 1-1-2 presents the
highest efciency among the three cases, and the NPC inverter
presents the lowest efciency.
VI. EXPERIMENTAL RESULTS
This section presents some experimental results obtained
with a low-power prototype of one leg of the 1-1-2 inverter.
This multilevel inverter uses three H-bridge cells in series, and
its nominal output power is 1 kW. The isolated dc voltage
sources are the following: V
DC1
= 85 V, V
DC2
= 85 V, and
V
DC3
= 170 V. These dc voltage sources are implemented
using a multipulse transformer and four three-phase rectiers,
where the nominal load of each rectier is as follows: P
1
=
133 W, P
2
= 230 W, P
3
= 318.5 W, and P
4
= 318.5 W. The
dc voltage source of cell 3 is obtained with two series-connected
rectiers (rectiers 3 and 4) [31], [32].
All H-bridge cells are implemented using the IGBT module
SK45GB063 (600 V/30 A). The mathematical models of the
SK45GB063 are given in the Appendix (35)(39). The power
losses of each cell are computed from the mathematical model
of each semiconductor, and the theoretical efciencies are
presented in Table IV.
Fig. 10 shows the measurements of input and output variables
of each cell of the 1-1-2 inverter, where UrmsX, IrmsX,
and PX represent, respectively, the voltage, current, and active
power of each channel X (X = 1, 2, 3, 4, 5, and, 6). Channels
1, 2, and 3 represent the input measurements of the cells 1, 2,
and 3, respectively, while channels 4, 5, and 6 represent the
output measurements of these cells. The parameters F1, F2,
and F3 are the efciencies of cells 1, 2, and 3. P

A is the
total input active power, P

B is the total output active power,

and is the total efciency of the converter. The efciency of
each H-bridge cell obtained in the prototype can be seen in
Table IV. One can observe that the theoretical efciencies are
similar to the experimental efciencies.
VII. CONCLUSION
This paper has presented a comparison of three topologies
of multilevel inverters, namely, the NPC inverter and two
nine-level inverters with H-bridge cells connected in series,
where one conguration is hybrid and asymmetrical and the
other is symmetrical. The multilevel inverters were designed
to present 99% efciency at the nominal operating point, and
some performance indexes were compared for distinct values
of the amplitude modulation depth.
2304 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 7, JULY 2010
TABLE II
SUMMARY OF THE COMPARISON(m
a
= 1)
TABLE III
EFFICIENCY COMPARISON FOR THE SAME HARMONIC PERFORMANCE
TABLE IV
COMPARISON BETWEEN THE THEORETICAL AND
EXPERIMENTAL RESULTS
Fig. 10. Measurements of the 1-1-2 inverter.
Based on the results, the 1-1-2 topology presents the highest
switching frequency but the lowest values for THD, DF1, and
DF2. Moreover, it presents the smallest heat-sink volume.
Although the NPC inverter is the most used multilevel in-
verter, it presents the worst values for THD, DF1, and DF2 and
the largest heat-sink volume.
The main advantages of the NPC inverter are its simplicity,
the use of a small number of semiconductor devices, and the
requirement of only one dc voltage source to supply the three
legs of the inverter. However, the cost of the semiconductor
devices increases exponentially with higher voltage ratings, and
the complexity of the transformer used in the cascaded topolo-
gies does not signicantly affect the cost, since the cost of the
transformer is directly related to its power rating. Therefore,
the cost of cascaded topologies is not necessarily higher than
the NPC inverter, and cascaded topologies may present low-
distortion output voltage and higher efciency.
APPENDIX
SEMICONDUCTORS AND HEAT-SINK MODELS
The mathematical models obtained for module
BSM200GB170DLC are given by (21)(25); for the GTO
DG408BP45 and diode DSF8045SK are given by (26)(29);
for the module FZ200R65KF1 are given by (30)(34); and
for the heat sinks HS21577, HS125137, and HS125135L are
given, respectively, by (40)(42)
v
ce
BSM
=0.27I
l
()
0.47
+ 0.025 (21)
v
F
BSM
=0.29I
l
()
0.38
0.057 (22)
E
on
BSM
=
_
98.93e
(0.004I
l
())
95.77e
(0.002I
l
())
_
10
3
(23)
E
off
BSM
=
_
63.57e
(0.002I
l
())
63.78e
(0.003I
l
())
_
10
3
(24)
E
rec
BSM
=
_
55.87e
(0.0002I
l
())
63.31e
(0.011I
l
())
_
10
3
(25)
v
TM
DG
= 0.26I
l
()
2
+ 2.32I
l
() + 1.47 (26)
v
F
DSF
= 2.79.10
6
I
l
()
2
+ 0.005I
l
() + 1.19 (27)
E
on
DG
=
_
4 10
5
I
l
()
2
+ 1.43I
l
() + 220
_
10
3
(28)
E
off
DG
=
_
8 10
4
I
l
()
2
+ 4I
l
() 189.1
_
10
3
(29)
v
ce
FZ
=3.78e
(0.002I
l
())
2.70e
(0.015I
l
())
(30)
ZAMBRA et al.: COMPARISON OF NPC, SYMMETRICAL, AND HYBRID ASYMMETRICAL MULTILEVEL INVERTERS 2305
v
F
FZ
=2.9e
(0.0016I
l
())
2.35e
(0.015I
l
())
(31)
E
on
FZ
=
_
1058e
(0.004I
l
())
1011e
(0.004I
l
())
_
10
3
(32)
E
off
FZ
=
_
1051e
(0.002I
l
())
1097e
(0.005I
l
())
_
10
3
(33)
E
rec
FZ
=
_
211e
(0.004I
l
())
_
10
3
(34)
v
ce
SK45
=1.598e
(0.008045I
l
())
1.573e
(0.09678I
l
())
(35)
v
F
SK45
=1.016e
(0.005818I
l
())
1.012e
(0.1285I
l
())
(36)
E
on
SK45
=
_
3.31e
(0.058I
l
())
2.93e
(0.059I
l
())
_
10
3
(37)
E
off
SK45
=
_
10.3e
(0.0038I
l
())
10.1e
(0.0077I
l
())
_
10
3
(38)
E
rec
SK45
=
_
2.69e
(0.006I
l
())
2.63e
(0.012I
l
())
_
10
3
(39)
R
HS21577
=0.3661e
(0.9446V el)
+ 0.1589e
(0.04784V el)
(40)
R
HS125137
=0.4305e
(1.031V el)
+0.2351e
(0.07816V el)
(41)
R
HS125137
=0.4305e
(1.031V el)
+0.2351e
(0.07816V el)
.
(42)
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2306 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 7, JULY 2010
Diorge A. B. Zambra (S08) was born in Iju, RS,
Brazil, in 1980. He received the B.S. degree in elec-
trical engineering from the Universidade Regional
do Noroeste do Estado do Rio Grande do Sul, Iju,
Brazil, in 2003, and the M.S. degree in electrical
engineering from the Federal University of Santa
Maria, Santa Maria, Brazil, in 2006, where he is cur-
rently working toward the Ph.D. degree in electrical
engineering.
Since 2009, he has been with the Universidade de
Caxias do Sul, Caxias do Sul, where he is currently a
Professor. His research interests include multilevel converters and modulation
techniques.
Cassiano Rech (S01M06) was born in Carazinho,
RS, Brazil, in 1977. He received the B.S., M.S.,
and Ph.D. degrees in electrical engineering from
the Federal University of Santa Maria, Santa Maria,
Brazil, in 1999, 2001, and 2005, respectively.
From 2005 to 2007, he was with the Universidade
Regional do Noroeste do Estado do Rio Grande do
Sul, Iju, Brazil. From 2008 to 2009, he was with
the Santa Catarina State University, Joinville, Brazil.
Since 2009, he has been with the Federal University
of Santa Maria, where he is currently a Professor. His
research interests include multilevel converters, modeling, and digital control
techniques of static converters.
Jos Renes Pinheiro (S93M95) was born in
Santa Maria, Brazil, in 1958. He received the B.S.
degree in electrical engineering from the Federal
University of Santa Maria, in 1981 and the M.S.
and Ph.D. degrees in electrical engineering from the
Federal University of Santa Catarina, Florianpolis,
Brazil, in 1984 and 1994, respectively.
Since 1985, he has been a Professor with the
Federal University of Santa Maria, where, in 1987,
he founded the Power Electronics and Control Re-
search Group (GEPOC). From 2001 to 2002, he was
with the Center for Power Electronics Systems (CPES), Virginia Polytechnic
Institute and State University (Virginia Tech), Blacksburg, as a Postdoctoral
Research Scholar. He has authored more than 200 technical papers published
in the proceedings of conferences and journals. His current research interests
include high-frequency and high-power conversion, power supplies, multi-level
converters, and modeling and control of converters.
Dr. Pinheiro was the Technical Program Chairman of the 1999 Brazilian
Power Electronics Conference (COBEP) and of the 2000 and 2005 Power
Electronics and Control Seminar (SEPOC).