Fujitsu Semiconductor Europe Factsheet Fujitsu ARM Cortex Design Support

Fujitsu ARM Cortex Design Support

ATB

FASP Support (Fujitsu ARM based SoC Prototyping Kit) I FASP is a reference design concept of ARM based SoC I All Fujitsu IPs are integrated into a reference design I FASP consists of a reference design (RTL), simulation environment, example program (boot code), synthesis environment, net list, verification environment (FV script and example STA scripts) I FASP enables the customer to shorten the design TAT and verification TAT I FASP will support the following ARM cores: - CortexTM-M3 - Cortex-A9 - Cortex-R4F - Cortex-A5 (planned) - Cortex-A15 (planned)

ATB

ATB

ATB

Cortex-A9 Core Bock

Cross Trigger

PTM

PTM

PTM

PTM

CTM FPU/NEON CTI PTM I/F FPU/NEON PTM I/F FPU/NEON PTM I/F FPU/NEON PTM I/F

Cortex-A9 CPU ROM Table Interrupt Signals Debug APB I-Cache D-Cache Generic Interrupt Control and Distribution

Cortex-A9 CPU I-Cache D-Cache Timers/ Watchdog

Cortex-A9 CPU I-Cache D-Cache Snoop Control Unit (SCU)

Cortex-A9 CPU I-Cache D-Cache Accelerator Coherence Port (ACP) ACP

64-bit AXI Interface APB_MUX APB_DEC APB_SYNC

Bus Interface Unit Optional 64-bit AXI Interface

PL310

Debug APB

Cortex-A9 Block diagram

ARMONDE-A9 (ARM Evaluation Chip) This ARM evaluation chip is targeted to develop high performance ARM based SoCs and contains therefore the Cortex-A9, Cortex-R4 and Cortex-M3 cores. In the future, the EV chip will have implemented Fujitsu advanced IPs like PCIgen2, SATAgen2, USB3.0, etc. This EV chip enables designers to develop IP drivers and OS. Also, the TAT for SoC prototyping will be much shorter. An Evaluation Board will also be provided with the ARMONDE-A9. This board is available with an LCD monitor (touch panel) and FPGA for user logic extension. The following deliverables are available with the board: I FPGA reference design I Software (OS: Linux, ITRON or Android) I Drivers for IPs I ARMONDE-A9 Block Diagram I IPs used on ARMONDE-A9 (see table on P2)

ARMONDE-A9
UDL Extention PCIe RC/EP Gen2-4Lane PCIe RC/EP Gen2-4Lane SRAM 16k SRAM 16k SATA Gen2 Host USB3.0 Func

HSIO Block
64bit

DDRC Block

NIC-301 AXI 300MHz 64-bit

32-bit GMAC SRAM NoE GMAC NoE 64-bit BB BB BB NIC-301 AXI 300M/64-bit LCDIF x 2 2DGPU 3DGPU

GPU Block
64bit

Multi-port MEMC

Controller Block
DMAC

AP Block Cortex-A9 2MP 500MHz

L2CC (PL310) NIC-301 AXI 300MHz 64-bit 64bit DMAC ACP

32bit

DDR3 600

Cortex-R4F 250MHz

SRAM

BP137

BP137

Cortex-M3 125MHz
AHB BusMatrix

BP137 DAP H2XBB AHB-AP AHB BusMatrix USB2.0 Host/ APB Func GMAC

BP137 DMAC AHB BusMatrix 75MHz H2PBB DMAC SDRAMC Reg. APB SDIO MRBC, CRG11, EXIU, GPIO, UART H2PBB CCPB

AHB BusMatrix

ARM IP ADK/Primecell FSL IP 3rd IP

VIC

H2PBB APB

SRAM 64k x 2 DMAC I2S

IPCU

H2PBB

SFI DAP System APB MEMC TIMER WDT

TIMER/WDT

TPIF

SPI/I2C/ MCC

SRAM

RELC

FLASH

Operating frequency (except as otherwise stated) AXI= 64-bit/300MHz, AHB= 32-bit/150MHz, APB= 32-bit/75MHz

ARMONDE-A9 Block diagram

Page 1 of 2

Factsheet Fujitsu ARM Cortex Design Support

IPs on ARMONDE-A9 Processor Category

IP Name

Interface Macro

Memory I/F CPU Peripherals Bus Interconnect Others

SDRAMC MEMCS SPI

PCIe SATA USB3.0 USB2.0 HDC GMAC SDIO UART I2C I2S SSP (PL022) NoE TPIF

Cortex-A9 MPcore Cortex-R4F Cortex-M3 GPU

Descriptions

PCI Express Gen2, Root/Endpoint, 4-lanes (2-ch/SoC IF + FPGA extension) Serial ATA Host Gen2 USB3.0 Function USB2.0 Host/Function DMAC Ethernet MAC 1000/100base, 802.3az (LPI), GMII, IEEE1588 UHS-1(eMMC) UART (2-ch) I2C (1-ch) I2S (1-ch) + DMAC Compatible with Motorola SPI, TI SSI and National Semiconductor Microwire 2ch IPSec Network Off-load Engine with GMAC4MT (700Mbps half duplex IPSEC) Touch Panel Interface (Multi-touch detection) DDR2/3-600MHz 32-bit Flash/SRAM Controller Quad Serial Flash Controller

Dual-core, 500MHz, L1 cache I/D=32KB/32KB, L2 cache = 512KB, ACP-DMA 250MHz, L1 cache =16KB/16KB, TCM_A=64KB, TCM_B0=32KB, TCM_B1=32KB 125MHz OpenGL ES1.1/OpenGL ES2.0/OpenVG1.1, LCD Controller (2-ch)

NIC-301 AHB BusMatrix

OPAL/RELC/ADC

ARM Network Interconnect (AXI, AHB, APB) AHB Interconnect

VIC (Vectored Interrupt Controller), CRG11 (ClockReset Generator), IPCU (Inter-processor Communication Unit), GPI0, Watchdog, Timer, MRBC (Remap and Boot Controller), SYSOC (System Operation Controller), SRAM on AXI (128KB), SRAM on AHB (64KB x2)

Instruction encryption/data compression and decompression / ADC 2ch for touch panel control

High-speed Cortex-A9 HLB (Hierarchical Layout Block) I 65nm: 600MHz I 40nm: 800MHz I 28nm: 1000MHz

All company and product trade marks and registered trade marks used throughout this literature are acknowledged as the property of their respective owners.

asic.fseu@de.fujitsu.com http://emea.fujitsu.com/asic
FSEU-A52-28SEPT11

Page 2 of 2