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ELEC2102
Lecture Notes #3
De Montfort University
Faculty of Computer Sciences and Engineering
Department of Engineering and Technology
Digital Electronics – ELEC2102
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0 1 0
1 0 1
1 1 1
The most well-known bistable circuits are SR-type bistables. They have two inputs: Set (or S) and
Reset (or R) and two outputs Q and Q (one is the inverse of the other during normal operation). The Set
input forces the main output (Q) to ‘1’ while the Reset forces Q to ‘0’. Three possible implementation
alternatives for SR bistable are presented in Fig. 3-3, while the corresponding truth tables are illustrated by
Table 3-2 and Table 3-3.
Table 3-2
Truth Table for Bistable A Truth Table for Bistable B
S R Qt Qt S R Qt Qt
0 0 Qt-1 t −1 0 0 — —
Q
0 1 0 1 0 1 1 0
1 0 1 0 1 0 0 1
1 1 — — 1 1 Qt-1 t −1
Q
Table 3-3
Truth Table for Bistable C
S R Qt Qt
0 0 Qt-1 t −1
Q
0 1 0 1
1 0 1 0
1 1 — —
The inputs Set and Reset can be “active high” meaning that they act when ‘1’, or “active low” (active
when ‘0’). In Fig. 3-3, the inputs are active high for circuits (a) and (c), and active low in circuit (b).
Both inputs should normally be at a logic level ‘0’ in the case of the NOR circuit in Fig. 3-3 (a).
Changing the input Set to a logic level ‘1’ will force the Q to ‘0’. This signal feeds back to the input of the
lower NOR gate, and Q becomes ‘1’ thereby reinforcing the output of the upper NOR gate. Similarly, if
Reset is forced to ‘1’ instead, then Q will be forced to ‘0’ while Q becomes ‘1’.
Exercise: Explain the operation of the other two bistable circuits in Fig. 3-3.
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The simultaneous activation of both Set and Reset brings the bistable into a paradoxical state where
both Q and Q have the same value. As a result, it is customary to avoid the simultaneous activation of both
Set and Reset and the corresponding combination of inputs is not analysed in the truth tables (see Table 3-2
and Table 3-3). Moreover, the simultaneous deactivation of Set and Reset in the circuits presented in Fig. 3-3
after they were both active generates unpredictable results due to the circuit symmetry. The final state after
such a transition depends on minute differences of propagation delays through the two (or four) gates of the
bistable. So apparently, identical circuits will behave differently due to such small propagation time
differences, which cannot be properly controlled during the manufacturing process.
3.1.1 Latches
Latches are particular cases of bistable circuits that have an additional input (usually named CLOCK,
CLK, ENABLE or EN) that enables and disables the transitions on the outputs. Two possible
implementations of SR latches are presented in Fig. 3-4. The state of such circuits can change only when the
CLK input is ‘1’, while CLK=’0’ “freezes” the internal state and the outputs of the latch.
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3.1.2 Flip-Flops
Flip-flops are edge-triggered bistables. Their outputs change in accordance with the inputs only when
the clock signal changes from ‘0’ to ‘1’ (the rising edge of the clock) or from ‘1’ to ‘0’ (the falling edge of
the clock). Flip-flops are active either on the rising or on the falling edge of the clock but not both of them
simultaneously.
The constant p is the solution of the attached polynomial characteristic equation (3-3), while the
constants K1 and K2 can be determined from the initial and the final conditions of the system as sown in
(3-4). Initially, the capacitor is completely discharged qc=0 while the final charge is qc=C⋅uclk.
1 1
+ R 1p = 0 ⇒ p = − (3-3)
C R 1C
q c (0 ) = K 1 + K 2 = 0 K = −C ⋅ u clk
⇒ 1 (3-4)
q c (+∞) = K 2 = C ⋅ u clk K 2 = C ⋅ u clk
Therefore the solution of the differential equation in (3-1) is
−
t
q c (t ) = C ⋅ u clk ⋅ 1 − e
R 1C
(3-5)
The voltage uNAND applied on the inputs of the NAND gates is approximately
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t t
dq 1 − −
u NAND ≅ R 1 ⋅ i1 = R 1 ⋅ i c = R 1 ⋅ c = R1 ⋅ C ⋅ u clk ⋅ ⋅ e R 1C = u clk ⋅ e R 1C (3-6)
dt R 1C
This is a decreasing exponential. The voltage signal is interpreted as ‘1’ as long as it is larger than VIHmin (the
minimum input voltage guaranteed to be recognised as logic ‘1’) and is interpreted as ‘0’ when the it falls
below VIHmin. Consequently, this formula can be used to calculate the necessary capacitor and resistor in
order to obtain the required validation time. For instance, if the validation time Tv should be less than 1ns
and the logic gates are implemented in the CMOS technology (VILmax=1.5V) then the following calculations
need to be performed:
TV
−
TV 10−9
VIL max = u clk ⋅ e R 1C
⇒ R 1C ≤ = = 8.306 ⋅ 10 −10 s (3-7)
u 5
ln clk ln
VIL max 1.5
Several pairs of values for R1 and C can be used provided that their product complies with the condition
(3-7). If for example C=1pF then R1 has to be less than 830.6Ω.
When the clock voltage changes from +5V to 0V (during the falling edge of the clock) the capacitor
discharges through both R1 and R2 because the diode conducts the current from the ground to the capacitor.
As a result the discharging current is larger and the discharging process is faster than the charging. The
voltage supplied to the NAND gates is the voltage across the diode and it does not surpass -0.7V.
The validation signal can be generated by purely digital means using the circuits in Fig. 3-8, exploiting
the phenomenon of hazard. Thus, the signals x and y at the inputs of the AND gate do not change
simultaneously due to the delays generated by the buffer and the NOT gates. As a result, the AND gate
generates a short logic pulse ‘1’ whose widths is proportional to the number of logic elements used to delay
the signal ‘x’. Consequently, the circuit in Fig. 3-8 (A) generates a narrower validation pulse than the circuit
in Fig. 3-8 (B).
This digital solution is less flexible than the analogue approach previously presented because in this
second situation the validation pulse width is always an integer multiple of one gate delay whereas in the
first case it could have any width (depending on C and R1).
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Fig. 3-8 – Digital validation signal generators with buffer and inverter (A) and only with inverters (B)
Fig. 3-9 – Master-slave SR flip-flops: falling-edge triggered (a) and rising-edge triggered (b)
Fig. 3-10 – SR flip-flop operation (active on the rising edge of the clock)
The most important flip-flops are JK, D (or Data) and T (or Toggle). These flip-flops are derived from
the basic SR flip-flop (Fig. 3-9) in the manner shown in Fig. 3-11. Depending on the inputs of the master and
slave SR latches (active-low or active-high) the resulting flip-flops will have different types of inputs (active-
low or active-high). Thus, two types of truth tables are possible: Table 3-4 refers to flip-flops with active-
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high inputs while Table 3-5 applies to flip-flops with active-low inputs. The active inputs are shaded in
both tables below.
Table 3-4 – JK, D and T flip-flop truth tables (inputs active-high). The active inputs are shaded.
JK flip-flop D flip-flop T flip-flop
J K Q Q D Q Q T Q Q
0 0 Qt-1 Q t −1 0 0 1 0 Qt-1 Q t −1
0 1 0 1 1 1 0 1 Q t −1 Qt-1
1 0 1 0
t −1
1 1 Q Qt-1
Table 3-5 – JK, D and T flip-flop truth tables (inputs active-low). The active inputs are shaded.
JK flip-flop D flip-flop T flip-flop
J K Q Q D Q Q T Q Q
0 0 Q t −1 Qt-1 0 1 0 0 Q t −1 Qt-1
0 1 1 0 1 0 1 1 Qt-1 Q t −1
1 0 0 1
Q t −1
t-1
1 1 Q
IMPORTANT NOTE: The flip-flops with the main inputs (S, R, T, J, K) active high are by far more
popular than the ones with inputs active low. Therefore, Table 3-4 shows the truth-tables used in most
practical cases.
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Flip-flop excitation tables show the inputs necessary to obtain any required changes of the flip-flop
output. There are only four possible output changes: 0→0; 0→1; 1→0; 1→1. These are covered in Table 3-6
where the sign ‘*’ stands for any input (either ‘0’ or ‘1’). Based these tables and using logic gates where
necessary, any flip-flop can be transformed in any other flip-flop. Some of the conversions are illustrated in
Fig. 3-11.
Table 3-6 – Flip-flop excitation tables (inputs active high).
SR flip-flop JK flip-flop
Qt Qt+1 S R Qt Qt+1 J K
0 0 0 * 0 0 0 *
0 1 1 0 0 1 1 *
1 0 0 1 1 0 * 1
1 1 * 0 1 1 * 0
D flip-flop T flip-flop
Qt Qt+1 D Qt Qt+1 T
0 0 0 0 0 0
0 1 1 0 1 1
1 0 0 1 0 1
1 1 1 1 1 0
( )
T Qt , D = Qt ⋅ D + Qt ⋅ D = Qt ⊕ D (3-8)
Table 3-8
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Initial Emulated
Flip-Flop Flip-Flop Inputs
Input
Qt Qt+1 D J K
0 0 0 0 *
0 1 1 1 *
1 0 1 * 1
1 1 0 * 0
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1 1 0 0 0 Beginning
1 1 1 0 0 of the
1 1 1 1 0 second
cycle
The RESET input is essential for the correct operation of a Johnson counter in Fig. 3-25 because the
counter needs to start from one of its correct states. A correct state is one where all the output bits ‘1’ are
neighbours to one-another. A state like “1011” is not a correct state for a Johnson counter. The counter in
Fig. 3-26 does not need a reset input because it automatically converges to its normal operation cycle
regardless of the initial state. This is achieved by means of the feed-back loop that contains the NOR gate
which feeds a new bit ‘1’ into the counter only when all the outputs are simultaneously ‘0’. An example is
presented in Table 3-11.
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Table 3-11
Feed-back bit Out0 Out1 Out2 Out3
0 1 1 0 1 Initial states
0 0 1 1 0
0 0 0 1 1
0 0 0 0 1
1 0 0 0 0
0 1 0 0 0 One normal
0 0 1 0 0 operation
0 0 0 1 0 cycle
0 0 0 0 1
1 0 0 0 0
0 1 0 0 0
Such ring-counters are normally used to control complex devices (as industrial robots, for instance)
where a cyclical task is being performed and the task consists of several steps. Each step is initiated by
activating one output signal (one flip-flop output).
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Table 3-12 –The state table of the Gray counter and the corresponding D inputs of the flip-flops
Q2 Q1 Q0 Q 2t +1 Q1t +1 Q0t +1 D2 D1 D0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 1 0 1 1
0 1 1 0 1 0 0 1 0
0 1 0 1 1 0 1 1 0
1 1 0 1 1 1 1 1 1
1 1 1 1 0 1 1 0 1
1 0 1 1 0 0 1 0 0
1 0 0 0 0 0 0 0 0
Fig. 3-29 – The logic functions underlying the operation of the 3-bit Gray counter
(
D 0 = Q 2 Q1 + Q 2Q1 = Q 2 Q1 + Q 2Q1 = Q 2 Q1 ⋅ Q 2Q1 = (Q 2 + Q1 ) ⋅ Q 2 + Q1 =)
= Q 2 Q 2 + Q 2 Q1 + Q1 Q 2 + Q1 Q1 = Q 2 Q1 + Q1 Q 2 = Q1 ⊕ Q 2
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Table 3-13 – The state table of the Gray counter and the corresponding T or J and K inputs of the flip-flops
Q2 Q1 Q0 Q 2t +1 Q1t +1 Q0t +1 T2 T1 T0 J2 K2 J1 K1 J0 K0
0 0 0 0 0 1 0 0 1 0 * 0 * 1 *
0 0 1 0 1 1 0 1 0 0 * 1 * * 0
0 1 1 0 1 0 0 0 1 0 * * 0 * 1
0 1 0 1 1 0 1 0 0 1 * * 0 0 *
1 1 0 1 1 1 0 0 1 * 0 * 0 1 *
1 1 1 1 0 1 0 1 0 * 0 * 1 * 0
1 0 1 1 0 0 0 0 1 * 0 0 * * 1
1 0 0 0 0 0 1 0 0 * 1 0 * 0 *
3.2.3 Registers
Registers are digital circuit capable to store N bits in the same time where each bit is stored by one
flip-flop. Usually registers are built with D-type flip-flops but other types of flip-flops can also be used.
Depending on the types of the inputs and the outputs, there are four main categories of registers:
• Parallel-In Parallel Out (PIPO)
• Serial-In Serial-Out (SISO)
• Parallel-In Serial-Out (PISO)
• Serial-In Parallel-Out (SIPO)
Combinations of these main types are also possible.
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Fig. 3-35 – 5-bit PISO register with asynchronous input control (load)
Fig. 3-36 – 4- bit register with synchronous parallel and serial inputs and a serial output
Exercise: Modify the circuit in Fig. 3-36 to transform it into a register with both a serial output and four
parallel outputs.
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initial value (a "seed") to start a series of numeric or logical operations to produce a long pattern of
successive results. The main applications of pseudo-random number generators are:
• simulation of complex phenomena (weather, stock exchange etc.)
• testing computer programs
• testing complex digital circuits
• electronic games
• communication systems.
One of simplest digital random generators consists of a shift register and an XOR gate whose inputs
are connected to some of the outputs of the flip-flops in the register. The XOR gate feeds the serial input of
the register while the pseudo-random bit pattern is provided by the serial output of the register. An example
is provided by Fig. 3-37. Notice that the ‘reset’ input of circuit initialises the register with a bit pattern where
not all the values are ‘0’. If they were all ‘0’ then the XOR gate would always generate ‘0’ and no random bit
pattern could be generated. The quality of the circuit is given by the length of the bit-pattern it generates.
This in turn depends on the register length, the number of XOR inputs and the flip-flops they are connected
to. Generally, such a circuit does not enter its normal operation cycle immediately after reset, but it first
visits a few initial states, which are not revisited again during its normal cyclical operation. The first
operation steps of the presented circuit are calculated in Table 3-14.
Exercise: Find the number of initial states after reset and total length of the operation cycle for the random
generator in Fig. 3-37.
Table 3-14 – The first operation steps of the random bit generator in Fig. 3-37
XOR-Out D-Out0 D-Out1 D-Out2 D-Out3 D-Out4 D-Out5
1 0 0 1 1 0 0
0 1 0 0 1 1 0
0 0 1 0 0 1 1
0 0 0 1 0 0 1
1 0 0 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
1 1 1 1 0 0 0
0 1 1 1 1 0 0
1 0 1 1 1 1 0
0 1 0 1 1 1 1
1 0 1 0 1 1 1
1 1 0 1 0 1 1
0 1 1 0 1 0 1
0 0 1 1 0 1 0
1 0 0 1 1 0 1
0 1 0 0 1 1 0
0 0 1 0 0 1 1
0 0 0 1 0 0 1
1 0 0 0 1 0 0
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Message : 6 23 4
Message with checksum : 6 23 4 33
Message with error after transmission : 6 27 4 33
The second byte of the message was corrupted in the above example from 23 to 27 by the communications
channel. However, the receiver can detect this by comparing the transmitted checksum (33) with the
computer checksum of 37 (6 + 27 + 4). If the checksum itself is corrupted, then a correctly transmitted
message might be incorrectly identified as a corrupted one. However, this is a safe-side failure. A dangerous-
side failure occurs where the message and/or checksum are corrupted in a manner that results in a
transmission that is internally consistent. For example:
Message : 6 23 4
Message with checksum : 6 23 4 33
Message after transmission : 8 20 5 33
Unfortunately, this possibility is not completely avoidable and the best that can be done is to minimise its
probability by increasing the amount of information in the checksum (e.g. widening the checksum from one
byte to two bytes). To strengthen the checksum, one could change from an 8-bit register to a 16-bit register
(i.e. sum the bytes mod 65536 instead of mod 256) so as to apparently reduce the probability of failure from
1/256 to 1/65536. While a good idea, it fails in this particular case because the formula used is not
sufficiently "random". With a simple summing formula, each incoming byte affects roughly only one byte of
the summing register no matter how wide it is. For example, in the second example above, the summing
register could be a Megabyte wide, and the error would still go undetected. This problem can only be solved
by replacing the simple summing formula with a more sophisticated formula that causes each incoming byte
to have an effect on the entire checksum register. Thus, at least two aspects are required to form a strong
checksum function:
• WIDTH: A register width wide enough to provide a low a-priori probability of failure (e.g. 32-bits gives
a 1/2^32 chance of failure).
• CHAOS: A formula that gives each input byte the potential to change any number of bits in the register.
Note: The term "checksum" was presumably used to describe early summing formulas, but has now taken on
a more general meaning encompassing more sophisticated algorithms such as the (Cyclical Redundancy
Codes (CRC). The CRC algorithms can be adjusted to satisfy the second condition very well, and can be
configured to operate with a variety of checksum widths.
3.2.4.2.1 The basic principle of CRC
While addition is clearly not strong enough to form an effective checksum, it turns out that division is,
so long as the divisor is about as wide as the checksum register. The basic idea of CRC algorithms is simply
to treat the message as an enormous binary number, to divide it by another fixed binary number, and to make
the remainder from this division the checksum. Upon receipt of the message, the receiver can perform the
same division and compare the remainder with the "checksum" (transmitted remainder).
Example: Suppose the message consisted of the two bytes (the decimal numbers 6 and 23) as in the previous
example. These can be considered to be the hexadecimal number 0617 which can be considered to be the
binary number 0000-0110-0001-0111. Suppose that we use a checksum register one-byte wide and use a
constant divisor of 1001, then the checksum is the remainder after 0000-0110-0001-0111 is divided by 10012
which is 00102. Therefore, the transmitted message would look like this (in hexadecimal): 06172 (where the
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0617 is the message and the 2 is the checksum). The receiver would divide 0617 by 9 and see whether the
remainder was 2.
Although the effect of each bit of the input message on the quotient is not all that significant, the 4-bit
remainder gets kicked about quite a lot during the calculation, and if more bytes were added to the message
(dividend) it's value could change radically again very quickly. This is why division works where addition
doesn't.
While the division scheme described in the previous section is very similar to the check summing
schemes called CRC schemes, the CRC schemes are in fact a bit weirder. The key concept behind the CRC
algorithms is summed up by the word "polynomial". A given CRC algorithm will be said to be using a
particular polynomial, and CRC algorithms in general are said to be operating using polynomial arithmetic.
What does this mean?
Instead of the divisor, dividend (message), quotient, and remainder (as described in the previous
section) being viewed as positive integers, they are viewed as polynomials with binary coefficients. This is
done by treating each number as a bit-string whose bits are the coefficients of a polynomial. For example, the
ordinary number 23 (decimal) is 17 (hex) and 10111 binary and so it corresponds to the polynomial:
Using this technique, the message, and the divisor can be represented as polynomials and we can do
all our arithmetic just as before, except that now it's all cluttered up with Xs. For example, suppose one
wanted to multiply 1101 by 1011. This can be simply done by multiplying the polynomials:
(x^3 + x^2 + x^0)(x^3 + x^1 + x^0)=
=(x^6 + x^4 + x^3 + x^5 + x^3 + x^2 + x^3 + x^1 + x^0)=
= x^6 + x^5 + x^4 + 3*x^3 + x^2 + x^1 + x^0
At this point, to get the right answer, we have to pretend that x is 2 and propagate binary carries from
the 3*x^3 yielding: x^7 + x^3 + x^2 + x^1 + x^0. It's just like ordinary arithmetic except that the base is
abstracted and brought into all the calculations explicitly instead of being there implicitly. So what's the
point?
The point is that IF we pretend that we DON'T know what x is, we CAN'T perform the carries. We
don't know that 3*x^3 is the same as x^4 + x^3 because we don't know that x is 2. In this true polynomial
arithmetic the relationship between all the coefficients is unknown and so the coefficients of each power
effectively become isolated from the others. Coefficients of x^2 are effectively of a different type to
coefficients of x^3, for example. With the coefficients of each power nicely isolated, mathematicians came
up with all sorts of different kinds of polynomial arithmetics simply by changing the rules about how
coefficients work. Of these schemes, one in particular is relevant here, and that is a polynomial arithmetic
where the coefficients are calculated MOD 2 and there is no carry; all coefficients must be either 0 or 1 and
no carries are calculated. This is called "polynomial arithmetic mod 2".
Under the normal arithmetic, the 3*x^3 term was propagated using the carry mechanism using the
knowledge that x=2. Under "polynomial arithmetic mod 2", one doesn’t know what x is, there are no carries,
and all coefficients have to be calculated mod 2. Thus, the previous example becomes:
(x^3 + x^2 + x^0)(x^3 + x^1 + x^0)== x^6 + x^5 + x^4 + x^3 + x^2 + x^1 + x^0
Thus, polynomial arithmetic mod 2 is just binary arithmetic mod 2 with no carries. While polynomials
provide useful mathematical machinery in more analytical approaches to CRC and error-correction
algorithms, for the purposes of exposition they provide no extra insight and some encumbrance and have
been discarded in the remainder of these handout notes in favour of direct manipulation of the arithmetical
binary system with no carry.
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11001010
01010001
Subtraction is identical:
10011011-
11001010
01010001
where:
0-0=0
0-1=1 (wraparound)
1-0=1
1-1=0
In fact, both addition and subtraction in CRC arithmetic is equivalent to the XOR operation, and the
XOR operation is its own inverse. This effectively reduces the operations of the first level of power
(addition, subtraction) to a single operation that is its own inverse. This is a very convenient property of the
arithmetic.
By collapsing of addition and subtraction, the arithmetic discards any notion of magnitude beyond the
power of its highest one bit. While it seems clear that 1010 is greater than 10, it is no longer the case that
1010 can be considered to be greater than 1001. To see this, note that you can get from 1010 to 1001 by both
adding and subtracting the same quantity:
1001 = 1010 + 0011
1001 = 1010 - 0011
This makes nonsense of any notion of order.
Having defined addition, we can move to multiplication and division. Multiplication is absolutely
straightforward, being the sum of the first number, multiplied by the bits of the second, shifted and added in
accordance with the previous rules.
Example:
1101 x 1011
1101
1101
0000.
1101 .
1111111
Division is a little messier as we need to know when "a number goes into another number". To solve
the problem, a so-called “weak” definition of magnitude can be invoked: X is greater than or equal to Y if
and only if the position of the highest 1 bit of X is the same or greater than the position of the highest 1 bit of
Y. Adopting this definition makes the subtraction possible again.
Example:
101101110011 : 1001 = 10100011
1001
100
0000
1001
1001
01
0000
11
0000
110
0000
1100
1001
1011
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1001
101
The issue of divisibility in the polynomial modulo 2 arithmetic is the same as in the normal arithmetic:
one number is dividable by another if the remainder generated by the division is zero. As a consequence of
the mathematical properties of the new arithmetic described, if M and Y are two numbers and M=Z*Y+R (R
is the remainder of the division M/Y) then M+R is dividable by Y.The polynomial division is used to
generate the checksum for the CRC algorithms. A typical CRC algorithm consists of two stages:
• The calculation of the checksum before message transmission. The message is considered a
polynomial and the checksum is calculated as the remainder generated by the division of this
polynomial with a so-called “generator polynomial”. However the message is padded with a few
final zeroes before division. Thus if the message is M=1101001 and the generator polynomial is
100101, then the message becomes M’=110100100000 before division. The number of final zeroes
equals the order of the generator polynomial. In the example above N=5. The calculated checksum
(remainder) is added to the message to ensure that the transmitted block of bits (M’+R) is dividable
by the generator polynomial Y. In the example above the transmitted bits are
M’+R=110100111110.
• The check for errors at the reception. The received block of bits M’ is considered as a number
that is divided by Y using polynomial modulo 2 arithmetic and the remainder is verified. If the
remainder is “0000…000” then the reception is correct. Otherwise, an error has occurred during
transmission.
The CRC algorithm has the advantage that it can be implemented much simpler than normal divisions
of binary numbers. Fig. 3-38 presents a CRC implementation where the generator polynomial is 10100101.
The circuit is constructed only with a PIPO register and three XOR gates.
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