1CY 626 4

PRELIMINARY CY6264

Features
• 55, 70 ns access times
• CMOS for optimum speed/power
• Easy memory expansion with CE1, CE2, and OE fea-
tures
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
Functional Description
The CY6264 is a high-performance CMOS static RAM orga-
nized as 8192 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE1), an active HIGH
chip enable (CE2), and active LOW output enable (OE) and
three-state drivers. Both devices have an automatic pow-
er-down feature (CE1), reducing the power consumption by
8K x 8 Static RAM
over 70% when deselected. The CY6264 is packaged in a
450-mil (300-mil body) SOIC.
An active LOW write enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE1 and WE in-
puts are both LOW and CE2 is HIGH, data on the eight data
input/output pins (I/O0 through I/O7) is written into the memory
location addressed by the address present on the address
pins (A0 through A12). Reading the device is accomplished by
selecting the device and enabling the outputs, CE1 and OE
active LOW, CE2 active HIGH, while WE remains inactive or
HIGH. Under these conditions, the contents of the location ad-
dressed by the information on address pins is present on the
eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to insure alpha immunity.

Logic Block Diagram Pin Configuration

SOIC
Top View

NC 1 28 VCC
A4 2 27 WE
A5 3 26 CE2
I/O0 A6 4 25 A3
A7 5 24 A2
INPUT BUFFER A8 6 23 A1
I/O1 A9 OE
7 22
A10 8 21 A0
A1 A11 9 20 CE1
I/O2 A12 I/O7
10 19
A2 I/O0 I/O6
11 18
A3 I/O3 I/O1 12 17 I/O5
A4 256 x 32 x 8 I/O2 13 16 I/O4
A5 ARRAY GND 14 15 I/O3
A6 I/O4
CY6264-2
A7
A8 I/O5

I/O6

CE1 POWER
CE2 COLUMN DECODER DOWN I/O7
WE
OE

CY6264-1

Selection Guide
CY6264-55 CY6264-70

Maximum Access Time (ns) 55 70

Maximum Operating Current (mA) 100 100
Maximum Standby Current (mA) 20/15 20/15
Shaded area contains advanced information.

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 1994 – Revised June 1996
 PRELIMINARY CY6264

Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage .......................................... >2001V
(Above which the useful life may be impaired. For user guide- (per MIL-STD-883, Method 3015)
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C Latch-Up Current .................................................... >200 mA

Ambient Temperature with

Power Applied............................................. –55°C to +125°C Operating Range
Supply Voltage to Ground Potential ............... –0.5V to +7.0V Ambient
Range Temperature VCC
DC Voltage Applied to Outputs
in High Z State[1] ............................................ –0.5V to +7.0V Commercial 0°C to +70°C 5V ± 10%
DC Input Voltage[1]......................................... –0.5V to +7.0V

Electrical Characteristics Over the Operating Range

6264-55 6264-70
Parameter Description Test Conditions Min. Max. Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 V
VIH Input HIGH Voltage 2.2 VCC 2.2 VCC V
VIL Input LOW Voltage[1] –0.5 0.8 –0.5 0.8 V
IIX Input Load Current GND < VI < VCC –5 +5 –5 +5 µA
IOZ Output Leakage GND < VI < VCC, –5 +5 –5 +5 µA
Current Output Disabled
IOS Output Short VCC = Max., –300 –300 mA
Circuit Current[2] VOUT = GND
ICC VCC Operating VCC = Max., 100 100 mA
Supply Current IOUT = 0 mA
ISB1 Automatic CE1 Max. VCC, CE1 > VIH, 20 20 mA
Power–Down Current Min. Duty Cycle=100%
ISB2 Automatic CE1 Max. VCC, CE1 > VCC – 0.3V, 15 15 mA
Power–Down Current VIN > VCC – 0.3V or VIN < 0.3V
Shaded area contains advanced information.

Capacitance[3]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz, 7 pF
COUT Output Capacitance VCC = 5.0V 7 pF
Notes:
1. Minimum voltage is equal to -3.0V for pulse durations less than 30 ns.
2. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
3. Tested initially and after any design or process changes that may affect these parameters.

AC Test Loads and Waveforms

R1 481Ω R1 481Ω
5V 5V
OUTPUT OUTPUT ALL INPUT PULSES
3.0V 90%
90%
30 pF R2 5 pF R2 10% 10%
255Ω 255Ω GND
INCLUDING INCLUDING
JIG AND JIG AND < 5 ns < 5 ns
SCOPE SCOPE CY6264-3 CY6264-4
(a) (b)
Equivalent to: THÉVENIN EQUIVALENT

167Ω
OUTPUT 1.73V

2
 PRELIMINARY CY6264

Switching Characteristics Over the Operating Range[4]

6264-55 6264-70
Parameter Description Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time 55 70 ns
tAA Address to Data Valid 55 70 ns
tOHA Data Hold from Address Change 5 5 ns
tACE1 CE1 LOW to Data Valid 55 70 ns
tACE2 CE2 HIGH to Data Valid 40 70 ns
tDOE OE LOW to Data Valid 25 35 ns
tLZOE OE LOW to Low Z 3 5 ns
tHZOE OE HIGH to High Z[5] 20 30 ns
tLZCE1 CE1 LOW to Low Z[6] 5 5 ns
tLZCE2 CE2 HIGH to Low Z 3 5 ns
tHZCE CE1 HIGH to High Z[5, 6] 20 30 ns
CE2 LOW to High Z
tPU CE1 LOW to Power-Up 0 0 ns
tPD CE1 HIGH to Power-Down 25 30 ns
WRITE CYCLE[7]
tWC Write Cycle Time 50 70 ns
tSCE1 CE1 LOW to Write End 40 60 ns
tSCE2 CE2 HIGH to Write End 30 50 ns
tAW Address Set-Up to Write End 40 55 ns
tHA Address Hold from Write End 0 0 ns
tSA Address Set-Up to Write Start 0 0 ns
tPWE WE Pulse Width 25 40 ns
tSD Data Set-Up to Write End 25 35 ns
tHD Data Hold from Write End 0 0 ns
tHZWE WE LOW to High Z[5] 20 30 ns
tLZWE WE HIGH to Low Z 5 5 ns
Shaded area contains advanced information.
Notes:
4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/I OH and 30-pF load capacitance.
5. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device.
7. The internal write time of the memory is defined by the overlap of CE 1 LOW, CE2 HIGH, and WE LOW. Both signals must be LOW to initiate a write and either
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.

3
 PRELIMINARY CY6264

Switching Waveforms
Read Cycle No.1[8, 9]
tRC

ADDRESS

tAA
tOHA

DATA OUT PREVIOUS DATA VALID DATA VALID

CY6264-5

Read Cycle No. 2 [10, 11]

CE1 tRC

CE2 tACE
OE
OE

tDOE tHZOE
tHZCE
tLZOE HIGH
HIGH IMPEDANCE IMPEDANCE
DATA OUT DATA VALID
tLZCE
tPD
tPU
VCC ICC
SUPPLY 50% 50%
CURRENT ISB
CY6264-6

Write Cycle No. 1 (WE Controlled)[9, 11]

tWC

ADDRESS

tSCE1
CE1

CE2
tSCE2

OE
tAW tHA
tSA tPWE
WE

tSD tHD

DATA IN DATAIN VALID

tHZWE tLZWE
HIGH IMPEDANCE
DATA I/O DATA UNDEFINED
CY6264-7
Notes:
8. Device is continuously selected. OE, CE = V IL. CE 2 = VIH.
9. Address valid prior to or coincident with CE transition LOW.
10. WE is HIGH for read cycle.
11. Data I/O is High Z if OE = VIH, CE1 = V IH, or WE = V IL.

4
 PRELIMINARY CY6264

Switching Waveforms (continued)

Write Cycle No. 2 (CE Controlled) [9, 11, 12]
tWC

ADDRESS

CE1 tSCE1

tSA

CE2 tSCE2
tAW tHA
tPWE
WE
tSD tHD

DATA IN DATAIN VALID

tHZWE
HIGH IMPEDANCE
DATA I/O DATA UNDEFINED
CY6264-8

Note:
12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.

Typical DC and AC Characteristics

NORMALIZED SUPPLY CURRENT NORMALIZED SUPPLY CURRENT OUTPUT SOURCE CURRENT
vs. SUPPLY VOLTAGE vs. AMBIENT TEMPERATURE vs. OUTPUT VOLTAGE
1.4 1.2 120
1.2 1.0 100
ICC ICC
1.0
0.8 80
0.8
VCC =5.0V
0.6 60 TA =25°C
0.6
0.4 VCC =5.0V 40
0.4
VIN =5.0V
0.2 ISB 0.2 ISB 20

0.0 0.0 0
4.0 4.5 5.0 5.5 6.0 −55 25 125 0.0 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (°C) OUTPUT VOLTAGE (V)

NORMALIZED ACCESS TIME NORMALIZED ACCESS TIME OUTPUT SINK CURRENT

vs. SUPPLY VOLTAGE vs. AMBIENT TEMPERATURE vs. OUTPUT VOLTAGE
1.4 1.6 140
120
1.3 1.4
100
1.2 VCC =5.0V
1.2 80 TA =25°C
1.1
TA =25°C 60
1.0
1.0 VCC =5.0V
40
0.8
0.9 20

0.8 0.6 0
4.0 4.5 5.0 5.5 6.0 −55 25 125 0.0 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (°C) OUTPUT VOLTAGE (V)

5
 PRELIMINARY CY6264

Typical DC and AC Characteristics (continued)

TYPICAL POWER-ON CURRENT TYPICAL ACCESS TIME CHANGE

vs. SUPPLY VOLTAGE vs. OUTPUT LOADING NORMALIZED ICC vs. CYCLE TIME
3.0 30.0 1.25
VCC =5.0V
2.5 25.0 TA =25°C
VCC =0.5V
2.0 20.0 1.00

1.5 15.0

1.0 10.0 0.75

VCC =4.5V
TA =25°C
0.5 5.0

0.0 0.0 0.50

0.0 1.0 2.0 3.0 4.0 5.0 0 200 400 600 800 1000 10 20 30 40
SUPPLY VOLTAGE(V) CAPACITANCE(pF) CYCLE FREQUENCY (MHz)

Truth Table
CE1 CE2 WE OE Input/Output Mode
H X X X High Z Deselect/Power-Down
X L X X High Z Deselect
L H H L Data Out Read
L H L X Data In Write
L H H H High Z Deselect

Address Designators
Address Address Pin
Name Function Number
A4 X3 2
A5 X4 3
A6 X5 4
A7 X6 5
A8 X7 6
A9 Y1 7
A10 Y4 8
A11 Y3 9
A12 Y0 10
A0 Y2 21
A1 X0 23
A2 X1 24
A3 X2 25

6
 PRELIMINARY CY6264

Ordering Information
Speed Package Operating
(ns) Ordering Code Name Package Type Range
55 CY6264-55SC S23 28-Lead 330-Mil SOIC[13] Commercial
[13]
70 CY6264-70SC S23 28-Lead 330-Mil SOIC Commercial
55 CY6264-55SNC S22 28-Lead 300-Mil SOIC Commercial
70 CY6264-70SNC S22 28-Lead 300-Mil SOIC Commercial
Shaded area contains advanced information.
Note:
13. Not recommended for new designs.
Document #: 38-00425-A

Package Diagrams

28-Lead 450-Mil (300-Mil Body Width) SOIC S22

7
 PRELIMINARY CY6264

Package Diagrams (continued)

28-Lead (330-Mil) SOIC S23

© Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.