Professional Documents
Culture Documents
10/20/2010
for
Sangmin, Sangmin Bae DFX Group IDC, System LSI, Samsung Electronics Co, Ltd Co Samsung Property
Contents
Introduction
Environments and Scopes
Technical Items
Integration complexity MBIST design consideration Design flow consideration Repair and ECC
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Introduction
Status on eMemory Testing Driver
Complex advanced design flow with limited TAT Complex,
Advanced lo po e Ad anced low-power design techniq e technique Design reuse : Heterogeneous IP integration
Performance gain and yield goal is more challenging than before Reliability, test escape reduction Bit-cell engineering requires efficient channel for si. analysis
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Introduction
Scope and limitation on eMemory Testing Typically, memory is not fully controllable and we have fewer knobs than logic dft (scan) technique technique.
Memory BIST y
MBIST is classical and well-defined technique, but most of eMemory design and test issues are tightly coupled with DFT logic ( g (MBIST). So, re-visiting of MBIST is still occurred ) , g Not easy to maintain current through-put within the previous DFT resource (test cost, H/W area) cost
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Integration Complexity
Difficulty on SRAM Tests
Layout is more crucial compare with logic std. cell Each 6 tr. has very strong relationship : y g p Trade-off exists between area, performance, yield Bit-cell array and peri. circuit is controlled by self-timed logic SRAM configuration widely varies on their usages Most SRAM are deeply embedded in a chip MBIST just do functional test on SRAMs
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Integration Complexity
Who is DFT player?
Example : test lvcc problem
Vector and screening condition
Test engr IP or package engr SoC DFT designr FE/BE eng r engr
IO + package spec. full-chip full chip level DFT planning power-clock network
Design methodology + Sign-off rules
MBIST engr
SRAM core 6T bit-cell w/ SNM, SNM DNM + peri. design w/ self-timing margin
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Integration Complexity
Memory BIST Limitation
Typically, MBIST is implemented on ASIC flow Test is based on functional test Without memory changes, very difficult to obtain useful knobs on test Example : Controlling clock skew between multi-port memories Each type could requires extra implementation overhead Sacrifice parallelism for area reduction Poor resolution Pattern development difficulties p p / p ROI perspective : Trade-off b/w implementation efforts and TAT
BIST A
BIST B
BIST
BIST
direct control clock
mem. mem.
Port A Port B 0 1 1 0 0 1
mem.
1 0
A Type
B Type
C Type
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Integration Complexity
MBIST complexity Increased memory counts
Hierarchical/multi-step generation and insertion capacity Redundancy strategy
mbist
Solution approaches
JTAG + IEEE1500 interface with tricky interface blocks MBIST insertion variation GL vs. RTL insertion Hierarchical test-bus
mbist
Block A
IP i/f mbist
mbist
mbist
Block C
mbist
IP i/f
Block B
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MBIST generator : easily adapted and deployed in industry Script or GUI based input form : memory and MBIST lib. format Based on configurable and parameterized template ased o co gu ab e a d pa a e e ed e p a e IDE fasten DK iteration : planning, insertion, verification Several consideration : mainly automation and flow issues Customization can not be avoidable Different DFT budgets and targets by different customer Clock scheme, and scan mode isolation scheme Seamless automation flow requires continuous efforts Hard to be properly hidden during implementation flow Timing closure, STA, Verification closure STA Samsung Property
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Initial statistical analysis Extract exact fail bit-map Parametric analysis using memory operation mode MBIST logic fails Typically, detected by design verification review and work around work-around can be exists
Test escape
Re producing Re-producing fail on DFT@ATE test is technical goal Main barrier : lacks of fail modeling and MBIST flexibilities Diagnosis time is most important
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Programmable MBIST
Programmable MBIST Flexibility depends on structures
FSM-based FSM based ALPG like (micro-code based) Extension of general micro-controller ISA w/ custom module
Needs of programmable MBIST
Control of complex memory IP : eDRAM, KGD(SiP, TSV) Si diagnosis repair analysis : diagnostic pattern, repair analysis Si. diagnosis, pattern
Pattern level programmability seems to be not sufficient
ALPG ( i i memory ATE) approaches i popular (mini. h is l Pattern development costs Well defined flexible ISA
ATE or on-chip control interface is one of issues
JTAG or AMBA-bus based Vector and simulation flow is required Samsung Property
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1D Redundancy Red. Type # of Red. BIRA Single (Row / Column / IO) N Simple
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JTAG
Wrapper
Wrapper
Wrapper
JTAG
BIST
Fuse Related Controller
SRAM
...
SRAM
SRAM
Repair Address
Repair Address
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Memory Instance
Memory Instance
F/F
normal memory bus
Memory Instance e
Memory Instance
F/F
BIST vs. Memory Interconnection
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Both, spec. and run-time level required , p q Should consider BIST generation, pattern, repair
Average vs. peak power based Clock skew and timing dependency P&R floor-planning back-annotation Memory operations
Run #2
Run u #3
Run #4
Capacities
MILP or graph-based solver Graph-based : bin-packing problem Graph based bin packing
Test Time
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Bit-cell related Reliability and manufacturability issues NBTI, Hot-carrier, TDDB Memory related Multi port memory related Multi-port Parametric diagnosis structure Memory test-assist function support g g / Design-assist function using BIST/BIRA resource BIST-BIRA related BISR(self-repair) Repair analysis algorithm fuse-compress and repair-bus structure BIST/BIRA planning and scheduling Shared BIST or hierarchical BIST architecture BIST/BIRA planning w/ design constraints TSV, SiP memory test support
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Summary
DFT for Memories Memory BIST for eSRAM
On-product diagnostic features in mass volume On product Fluent and flexible design flow
Memory BIST for SiP, TSV
Technical requirements on current MBIST Well-designed memory test-bus g y Matured programmable MBIST for SiP, TSV Latest full-chip DFT architecture compliance
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