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High-Power-Factor Single-Stage LCC Resonant Inverter for Liquid Crystal Display Backlight
Zhe Li, Chun-Yoon Park, Jung-Min Kwon, Member, IEEE, and Bong-Hwan Kwon, Member, IEEE
AbstractThe aim of this paper is to propose a high-powerfactor (HPF) single-stage inductor-capacitor-capacitor (LCC) resonant inverter for liquid crystal display (LCD) backlight. A half-bridge LCC resonant inverter shares switches with a powerfactor-correction circuit to form single stage. The proposed singlestage LCC resonant inverter can achieve almost unity power factor and ripple-free input current by using a coupled inductor, and can also realize zero-voltage-switching by operating the switches above the resonant frequency. Thus, the proposed single-stage inverter not only provides HPF to the utility line, but also achieves circuit simplicity, low cost, and high reliability. Experimental results on a 32-in LCD backlight are obtained to show the performance of the proposed inverter. Index TermsPower-factor-correction (PFC), resonant inverter, single-stage.

I. I NTRODUCTION ITH THE development of at panel display technology, large liquid crystal display (LCD) panels have become more and more common. As the LCD panels are transmissive displays, they need backlight illuminations. To date, cold cathode uorescent lamps (CCFLs) have been widely used as the backlight source for large LCD panels to provide the backlight illuminations because they meet the demands required for display performance, size, and efciency satisfactorily. They are considered to be one of the best backlight sources when considering factors such as cost, efciency, and uniformity ratio of illumination [1][3]. Like other gas discharge lamps, CCFLs also have a negative impedance characteristic in the desired operation region [4], and the preferred method to drive CCFLs is a sinusoidal current with minimal ripple components. Inductor-capacitor-capacitor (LCC) resonant inverters have been considered to be quite attractive for this application because they not only establish the required high start-up voltage during the ignition process, but also maintain a steady-state rated sine-wave current for the CCFLs. They also have other advantages such as circuit simplicity, low cost, potential high efciency, and so on [5][9].

Manuscript received November 22, 2009; revised February 10, 2010; accepted March 26, 2010. Date of publication April 29, 2010; date of current version February 11, 2011. Z. Li, C.-Y. Park, and B.-H. Kwon are with the Department of Electronic and Electrical Engineering, Pohang University of Science and Technology, Pohang 790-784, Korea (e-mail: lizhe@postech.ac.kr; chunyoon@postech. ac.kr; bhkwon@postech.ac.kr). J.-M. Kwon is with Samsung Electronics Incorporated, Yongyin 446-712, Korea (e-mail: jmkwon@postech.ac.kr). Digital Object Identier 10.1109/TIE.2010.2048294

Without a power-factor-correction (PFC) circuit, the current drawn by the inverter from the utility line will contain signicant harmonic components and therefore, the inverter will operate at a poor power factor. By adding active PFC circuits, line current harmonics can be reduced effectively and high power factor is achieved, which means that the utility line can be utilized more efciently [10][12]. Also, the inverter effectively consists of two cascaded power conversion stages, where the rst stage is a boost converter operating as a preregulator and the second stage is a resonant inverter that provides the regulated high frequency voltage. The input current is controlled to follow the sinusoidal waveform of the input voltage to provide high-power-factor (HPF) to the utility line [11][16]. The advantage of this two-power-processingstage approach is that it is easy to optimize each stage, but the disadvantages are, since it has two-power-processing-stage topology, it reduces the inverter reliability, decreases the efciency, and increases the nal cost because more components are needed in this approach. In order to avoid these problems, inverters based on single-stage designs are considered to be desirable and several single-stage inverters have been proposed [17][26]. These kinds of inverters combine the PFC stage and the inverter stage by sharing switches to form single stage. Although the previous single-stage inverters have only onepower-processing-stage, they need an extra diode to accomplish the boost operation of the PFC stage. A smaller number of devices are more desirable in terms of efciency, reliability, and cost. The boost converter or its modied topologies can achieve HPF with simple controls, but their output voltages would need to be considerably higher than the peak amplitude of the line voltage. This increases the voltage stresses on power semiconductor devices. In this paper, an HPF single-stage LCC resonant inverter for LCD backlight is proposed, as shown in Fig. 1. The proposed inverter combines the PFC stage and the half-bridge LCC resonant inverter stage by sharing switches to form single stage. The proposed single-stage LCC resonant inverter achieves almost unity power factor and ripple-free input current by using a coupled inductor without increasing the voltage stress of the power semiconductor devices, and since the switches of the half-bridge LCC resonant inverter are driven above the resonant frequency complementarily with 50% duty ratio, it realizes zero-voltage-switching (ZVS) and reduces the switching losses. Thus, the proposed single-stage inverter not only provides HPF to the utility line, but also achieves circuit simplicity, low cost, and high reliability compared to the conventional HPF inverters. Experimental results on a 32-in LCD backlight are obtained to show the performance of the proposed inverter.

0278-0046/$26.00 2010 IEEE

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Fig. 1.

Proposed HPF single-stage LCC resonant inverter.

II. A NALYSIS OF PFC S TAGE Fig. 2 shows the proposed PFC circuit. iCf 1 and iCf 2 are the currents owing through the lter capacitors Cf 1 and Cf 2 (Cf 1 = Cf 2 = Cf ), respectively. The current owing through the inductor L is iL . The transformer-type coupled inductor Tc is modeled as an ideal transformer, which has a turn ratio of 1 : 1. The magnetizing inductance Lmc is large enough to maintain a constant current imc during a switching period. The steady-state operation of the PFC circuit in one switching period Ts includes eight modes, as shown in Fig. 3, and the theoretical waveforms are shown in Fig. 4. Switches S1 and S2 are operated symmetrically with the duty ratio equaling to 0.5. To illustrate the steady-state operation, it is assumed that all the components are ideal. The ripple components of the dc-link voltage Vd are negligible because the dc-link capacitor Cd has a large value. It is assumed that the supply voltage vi is constant during the switching period. Then, the capacitor current iCf 1 becomes dvCf 1 d (vi vCf 2 ) = Cf 1 = Cf 1 dt dt = Cf 1 dvCf 2 = iCf 2 . dt (1)

Fig. 2. Proposed PFC circuit.

Thus, the inductor current iL and the transition interval Tt are given by Tt = 2CS Vd IL (2) (3)

iCf 1

iL (t) = IL .

Therefore, the same amount of currents ow through each capacitor. Since iCf 1 = iCf 2 + iL , iCf 1 = 0.5iL . The ripple components of the lter capacitor voltages vCf 1 and vCf 2 are negligible because the lter capacitors Cf 1 and Cf 2 have large values. Thus, vCf 1 and vCf 2 are considered to be constant during the switching period Ts , and as the duty ratio equals 0.5, vCf 1 = vCf 2 = 0.5vi . CS1 and CS2 (CS1 = CS2 = CS ) are the parallel capacitors of switches S1 and S2 , respectively. Prior to Mode 1, the magnetizing inductor current imc becomes IL , and the inductor current iL ows with the positive peak value IL through D4 , L, and S2 . Mode 1 [t0 , t1 ]: At t0 , the lower switch S2 is turned off. Then, the inductor current iL starts to discharge CS1 and charge CS2 . The voltage vS1 across the upper switch S1 decreases and the voltage vS2 across the lower switch S2 increases.

Since the capacitors CS1 and CS2 in parallel with the switches S1 and S2 have small values, the transition interval Tt is negligible and the inductor current iL has a constant value. Mode 2 [t1 , t2 ]: At t1 , the voltage vS1 across the upper switch S1 becomes zero. Then, the upper diode DS1 and the diode D1 are turned on. Since vCf 1 = vL + vT c = 0.5vi and vCf 2 = vL + vT c + Vd = 0.5vi , the voltage vT c across the coupled inductor Tc and the voltage vL across the inductor L are given by vT c (t) = V d vi 2 Vd . 2 (4) (5)

vL = vCf 1 + vT c =

Then, the inductor current iL decreases linearly as follows: iL (t) = IL + vT c vCf 1 Vd (t t1 ) = IL (t t1 ) L 2L (6)

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Fig. 3. Operating modes of PFC stage.

where IL is the peak value of iL during one switching period. Since i2 = iL + i1 + imc , i1 = i2 , and imc = IL , the secondary current i2 of the coupled inductor Tc is given by i2 (t) = iL + imc Vd = IL (t t1 ). 2 4L (7)

Mode 3 [t2 , t3 ]: At t2 , the zero-voltage turn-on of the upper switch S1 is achieved because the current has already owed through the body diode DS1 before the upper switch S1 is turned on. When the upper switch S1 is turned on, S1 takes over

the current owing through DS1 . To guarantee ZVS at turnon, the gate signal should be applied to S1 before the current changes its direction. The inductor current iL and the current i2 decrease linearly as in Mode 2, and approach IL and zero, respectively at the end of Mode 3. Mode 4 [t3 , t4 ]: At t3 , the current i2 arrives at zero and the diode D4 is turned off. Then, the inductor current is clamped at IL . Because the magnetizing inductance Lmc of the coupled inductor Tc is much greater than that of the inductor L, the voltage across the inductor L is considered to be zero and the voltage vT c is xed to 0.5vi .

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Mode 7 [t6 , t7 ]: At t6 , the lower switch S2 is turned on. Zero-voltage turn-on of the lower switch S2 is achieved in a similar way that is described in Mode 3. The inductor current iL and the current i2 increase linearly as per Mode 6, and approach IL at the end of Mode 7. Mode 8 [t7 , t8 ]: At t7 , the primary current i1 arrives at IL and the diode D1 is turned off. Then, the inductor current iL and the current i2 are both clamped at IL . This mode ends one period Ts of the switching frequency fs . Referring to the voltage waveforms of vL and vT c shown in Fig. 4, the volt-second balance law gives the following equations: Vd Vd Tc1 = Tc2 2 2 (Vd vi ) vi T s Tc1 = Tc1 . 2 2 2 (12) (13)

Equations (12) and (13) give the current transition time as follows: Tc = Tc1 = Tc2 = vi T s . 2Vd (14)

From Mode 2 and Mode 3, the peak current IL is given by IL = 1 Vd Tc1 = vi . 4L 8Lfs (15)

The input voltage vi of the inverter is vi = Vm sin t

Fig. 4. Theoretical waveforms of PFC circuit.

(16)

Mode 5 [t4 , t5 ]: At t4 , the upper switch S1 is turned off. Then, the inductor current iL starts to charge CS1 and discharge CS2 . The voltage vS1 across the upper switch S1 increases, and the voltage vS2 across the lower switch S2 decreases. The transition interval Tt is the same as in Mode 1. The diode D4 is turned on at the end of Mode 5. Mode 6 [t5 , t6 ]: At t5 , the voltage vS2 across the lower switch S2 becomes zero. Then, the lower diode DS2 is turned on. Since vCf 1 = vL + vT c + Vd and vCf 2 = vL + vT c , the voltage vT c across the coupled inductor Tc and the voltage vL across the inductor L are given by V d vi vT c (t) = 2 vL = vCf 2 vT c = Vd . 2 (8) (9)

where Vm and are the peak amplitude and angular frequency, respectively. From Kirchoffs current law and (2), ii = iCf 1 + i1 = iCf 2 + i2 = 0.5(i1 + i2 ) and imc = IL . Then, the input current ii is given by ii = 1 imc = Vm sin t. 2 16Lfs (17)

Thus, the input current does not contain any high-frequency harmonics. The real input power Pi is determined as

1 Pi =
0

vi ii d(t) =

2 Vm . 32Lfs

(18)

From (16)(18), the power factor P F is given by Pi PF = = vi,rms ii,rms

2 Vm 32Lfs Vm V m 2 16 2Lfs

= 1.

(19)

Then, the inductor current iL increases linearly as follows: iL (t) = IL + vCf 2 vT c Vd (t t5 ) = IL + (t t5 ). L 2L (10)

Thus, the proposed PFC circuit gives unity power factor in theory. From (18), the inductor L for unity power factor is designed as follows: L<
2 Vm,min 32fs Pi,max

Since i2 = iL + i1 + imc , i1 = i2 , and imc = IL , the secondary current i2 of the coupled inductor Tc is given by i2 (t) = Vd iL + imc = (t t5 ). 2 4L (11)

(20)

where Pi,max is the maximum input power and Vm,min is the peak amplitude of the minimum input voltage.

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III. A NALYSIS OF H ALF -B RIDGE LCC R ESONANT I NVERTER The circuit of the half-bridge LCC resonant inverter is shown in Fig. 5(a). It is composed of two alternative switches S1 and S2 , series-resonant inductor Lr , dc-blocking capacitor Cb , parallel-resonant capacitor Cp , series-resonant capacitor Cs , and CCFLs, which are replaced with equivalent resistance Rlamp . The circuit is also accompanied by a step-up transformer T whose turn ratio is 1 : N . By transferring the secondary side of the transformer T to the primary side, the equivalent circuit can be drawn, as shown in Fig. 5(b), where the series-resonant inductor Lr , the parallel-resonant capacitor Cp , the magnetizing inductance Lm of T , and the reected secondary impedance of T comprise the resonant tank. In order to simplify the circuit model, the parasitic components are neglected. Fig. 3(c) shows the simplied circuit of Fig. 3(b), where Leq = Lr Lm . Lr + Lm (21)

Before the startup of the CCFLs, the equivalent resistance of the CCFLs is so high that it can be considered an open circuit. Then, the series loaded quality factor given by Qs = N Leq /Cs Rlamp (22)

is almost zero during the startup. So, the circuit performs as a parallel-resonant inverter under the preionized condition. As the parallel-resonant inverter has a voltage-boost characteristic, it provides the required high start-up voltage to re the CCFLs. After the ignition, the lamp resistance becomes much smaller. Then, the parallel resonance disappears due to the small parallel loaded quality factor given by Qp = Rlamp N2 Cp . Leq (23)
Fig. 5. (a) Half-bridge LCC resonant inverter. (b) Equivalent circuit of halfbridge LCC resonant inverter. (c) Simplied circuit.

Then, the LCC resonant inverter works as a series-resonant inverter, and since the switching frequency fs is greater than the series-resonant frequency given by f0 = 1 N 2 Cs Leq (24)

the load appears as if being driven by a current source. So, the LCC resonant inverter provides the necessary high startup voltage and drives the CCFLs with a sine-wave current as a current source after the ignition. The steady-state operation of the half-bridge LCC resonant inverter during one switching period Ts includes four modes and the theoretical waveforms are shown in Fig. 6. The switches are driven complementarily with 50% duty ratio, and in order to illustrate the steady-state operation, it is assumed that all the components are ideal. Prior to Mode 1, the upper switch S1 is turned on and the lower switch S2 is turned off, and the current ows through the upper switch S1 .

Mode 1 [t0 , t1 ]: At t0 , the upper switch S1 is turned off and the current ir begins to charge CS1 and discharge CS2 . As a result, the voltage vS1 across the upper switch S1 increases, and the voltage vS2 across the lower switch S2 decreases. When the voltage across the body diode DS2 of the lower switch S2 decreases to zero, it is turned on and it starts to conduct the current ir . Since the output capacitors CS1 and CS2 have small values, the transition interval is negligible. Mode 2 [t1 , t2 ]: At t1 , the zero-voltage turn-on of the lower switch S2 is achieved because the current has already owed through the body diode DS2 before the lower switch S2 is turned on. Then, the lower switch S2 takes over the current owing through DS2 and the current ir decreases resonantly. With the switching frequency fs greater than the resonant frequency fo , the gate signal is applied to the lower switch S2 before the current changes its direction and the lower switch S2 achieves ZVS.

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Fig. 6.

Theoretical waveforms of half-bridge LCC resonant inverter.

Fig. 8. Waveforms of PFC circuit. (a) Coupled inductor currents and switch voltage. (b) Inductor current, input current, and switch voltage.

Fig. 7.

Waveforms of input voltage and input current.

Mode 3 [t2 , t3 ]: At t2 , the lower switch S2 is turned off and the current owing through it begins to charge CS2 and discharge CS1 . As a result, the voltage vS1 decreases and the voltage vS2 increases. When the voltage across the body diode DS1 of the upper switch S1 decreases to zero, it starts to conduct the current ir . Mode 4 [t3 , t4 ]: At t3 , the zero-voltage turn-on of the upper switch S1 is achieved similarly as in Mode 2. Then, the upper switch S1 takes over the current owing through DS1 and the current ir increases resonantly. This is the completion of one full conversion cycle, and both switches of the half-bridge LCC resonant inverter realize ZVS and reduce the switching losses.

Fig. 9. Waveforms of current and voltage of switch S1 .

IV. E XPERIMENTAL R ESULTS The hardware circuit of the proposed inverter in Fig. 1 for a 32-in LCD backlight with 12 CCFLs connected in parallel

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bridge LCC resonant inverter. The current iS1 owing through the upper switch S1 has already owed through the body diode DS1 before it is turned on. Thus, the power switches realize ZVS and the experimental waveforms are identical with the theoretical analysis. Fig. 10 shows the power factor and input power against the switching frequency. Both the power factor and input power decrease as the switching frequency increases. V. C ONCLUSION An HPF single-stage LCC resonant inverter for LCD backlight has been proposed. The proposed inverter combines the PFC stage and the inverter stage by sharing switches of the inverter to form single stage. The proposed single-stage LCC resonant inverter can achieve almost unity power factor and ripple-free input current by using a coupled inductor without increasing the voltage stress of the power semiconductor devices, and the switches of the inverter realize ZVS to reduce the switching losses. Thus, the proposed inverter not only provides HPF, but also achieves circuit simplicity, low cost, and high reliability. R EFERENCES
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Fig. 10. Measured power factor and input power. (a) Power factor versus switching frequency. (b) Input power versus switching frequency.

was implemented to verify the theoretical analysis. The size of the transformer-type coupled inductor was 12 mm 29 mm 29 mm, with tight coupling and the magnetizing inductance Lmc = 1 mH. The turn ratio of the step-up transformer T was 20 : 175 with the magnetizing inductance Lm = 1.45 mH. The proposed inverter was tested at 220 Vrms input voltage and the switching frequency fs = 80 kHz with 50% duty ratio. For unity power factor, (20) gives L < 315 H, and L = 300 H was selected. Other parameters of the inverter used for the experiment were as follows: Lr = 430 H Cf = 0.1 F Cd = 560 F Cb = 1 F Cp = 6.8 nF Cs = 264 pF.

Thus, (24) gives the resonant frequency fo = 62 kHz. The rate current of a CCFL used in this experiment was 14 A, the voltage was 870 Vrms , and the steady-state resistance was 88 k. The maximum input power was 120 W and the efciency of the proposed inverter could be as high as 88%. Experimental waveforms of the input voltage vi and the input current ii are shown in Fig. 7. The input current is ripplefree and the measured power factor is 0.998, which is almost unity. Fig. 8 shows the waveforms of the PFC circuit. We can see that the experimental current waveforms agree with the theoretical waveforms. Fig. 9 shows waveforms of the half-

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[16] J. M. Kwon, W. Y. Choi, H. L. Do, and B. H. Kwon, Singlestage half-bridge converter using a coupled-inductor, Proc. Inst. Elect. Eng.Electr. Power Appl., vol. 152, no. 3, pp. 748756, May 2005. [17] R. O. Brioschi and J. L. F. Vieira, High-power-factor electronic ballast with constant dc link voltage, IEEE Trans. Power Electron., vol. 13, no. 6, pp. 10301037, Nov. 1998. [18] M. A. C, D. S. L. Simonetti, and J. L. F. Vieira, High-power-factor electronic ballast based on a single power processing stage, IEEE Trans. Ind. Electron., vol. 47, no. 4, pp. 809820, Aug. 2000. [19] K. Jirasereeamornkul, M. K. Kazimierczuk, and K. Chamnongthai, Single-stage electronic ballast with class-E rectier as power-factor corrector, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 1, pp. 139 148, Jan. 2006. [20] C. H. Lin, Digital-dimming controller with current spikes elimination technique for LCD backlight electronic ballast, IEEE Trans. Ind. Electron., vol. 53, no. 6, pp. 18811888, Dec. 2006. [21] T. B. Marchesan, M. A. Dalla-Costa, J. M. Alonso, and R. N. do Prado, Integrated ZetaFlyback electronic ballast to supply high-intensity discharge lamps, IEEE Trans. Ind. Electron., vol. 54, no. 5, pp. 29182921, Oct. 2007. [22] H. Chiu and S. J. Cheng, Single-stage voltage source charge-pump electronic ballast with switched-capacitor dimmer for multiple uorescent lamps, IEEE Trans. Ind. Electron., vol. 54, no. 5, pp. 29152918, Oct. 2007. [23] H. J. Chiu, T. H. Song, S. J. Cheng, C. H. Li, and Y. K. Lo, Design and implementation of a single-stage high-frequency HID lamp electronic ballast, IEEE Trans. Ind. Electron., vol. 55, no. 2, pp. 674683, Feb. 2008. [24] G. Y. Jeong, Novel LCD backlight inverter using a simple control circuit, in Proc. IEEE Power Electron. Spec. Conf., 2007, pp. 29642968. [25] C. S. Moo, K. H. Lee, H. L. Cheng, and W. M. Chen, A single-stage highpower-factor electronic ballast with ZVS buck-boost conversion, IEEE Trans. Ind. Electron., vol. 56, no. 4, pp. 11361146, Apr. 2009. [26] Y. C. Chuang, C. S. Moo, H. W. Chen, and T. F. Lin, A novel single-stage high-power-factor electronic ballast with boost topology for multiple uorescent lamps, IEEE Trans. Ind. Electron., vol. 45, no. 1, pp. 323332, Jan./Feb. 2009.

Chun-Yoon Park was born in Yeongju, Korea, in 1984. He received the B.S. degree in electronic and electrical engineering from the Pohang University of Science and Technology, Pohang, Korea, in 2008, where he is currently working toward the Ph.D. degree in electrical engineering. His research interests include dcdc converter, power-factor correction, and switch-mode power supplies.

Jung-Min Kwon (S08M09) was born in Ulsan, Korea, in 1981. He received the B.S. degree in electrical and electronic engineering from the Yonsei University, Seoul, Korea, in 2004 and the Ph.D. degree in electronic and electrical engineering from the Pohang University of Science and Technology, Pohang, Korea, in 2009. He is currently with Samsung Electronics, Inc., Korea. His research interests include renewable energy, distributed generation, and switch-mode power supplies.

Zhe Li received the B.S. degree in electrical engineering from the Shandong University, Jinan, China, in 2008. He is currently working toward the M.S. degree in electronic and electrical engineering at the Pohang University of Science and Technology, Pohang, Korea. His research interests include dcdc converters and switch-mode power supplies.

Bong-Hwan Kwon (M91) was born in Pohang, Korea, in 1958. He received the B.S. degree from the Kyungpook National University, Daegu, Korea, in 1982 and the M.S. and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology, Seoul, Korea, in 1984 and 1987, respectively. Since 1987, he has been with the Department of Electronic and Electrical Engineering, Pohang University of Science and Technology, Pohang, where he is currently a Professor. His research interests include converters for renewable energy, high-frequency converters, and switchmode power supplies.