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Lab 1 Quartus II and PLDT-2 Tutorial1

This tutorial will center on a calendar logic network in which January is encoded as M8M4M2M1 = 00012, February as 00102, through December as 11002. On the desktop find the Quartus II icon and double click.

Figure 1 Quartus II Icon

This will force Quartus II to open and a window similar to Figure 2 to appear. All work within Quartus II is done in a project. The project can be a single level or multiple levels or hierarchical. The first project will be a single level, but subsequent projects will be hieratical.

Figure 2 Quartus II Splash Screen

To create a project we will use the Project Wizard. The wizard will take us through the steps necessary to create a project. To access the project wizard, select the File menu and the select the New Project Wizard as shown in Figure 3.

Note graphics taken from Subscription Version of Quartus II 6.1

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Figure 3 File Menu

On page 1 of the wizard, the subdirectory for the project is specified. In Figure 4 the directory is specified under the subdirectory LAB_DAY. You should use LAB_MON for Monday through LAB_FRI for Friday. It is requested that you create a subdirectory structure under the above-mentioned directory. In this case the subdirectories Lab01 and then Calendar were created. Also, specify the project name and the top-level filename. All other files in a hierarchical design will fall below this level. In this project there will be no files below Calendar. You may click past page 2 of the wizard because no file has yet to be created for the project. On page 3 of the wizard the device to be programmed is specified. The PLDT-2 has the Altera MAX EPM7128SLC84-15. This device is in the MAX7000S Family. The 128 in 7128 indicates there are 128 macro cells; each one contains a single flip-flop. The S indicates that the device can be reprogrammed in place on the printed circuit board using a low voltage programming process. The LC indicates the device is in a LCC or Leaded Chip Carrier package (sometimes called Leadless Chip-Carrier). The 84 indicates that the package has 84 pins, which infers that there are in the range of 84 Input/Output pins. The -15 is the speed rating of this particular device. The -15 indicates that the nominal delay from input to non-registered output is a maximum of 15 ns. You will select the specific device because this is the only device provided for you. But a practicing engineer might select auto, and let the device grow as the design becomes bigger.

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Figure 4 Project Wizard Page 1

Select the MAX7000S family and then the EMP7128SLC84-15 device. You should click through the last two pages and then select the Finish button.

Figure 5 Select Specified Device

We want to program the unused pins as input in tri-state. This will prevent the unused pins from driving 1 or 0 as outputs. Therefore if we have a DIP-switch connected to

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ground on one of the unused pins, we dont want to burn it out. To set unused to input in tri-state, select Assignments and then Device. See Figure 6.

Figure 6 Assign Device Menu

Then the dialog box shown in Figure 7 will appear. Select the Device & Pin Options button. Then select the Unused Pins tab. The dialog box shown in Figure 8 will then appear. Select the As Inputs, Tri-Stated from dropdown list. This is not the default. The default condition may accidentally burnout the unused pin drivers. Now select the OK button. The unused pins are now safe from accidental burnout. I thank you and your fellow students thank you. We now need to create a design file that will specify the logic in the design. The design file may be a schematic with logic gate symbols placed on the page and interconnected with wires. Select File and then New on the main menu bar and the list shown in Figure 9 will appear. Or the design may be one of three different hardware design languages. The languages are the proprietary AHDL (Altera Hardware Description Language), VHDL (VHSIC Hardware Description Language) used in the course or Verilog. Select Block Diagram/Schematic File from the list and then OK. This will produce a graphic field in which we can place components. Now save the empty graphic filed in a file called Calendar.bdf . Note the state of the Add file to current design checkbox. Under the main menu item File select Save As . Then complete the dialog box. Save your files in the previously created subdirectory. Now enter your design.

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Figure 7 Settings Dialog Box

Figure 8 Unused Pins Tab Dialog Box

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Figure 9 Block Diagram/Schematic File

Select the AND gate symbol on the left boarder of the Calendar.bdf window, see the icon . Then traverse the file tree to C:/altera/72sp1/quartus/libraries/primitives/logic. We want a 5-input AND gate to implement the d28 function discussed in chapter 1 of Contemporary Logic Design, 2nd Edition. See the associated handout. The closest thing in the library is the and6 or six-input AND gate.

Figure 10 Save As Calendar.bdf

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Select the and6 device and place it on the sheet by selecting the OK button. Place it on the sheet by clicking the left button. Then click the right button and select cancel. Do not place it too close to the left edge because a row of input pins and inverters (not gates) will be added.

Figure 11 Symbols

After placing the and6 gate, place 5 not gates on the schematic. Then place 5 input pins. The input pins are in the pin library, not the logic library. Place an output pin on the and6 output. Since we only need to use 5 of the 6 inputs, you might decide to let one input float. Rule one of logic design is to NEVER allow an input to float. Therefore we will add a VCC or logic-1 signal to one of the inputs. We will learn in the lecture portion of the course that this will not affect the output of the AND gate. VCC is under primitive/other. Now select the wire icon, two icons below the AND gate icon on the left border of the sheet. The icon looks like this . After the gates, I/O pins, Vcc and wires have been placed; the schematic should look similar to the one shown in Figure 12. Note there are two wiring errors in this figure. One is a missed connection, and the other is an invert or NOT gate that should not be present. If you dont catch them now, they will be detected later on in the design, simulation and programming process.

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Figure 12 D28 Schematic

It now would be a good time to compile the Calendar.bdf file and look for errors and warnings. As an example when I first compiled the file I found that I had not connected pin_name8 to inst4. It was close but no cigar. I corrected the error and it compiled. There are four different ways to start a compilation. One, you may select the Start Compilation on the tool bar. The start compilation icon is . Two, you may use the accelerator Cntrl-L. Three, you may select Start Compilation under the Process menu. Or four, you may select Compiler Tool under the Processing menu. I prefer the icon. Either way Quartus II performs and Analysis and Synthesis which check for errors and if none are found it converts the design to equations. Next the fitter is called that maps the equations to the selected device. The third step converts the equations to a programming file by performing and assembles. The last step is to perform a timing analysis. Repeat the edit and compile process until there are zero errors and zero warnings. The fitter placed the equation in the device based on timing constraints. But you must also be concerned about assigning the input and output pins so that they work with the switches and LEDs of the PLDT-2.

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Table 1 I/O Pin Assignments

Pin 34 33 36 35 37 44

Type Input Input Input Input Input Output

Name LEAP M8 M4 M2 M1 D28

PLDT-2 S1-1 S1-2 S1-3 S1-4 S1-5 LED1

Use Quartus II to assign the pin names as shown in Table 1. To assign names select a given pin and then right click and select Properties. Under properties, type in the new name, and then select OK. After all six I/O pins have been named, then recompile and click through each message by selection YES. Now assign pin numbers. There are several ways to assign pin number but we will only cover one method. Under Assignments menu select the Assignment Editor submenu. See Figure 13 for the access to the Assignment Editor.

Figure 13 Assignment Editor Access

Under category select Pin. Under Edit select <<new>> in the To column perform a right click. Now select Edit Cell. Up should pop a list box with the entire assigned name from D28 to M8. Select one of the names, such as D28. Go to the Location column and right click and select Edit Cell. Scroll down to the pin number you want to use. From Table 1 we can see that D28 is to be assigned pin_44.

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Figure 14 Edit Cell Submenu

After all, of the assignments the edit window should look similar to Figure 15. The To and associated Location are important, but their row number is not important. I assigned them in alphabetic order. But numeric pin number order is just as valid. As is a random order as long as the To and associated Location are correct.

Figure 15 Pin Assignments for Calendar

Save changes and recompile. Now the Fitter will map the logic variable to the I/O pins we have selected. It is now time to do simulation. There are two type of simulation. One type is functional simulation, which is only dependent on the logic equations and is time independent. We will do a functional simulation first. The second type of simulation is a Timing simulation in which nominal delays on input pins and output pin drivers are taken in to account. Also the delays associated with the routed traces and the gate delays are all taken into account. We will do this simulation last. To do a functional simulation we must first create a Functional Simulation Netlist. Under the Processing menu select Simulator Tool. In dialog box that opens select the Functional Simulation Mode and then select the Generate Functional Simulation Netlist button. When the netlist generation is done, select OK. Specify the end simulation at 25

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* 100 ns = 3200 ns. We use 25 = 32 since there are 5 inputs LEAP, M8, M4, M2, and M1. We will make each step 100 ns. To do a functional simulation we must next create a test vector file. Under File menu select new and then go to the Other Files tab and select Vector Waveform File and then OK. See Figure 16 for the correct tab and file type.

Figure 16 New Dialog Box

A waveform window pops open and it ready to edit. First we should set the ending time under the Edit menu. Then select Ending Time and specify 3200 ns. Then select OK. Next we must associate the logic names with the rows of the window. Under the name column, right click and select Insert Node or Bus . A dialog box will pop up and the Node Finder button should be selected. A second dialog box will pop open and you should select List. You should now select the >> button. If you are successful, the dialog box should look similar to Figure 17. Click OK and continue. This the Node Finder dialog box will close and you will see the Insert Node or Bus dialog box reappear. Again select OK. The output waveform will be crossed hatched and the input will all be at logic-0. We must edit the input waveforms. Select M1 and edit this waveform. The waveform edit icons will appear on the left edge of the window. With M1 still selected, select the Count Value icon that looks like .

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Figure 17 Node Finder Dialog Box

Next up will pop a dialog box, titled the Count Value. Select the Timing tab. Under Transition occur select edit the 10 ns in count every to read 100.0 ns, see Figure 18. Then select OK. A waveform with a period of 200 ns will appear for the M1 signal. Repeat the process for M2 with a multiplier of 2, M4 with a multiplier of 4, M8 with a multiplier of 8, and LEAP with a multiplier of 16. Now save the vwf file as Calendar.vwf. This file should look similar to Figure 19. Press Ctrl-W to force the waveform to fit into the current window. Find the Simulation Tool dialog box, which should still be open. Select the browse button with the three dots on it, and find the Calendar.vwf that you just saved. Now you are ready to perform the simulation by selecting the following tool bar icon .

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Figure 18 M1 Count Value Dialog Box

Figure 19 Calendar.vwf Waveforms

Note a window will appear that looks very similar to the Calendar.vwf waveforms, except the D28 will be replaced with a waveform with logic-0 and logic-1 instead of the cross hatch waveform. If you are successful, the waveforms will look similar to Figure 20.

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Figure 20 Calendar Functional Waveforms

Note you can tell this is a functional simulation in that there is no propagation delay between the time M1 and M2 change and the output D28 changes. Figure 21 is the time interval between 180 ns and 320 ns, and shows no propagation delay.

Figure 21 No Propagation Delay

Next a timing simulation will be performed. Go to the Processing Menu and then select the Simulation Tool submenu. In the Simulation Tool dialog box change Functional to Timing and select the Start Simulation icon in either the dialog box or on the toolbar. At first the waveforms may look identical but inspect the waveform in the time interval from 180 ns to 320 ns. Note that propagation delay is now taken into account. The timing simulation D28 waveform in Figure 22 is delayed by approximately 30 ns over that in the functional simulation shown in Figure 21.

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Figure 22 D28 Timing Simulation

Note simulations should be checked for correctness. If you did not catch the inverter that was placed inline with the input pin M2 and the and6 gate, both your functional simulation and timing simulations are incorrect. Rule Two of design is ALWAYS check simulations for correctness. If you were sloppy and inattentive, you will need to go back and edit Calendar.bdf . Then recompile the design. Regenerate the functional simulation netlist. Perform both the functional simulation and the timing simulation. Repeat this process until every thing is correct. There are only two more steps left. They are programming the device and testing the design on the PLDT-2 board. But first check that the PLDT-2 board is powered by checking the red LED next to the power connector. See connector E in Figure 25. If the LED is not on turn the power supply on with the selector switch in the 7.5 VDC position. To program the EPM7128SLC84-15 we must first access the programming dialog box. To access this box select the menu Tools, followed by the submenu Programmer. Figure 23 show the programmer dialog box. The PLDT-2 uses the parallel port of the PC and the parallel port on the PLDT-2 to perform the programming. This hardware setup is known as the ByteBlasterMV. Other systems use the BitBlaster such as the Alter UP-2. My favorite programmer is know as the MasterBlaster because of the two characters with the same name in the movie Mad Max Beyond Thunderdome. If the Hardware Setup is not already as the ByteBlasterMV, click the hardware setup button. Add the ByteBlasterMV and then click OK. Figure 24 may help you complete this step. If not already selected, specify the POF to be used for the program file. Use add file to specify the POF. In this example the Project, Top Level and Program files are all called Calendar. You can use Auto Detect to detect the EPM7128SL84-15 on the PLDT-2

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board. Check to see that the Mode is set to JTAG. Use the drop down list if some other mode is specified. Now select the check boxes Program/Configure, Verify, and Blank Check. Leave the others unchecked. Now select the Start button. After the device is programmed we can verify that it is programmed properly. If you get and error message, ask the laboratory instructor or laboratory assistant for help.

Figure 23 Program Dialog Box

Figure 24 Hardware Settings Dialog Box

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To verify that the device is programmed correctly we must exercise the inputs with the DIP Switch S1, positions 1 through 5. See Table 1 for the S1 position to logic symbol translation. When the switch is closest to the edge of the board the logic variable is in the logic-1 state. Furthest from the edge of the board the logic variable is in the logic-0 state. Note the output is displayed on LED1. On represent a logic-1 and off represents a logic0. If the LED1 never lights, there is a good chance that the jumpers are missing from header M. If missing, place five jumpers in the left-most positions. Now retest to verify the logic. Complete Table 2 from the PLDT-2 system and the functional or timing simulation.

Figure 25 PLDT-2 Layout

Table 2 D28 Truth Table from PLDT-2 and Quartus II Simulation

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S1-1 S1-2 S1-3 S1-4 S1-5 LED1 Simulation Leap M8 M4 M2 M1 D28 D28 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1

Done?
You have now successfully completed a long sequence of events. However, one question is did you master the major rules and philosophies of the Quartus II Environment and the Calendar Project? One way to measure this is to repeat the tutorial without the aid of these pages. Simply use the circuit in Figure 1.19 on page 18 of the textbook2 (see figure 3 on page 4 of previously mentioned handout).

Contemporary Logic Design, Second Edition by Randy Katz and Gaetano Borriello

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Another way would be to use the truth table of Figure 1.18 on page 17 in the textbook (figure 2 on page 3 of handout) and implement d29 and assign the output to LED2 or which is on Pin 45. Some readers are most likely asking, Will I get credit for this? Or they are asking, Is this required? A few may be thinking. Can I get extra credit for doing this? The answer in each case is no. But will improve your mastery, which will reap reduced time spent in laboratory or at least more efficient time spent in laboratory in the future.

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