Programmable logic Devices (PLD)

Mantk Devreleri Yard.Do.Dr. Mutlu BOZTEPE

Programmable logic Devices

Programmable Arrays
OR Array AND Array

Classifications of Simple Programmable Logic Devices (SPLD)

Programmable Read-Only Memory (PROM) Programmable Logic Array (PLA) Programmable Array Logic (PAL) Generic Array Logic (GAL)

OR Array

Figure 3--65

An example of a basic programmable OR array.

AND Array

Figure 3--66

An example of a basic programmable AND array.

Programmable Read-Only Memory Connected (PROM) as a decoder!

Figure 3--67

Block diagram of a PROM (programmable read-only memory).

The PROM is used primarly as an addressable memory and not as a logic device because of limitations imposed by fixed AND gates.

Programmable Logic Array (PLA))

Figure 3--68

Block diagram of a PLA (programmable logic array).

The PLA was developed to overcome some of the limitations of PROM. The PLA is also called an FPLA (Field programmable logic array) because the user in the field, not the manufacturer, programs it.

Programmable Array Logic (PAL)

Figure 3--69

Block diagram of a PAL (programmable array logic).

It was developed to overcome certain disadvantages of PLA, such as longer delays due to the additional fusible links that result from using two programmable arrays and more dificult complexity. The PAL is most common one-time programmable (OTP) logic device and is implemented with bipolar technology (TTL or ECL)

Generic Array Logic (GAL)

Figure 3--70

Block diagram of a GAL (generic array logic).

The two main differences between GAL and PAL devices are: The GAL is reprogrammable The GAL has programmable output configurations. The GAL programmable again and again because it uses E2CMOS (electrically erasable CMOS) technology instead of bipolar technology and fusible links.

SPLDs summary

PALs

PAL Operation

Figure 4--44

Basic structure of a PAL.

Example
X=AB+AB+AB

Figure 4--45

PAL implementation of a sum-of-products expression.

Figure 4--46

Simplified diagram of a programmed PAL.

Example

PAL Block Diagram

Tristate control

PAL Output configuration Logic

Standart PAL numbering PAL10L8

Programmable array logic Ten inputs Eight outputs Active low output L: active-LOW H: active-HIGH P: programmable polarity

PAL10L8

GALs

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SPLDs summary

Generic Array Logic (GAL)

Figure 3--70

Block diagram of a GAL (generic array logic).

The two main differences between GAL and PAL devices are: The GAL is reprogrammable The GAL has programmable output configurations. The GAL programmable again and again because it uses E2CMOS (electrically erasable CMOS) technology instead of bipolar technology and fusible links.

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PAL

GAL Operation
The cells can be electrically erased and reprogrammed. A typical E2CMOS cell can retain its programmed state for 20 years or more

Example

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Example

GAL Block Diagram

OLMC: Output Logic Macrocells (Programmable output types!! Combinational or registered)

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GAL22V10 OLMC configurations

Active-LOW combinational mode Active-HIGH combinational mode Active-LOW registered mode Active-HIGH registered mode

GAL22V10 OLMC Configurations

S1=1 S0=0 Active-LOW combinational mode

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GAL22V10 OLMC Configurations

S1=1 S0=1 Active-HIGH combinational mode

GAL22V10 OLMC Configurations

S1=0 S0=0 Active-LOW registered mode

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GAL22V10 OLMC Configurations

S1=0 S0=1 Active-HIGH registered mode

GAL22V10 OLMC Configurations

Output or Input selection:

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Example S0=?

S1=?

X=ABCD+ABCD+ABCD+ABCD+ABCD+ABCD

Standart GAL numbering GAL16V8

Generic array logic Sixteen inputs Eight outputs Variable output configuration (remember OLMC)

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PLD programming

GAL22V10
12 inputs 10 input/outputs (I/O)

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GAL22V10 Array Diagram

12 inputs 10 input/outputs (I/O)

GAL22V10 Array Diagram

cell numbers in OLMC block for programming S0 and S1 These 12 special cells (5808 through 5827) are not shown in the array diagram

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GAL22V10 22 input lines 132 product term lines 5808 E2PROM intersections Each product term line consist of 44 AND gate inputs

Example: Implementing an SOP function

X=ABCDEF+ABCDEF+ABCDEF+ABCDEF+ABCDEF+ABCDEF+ABCDEF

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GAL 16V8
GAL16V8 is designed to be programmed in one of three available modes to emulate most of the existing PALs; thus, it may replace the PAL for which it is programmed.

GAL16V8 OLMC configurations

PAL Emulation
Simple mode
Combinational output Combinational output with feedback to AND array Dedicated input

Complex mode
Combinational output Combinational input/output (I/O)

Registered mode
In chap.9

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GAL16V8 Simple mode

XOR determines active state of the output

GAL16V8 Complex mode

XOR determines active state of the output The I/Os are limited to 6 in this mode Notice that there are only 7 inputs to the OR gate!! Because 8th input is used for tristate control This means OLMC can produce up to seven product terms in SOP expression

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