Solid-State Electronics 46 (2002) 17231727 www.elsevier.

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Fabrication of single-electron transistors and circuits using SOIs

Yukinori Ono *, Kenji Yamazaki, Masao Nagase, Seiji Horiguchi, Kenji Shiraishi, Yasuo Takahashi
NTT Basic Research Laboratories, NTT Corporation, 3-1 Morinosato Wakamiya, Atsugi, Kanagawa 243-0198, Japan

Abstract The paper describes the fabrication of single-electron transistors and circuits using silicon-on-insulators (SOIs). We rst point out that control of the oxidation of Si is quite important and could be the key to the fabrication of quantum devices including single-electron devices. We then introduce our technique for making single-electron transistors, which uses special phenomena that occur during the oxidation of SOIs, and show that the technique enables us to realize primary single-electron circuits as a result of its high controllability, reproducibility and thermal stability. 2002 Elsevier Science Ltd. All rights reserved.
Keywords: Silicon-on-insulator; Single-electron transistor; Quantum device; Oxidation; Inverter

1. Introduction According to the International Technology Roadmap for Semiconductors, the gate length of the MOSFETs in MPUs will reach 2022 nm in 2014. At these sizes, eects originating from single-electron charging and from low-dimensional subbands become eective. Quantum devices utilizing these eects will therefore become signicant at that time or later. Using Si for quantum devices is quite important because this enables us to combine them with MOSFETs, which is expected to enhance the advantages of each device, leading to higher-performance LSIs. Silicon-on-insulators (SOIs) are promising base materials for Si quantum device research because they provide a thin sheet of single-crystalline Si and allow the formation of lower-dimensional structures with the help of lithography. In addition, the large banddiscontinuity of SiO2 /Si interfaces would be benecial for the high-temperature operation of the quantum devices because of the strong connement of electrons.

Corresponding author. Tel.: +81-46-240-2641; fax: +81-46240-4317. E-mail address: ono@aecl.ntt.co.jp (Y. Ono).

Therefore, quantum SOI devices have been widely studied. Among them, single-electron devices are attracting the most attention [14]. One of the earliest observations of single-electron transistor (SET) characteristics in Si was actually done using SOIs [3]. The rst demonstration of the high-temperature operation of a SET was also achieved using SOIs [4]. Ever since these pioneering studies, single-electron tunneling has been observed by many groups [510] and a large variety of single-electron devices and primary circuits have been demonstrated [1122]. There are also a lot of reports on the fabrication of one- and two-dimensional quantum structures using SOIs [2335], and some have suggested, from photoemission spectra [35] and electrical characteristics [23,2931], the formation of subbands originating from SiO2 connement barriers. Despite such eorts, however, single-electron device research still focuses mainly on single devices, although quite a few groups are studying circuits composed of SETs. Whether the subband formation due to SiO2 barriers occurs is still unclear, and resonant tunneling through one- or two-dimensional subbands, to the best of our knowledge, has not yet been demonstrated in the SiO2 /Si system. This situation is mainly a result of a lack of technologies for fabricating quantum structures with

0038-1101/02/$ - see front matter 2002 Elsevier Science Ltd. All rights reserved. PII: S 0 0 3 8 - 1 1 0 1 ( 0 2 ) 0 0 1 4 1 - 7

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good controllability for systematic investigation of the systems. It will be crucial to establish a technology that makes it as easy to fabricate quantum devices with excellent controllability as it is to fabricate MOSFETs in order to merge quantum devices into MOS LSIs with already high and ever-improving performance. In this paper, we will point out in Section 2 that control of the oxidation of Si could be a key process in the fabrication of quantum devices including single-electron devices. Then, as a clue for their mass production, we will introduce our technique for making SETs, which uses special phenomena that occur during the oxidation of SOIs. We will also describe a circuit operation, which was accomplished by successful control of the electrical parameters of the SETs.
Fig. 2. Change in the band gap of Si as a function of strain for a Si wire with valley direction as a parameter.

2. Impact of thermal oxidation on the fabrication of single-electron and quantum SOI devices The diculty in making quantum devices is obviously due to their small size. Control of nanometer-scaled thickness, area, and volume is not easy even when state of the art lithography and/or self-organization techniques are used. The solution to this problem could be control of the thermal oxidation of Si. Thermal oxidation converts Si to SiO2 and consequently reduces the size of the Si, making it possible to produce structures that are much smaller than the critical dimensions of lithography. Furthermore, some unique features of oxidation of nanometer-scaled Si arising from oxidationinduced stress might be applicable to the formation of quantum structures and their size control. One is pattern conversion [31,36,43]. An example of this is shown in Fig. 1. These are transmission electron microscope (TEM) images of post-oxidation SOIs that had a at Si layer before oxidation. Splitting of the Si layer occurs only when it was initially thin (Fig. 1(c) and (d)). This is

because accumulation of stress around the edges of the wire suppresses oxidation there. (Oxidation-rate reduction similar to this occurs when narrow Si pillars [37] and dots [38] are oxidized, which is referred to as selflimiting oxidation [37].) Fig. 1 shows that the size of the resultant narrow wires is independent of the initially dened wire width and indicates that we can make narrow quantum wires beyond critical dimension of lithography in a controlled way. Another feature is band-prole modulation [39]. Fig. 2 shows results of the rst-principle calculations of the change in the band gap of Si as a function of strain for a Si wire with valley direction as a parameter. The data indicate that we can modify the band prole of Si intentionally by introducing local strain at a desired area, which is achievable by using the oxidation-induced stress.

3. Pattern-dependent oxidation for fabricating singleelectron transistors We have developed a special method of fabricating SETs that exploits the above-mentioned properties of oxidation in a very sophisticated way. The method is called pattern-dependent oxidation, or PADOX [4,40 42] because the shape of the pre-oxidation pattern of Si and the oxidation conditions determines the nal physical and electrical structures of the devices. (We have actually fabricated some devices by changing the initial patterns [12,17].) Fig. 3 shows a version of PADOX, where the initial pattern is vertically modulated (hence this is called vertical PADOX, or V-PADOX) [43]. In VPADOX, the pattern conversion shown in Fig. 1 is employed, and a narrow and short wire is automatically formed at the edge of the thin region. Tunnel barriers (made of Si, not of SiO2 ) are also formed around the

Fig. 1. Cross-sectional TEM images of Si wires after oxidation at 900 C. Initial thicknesses of Si were 22 nm for (a) and (b) and 14 nm for (c) and (d).

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Fig. 3. Pattern conversion by V-PADOX. L is the length of the thin region.

boundaries between the resultant narrow wire and thick regions. We infer from theoretical considerations that this automatic tunnel-barrier formation results from two competing eects on the band-prole modulation: a band gap increase due to the quantum connement eect and a band gap decrease due to the abovementioned strain eect. These two eects are expected to form a potential prole for the SET, i.e., two bumps for barriers and a well acting as an island [44]. One of the remarkable features of PADOX (including V-PADOX) is that the SETs are denitely stable for thermal cycling. Fig. 4 shows the current characteristics of a SET fabricated using V-PADOX. The curve in Fig. 4(a) was obtained within a month after fabrication, while that in (b) was obtained two years after the former measurements. Between the two measurements, the device temperature was cycled between $30 K and room temperature several times. The curve does not change within the accuracy of the measurement system used, indicating that the SET is not inuenced by random mobile charges, which, in general, fatally destabilize the current characteristics of SETs. This is not surprising because the base material and fabrication process for our SETs are fundamentally the same as those for MOSFETs, which are of course very stable. As for immobile random oset charges, although we have not yet

Fig. 4. Drain current vs. gate voltage characteristics of a SET, measured at 27 K with a sourcedrain voltage of 10 mV, on May 10, 1999 (a), and on April 13, 2001 (b).

obtained available data, we expect that control of the oset of the current characteristics would not be much more dicult than the threshold voltage control of MOSFETs, provided that the size of the island is precisely controlled. Another advantage is that PADOX and V-PADOX oer high controllability of the size of the island and electrical parameters of SETs. Especially in V-PADOX, automatic formation of narrow Si (Fig. 1) leads to better control of island size. Fig. 5 shows examples of the characteristics of V-PADOX SETs with a dierent L: 10 nm (a) and 50 nm (b). Here, L denotes the length of the thin region (see Fig. 3). In the gure, upper data show the output drain current ID for a xed drain voltage VD , while lower data show the output drain voltage VD for a xed drain current ID , both as a function of the gate voltage VG . As shown in ID vs. VG curves, the SETs exhibit clear conductance oscillations. The VD vs. VG curves reect the so-called Coulomb diamond. From these

Fig. 5. Characteristics of a SET with L of 10 nm (a) and 50 nm (b) as a function of the gate voltage. The upper data indicate output drain current for a xed drain voltage VD of 10 mV, while the lower data indicate output drain voltage VD for a xed drain current ID of 10 pA (a) and 300 pA (b). The dashed lines represent the voltage gain. The measurement temperature was 27 K.

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Fig. 6. Gate capacitance (a), source and drain tunnel capacitances (b), and voltage gain (c) of the SETs as a function of L, where L is the length of the thin region.

Coulomb diamonds, the capacitances of the source, drain, and gate were estimated to be 0.6, 0.6, and 0.7 aF, respectively, for the SET in Fig. 5(a) and 1.3, 0.7, and 2.6 aF for that in Fig. 5(b). We made the same measurements for 11 dierent SETs. The results are summarized in Fig. 6(a) and (b), where the obtained capacitances are shown as a function of L. The relationship between CG and L is nearly linear as shown in Fig. 6(a). In V-PADOX, the width and the thickness of the islands are expected to be automatically determined if we x the thickness of the starting Si pattern and the oxidation conditions. Thus, the island size is inuenced only by the parameter L, which determines the length of the island. The results prove that a single SET is formed as designed and V-PADOX provides good control of the gate capacitance. In Fig. 6(b), both source and drain capacitances are plotted. In contrast to CG , the dependence of CD and CS on L is weak. CD and CS are also well controlled and are around 1 aF. We should also mention that V-PADOX provides high-gain SETs [45]. The voltage gain (more precisely, the inverting voltage gain) is dened by the slope of the falling sides of the diamonds and can be evaluated by CG =CD [46]. As you can see in Fig. 5, the present SETs have voltage gain larger than unity. Fig. 6(c) shows the voltage gain as a function of L. You can see that a larger L results in a larger gain and the gain exceeds 3 for some of the SETs with L 50 nm. There have been no SETs reported with such high gains at such high temperatures ($30 K).

Fig. 7. Atomic force microscope image (a) and equivalent circuit (b) of the inverter. Input gate (not shown in (a)) covers two SETs. Current characteristics of the SETs in the inverter (c) and inputoutput transfer curve (d) measured at 27 K.

4. Circuit operations by single-electron transistors The above-mentioned high controllability and thermal stability have enabled us to realize circuit operation using plural SETs [20,21]. In this section, we introduce a single-electron inverter that can operate at $30 K [20]. We have realized this circuit by using two high-gain SETs made by V-PADOX. Fig. 7(a) and (b) shows the structure and equivalent circuit of the inverter. It con-

sists of two double-gate SETs. Each SET has a common input gate and an individual control gate. The common input gate is made of poly-Si and covers the entire pattern shown in Fig. 7(a) (thus it is not shown there). The control gates are made of SOI and are situated at the side of each SET. By applying a constant DC voltage to the control gates, we can shift the peak position of the current curves, and thus we can change the type (n-type or p-type) of the SETs. Fig. 7(c) shows the current characteristics of the two SETs. The curve for SET-2 is shifted to the positive input-gate voltage direction by applying a negative constant voltage (VCON 7 V) to the corresponding control gate. Fig. 7(d) shows the inputoutput transfer curve for a power supply voltage of 20 mV. Both larger-than-unity gain and full logic swing are achieved. This is the rst experimental demonstration of a single-electron circuit amplifying the voltage. We have also demonstrated half-sum and carry-out operations for a half-adder using a similar circuit composed of two SETs. This is the rst step toward making arithmetic units using SETs [21].

5. Conclusions For the fabrication of quantum SOI devices, we believe that control of the oxidation process of nanometer-

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scaled Si is important. Unique features that arise when it is oxidized, like pattern conversion and band-prole modulation, could lead to the formation of various types of quantum structures with good controllability. The idea has been embodied in methods of fabricating SETs called PADOX and V-PADOX, which have made it possible to fabricate single-electron circuits, including a complementary inverter.

Acknowledgements We thank Dr. Katsumi Murase, Dr. Kenji Kurihara, Dr. Hideo Namatsu, Dr. Hiroyuki Kageshima, Dr. Masashi Uematsu, Dr. Akira Fujiwara and Dr. Hiroshi Inokawa for their helpful discussions. We also thank Torao Saito, Yoshio Watanabe, Junzo Hayashi, Toru Yamaguchi, and Kazuhito Inokuma for their collaboration in device fabrication. References
[1] Field SB, Kastner MA, Meirav U, Scott-Thomas JHF, Antoniadis DA, Smith HI, et al. Phys Rev B 1990;42:3523 36. [2] Paul DJ, Cleaver JRA, Ahmed H. Appl Phys Lett 1993; 63:6312. [3] Ali D, Ahmed H. Appl Phys Lett 1994;64:211920. [4] Takahashi Y, Nagase M, Namatsu H, Kurihara K, Iwadate K, Nakajima Y, et al. Tech Dig IEDM 1994: 93840. [5] Leobandung E, Guo L, Wang Y, Chou SY. Appl Phys Lett 1995;67:93840. [6] Ishikuro H, Fujii T, Saraya T, Hashiguchi G, Hiramoto T, Ikoma T. Appl Phys Lett 1996;68:35857. [7] Ohata A, Toriumi A, Uchida K. Jpn J Appl Phys 1997; 36:16869. [8] Kester T, Hadam B, Hofmann K, Gondermann J, Stein J, o Hu S, et al. J Vac Sci Technol B 1997;15:28369. [9] Tilke A, Blick RH, Lorenz H, Kotthaus JP, Wharam DA. Appl Phys Lett 1999;75:37046. [10] Manninen A, Kauranen J, Pekora J, Savin A, Kamp M, Emmerling M, et al. Jpn J Appl Phys 2001;40:20136. [11] Fujiwara A, Takahashi Y. Nature 2001;410:5602. [12] Fujiwara A, Takahashi Y, Murase K, Tabe M. Appl Phys Lett 1995;67:29579. [13] Takahashi Y, Fujiwara A, Yamazaki K, Namatsu H, Kurihara K, Murase K. Electron Lett 1998;34:456. [14] Durrani ZAK, Irvine AC, Ahmed H, Nakazato K. Appl Phys Lett 1999;74:12935. [15] Stone NJ, Ahmed H. Electron Lett 1999;35:18834. [16] Takahashi N, Ishikuro H, Hiramoto T. Tech Dig IEDM 1999:3714. [17] Fujiwara A, Takahashi Y, Yamazaki K, Namatsu H, Nagase M, Kurihara K, Murase K. IEEE Trans Electron Dev 1999;46:9549.

[18] Takahashi Y, Fujiwara A, Yamazaki K, Namatsu H, Kurihara K, Murase K. Appl Phys Lett 2000;76:6379. [19] Ono Y, Takahashi Y, Yamazaki K, Nagase M, Namatsu H, Kurihara K, et al. Jpn J Appl Phys 2000;39:23258. [20] Ono Y, Takahashi Y, Yamazaki K, Nagase M, Namatsu H, Kurihara K, et al. Appl Phys Lett 2000;76:31213. [21] Ono Y, Takahashi Y. Tech Dig IEDM 2000:297300. [22] Single C, Prins FE, Kern DP. Appl Phys Lett 2001; 78:14213. [23] Omura Y, Nagase M. Jpn J Appl Phys 1995;34:8126. [24] Takahashi Y, Furuta T, Ono Y, Ishiyama T, Tabe M. Jpn J Appl Phys 1995;34:9504. [25] Dibiase N, Gabetta G, Lumachi A, Scagliotti M, Parmigiani F. Appl Phys Lett 1995;67:24913. [26] Wei Y, Wallace RM, Seabaugh AC. J Appl Phys 1997; 81:641524. [27] Kanemitsu Y, Okamoto S. Phys Rev B 1997;56:R155614. [28] Saeta PN, Gallagher AC. Phys Rev B 1997;55:456374. [29] Namatsu H, Horiguchi S, Takahashi Y, Nagase M, Kurihara K. Jpn J Appl Phys 1997;36:366974. [30] Ono Y, Yakahashi Y, Horiguchi S, Murase K, Tabe M. J Appl Phys 1996;80:44507. [31] Namatsu H, Horiguchi S, Nagase M, Kurihara K. J Vac Sci Technol B 1997;15:168896. [32] Ishikawa Y, Shibata N, Fukatsu S. Appl Phys Lett 1998; 72:25924. [33] Tang X, Baie X, Colinge J-P. Jpn J Appl Phys 1998; 37:15913. [34] Ernst T, Munteanu D, Cristoloveanu S, Ouisse T, Horiguchi S, Ono Y, et al. Microelectron Eng 1999;48:339 42. [35] Tabe M, Kumezawa M, Ishikawa Y. Jpn J Appl Phys 2001;40:L1313. [36] Nagase M, Fujiwara A, Yamazaki K, Takahashi Y, Murase K, Kurihara K. Microelectron Eng 1998;41 42:52730. [37] Liu HI, Biegelsen DK, Johnson NM, Ponce FA, Pease RFW. J Vac Sci Technol B 1993;11:25327. [38] Single C, Zhou F, Heidemeyer H, Prins FE, Kern DP, Plies E. J Vac Sci Technol B 1998;16:393842. [39] Shiraishi K, Nagase M, Horiguchi S, Kageshima H, Uematsu M, Takahashi Y, et al. Physica E 2000;7:33741. [40] Takahashi Y, Nagase M, Namatsu H, Kurihara K, Iwadate K, Nakajima Y, et al. Electron Lett 1995;31: 1367. [41] Takahashi Y, Namatsu H, Kurihara K, Iwadate K, Nagase M, Murase K. IEEE Trans Electron Dev 1996; 43:12137. [42] Fujiwara A, Takahashi Y, Namatsu H, Kurihara K, Murase K. Jpn J Appl Phys 1998;37:325763. [43] Ono Y, Takahashi Y, Yamazaki K, Nagase M, Namatsu H, Kurihara K, et al. IEEE Trans Electron Dev 2000; 47:14753. [44] Horiguchi S, Nagase M, Shiraishi K, Kageshima H, Takahashi Y, Murase K. Jpn J Appl Phys 2001;40:L29 32. [45] Ono Y, Yamazaki K, Takahashi Y. IEICE Trans Electron 2001;E-84C:10615. [46] Likharev KK. IEEE Trans Magn 1987;23:11425.