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A STUDY AND COMPARISON OF FULL ADDER CELLS BASED ON THE STANDARD STATIC CMOS LOGIC

Amir Ali Khatibzadeh, Kaamran Raahemifar


akhatibz@ee.ryerson.ca, kraahemi@ee.iyerson.ca Department o Electrical and Computer Engineering f Ryerson University Toronto, Ontario, Canada, M5B 2K3

Abstract
An overview of the performance of I-bit full adder cells based on the main standard static logic styles and in depth examination of the advantages and limitations of each o them with respect to speed and power f dissipation are presented A comparison is performed in a wide range of main static logic styles. Six I-bitfull adder circuits based on these logic styles are chosen for the extensive evaluation. These circuits were redesigned at the transistor-level in a standard 0.18pm CMOS process technologV and comparison reported here uses HSPICE simulations to assess their perjormance. Realistic circuit arrangements are used to demonstrate the performance o each I-bit full f adder cell. The work presented in this paper gives a quantitative comparison o the adder cell performance. f The results rearranged the previous full adder cell ranking.
Keyword: Full Adder, Low power, High-speed

I. INTRODUCTION
The addition of two binary numbers is the fundamental and most often used arithmetic operation on microprocessors, digital signal processor (DSP), etc. Therefore, binary adders are crucial building blocks in very large-scale integrated (VLSI) circuits. From the previous works [1][2][3] it bas been concluded that there is no ideal adder cell that can be used by all types of applications. Therefore, many different circuits for binary addition have been proposed over the last decades, covering a wide range of performance characteristics to satisfy the constraints enforced by different applications. The logic style used in adder cells basically influences the speed, size and power dissipation of the CCECE 2004 - CCGEI 2004, Niagara Falls, May/mai 2004 0-7803-8253-6/04/$17.00 0 2004 IEEE -001-

circuits. The circuit delay is determined by the number of inversion levels, the number of transistors in series, and transistor sizes (i. e., channel width). Circuit size depends on the number of transistors and their sizes. Finally power dissipation is determined by the switching activity and the node capacitance (made up of gate, diffusion, and wire capacitance). All these characteristics may vary considerably from one logic style to another and thus make the proper choice of logic style crucial for circuit designer to satisfy their needs. In this paper the complementary CMOS logic, complementary pass-transistor, double pass-transistor, transmission gate, pseudo NMOS and a novel logic (combinational of XOR and transmission gate), all of which belong to the class of the static logic, are used as a basis for comparison. Six different adder cells are redesigned at transistor levels in 0.18 pCMOS technology and tested separately. Eacb of these circuits is optimized for power and speed. Adder cells are then ranked base on simulation results, according to power consumption and delay. This paper is organized as follow. In section 2 static logic style is briefly reviewed. Section 3 gives a short overview of I-Bit full adder cells for the most important existing static logic styles and compares them qualitatively. Results of quantitative comparisons based on the simulations are also given and the paper concludes with Section 4.

2. STATIC LOGIC
Different design requirements such as area, speed and power consumption generally translate into use of different logic styles. Proper choice of the logic style can considerably improve different aspects of the performance of a I-bit full adder cell. A major distinction bas been made between static and dynamic logic styles. In static logic each outputs of the gates assume at all times the value of the Boolean function implemented by the circuit. This means that at every point time, each

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output is connected to either V or V, via a low , resistance path. Static logic is viable candidate for low power circuit design because this logic style eliminates the precharging and decreases extra power dissipation by the clocking. The complementary CMOS, complementary pass-transistor (CPL), pass-transistor logic styles), double pass transistor (DPL) and singlerail pass transistor (LEAP), the pseudo NMOS are the most known static logic styles.

order to lower the power consumption of complementary pass-transistor, two circuit styles are used. These circuits have output levels restored with cross-coupled inverters (SWL)[5] and latches (LCPL)[6]. Layout of this full adder cell family is also not straightforward and efficient due to irregular transistor arrangements and high wiring requirement

~71.

3.3. Double Pass-transistor Full Adder

3. FULL ADDER CELLS


A short summary of the full adder operation can be defined for the given the three I-hit inputs A , B. and Ci.and two 1-hit outputs Sand C O as following. ,
S = A 8 B 8 Cin C , = A B + Cjn.(A E ) O, @ The static logic comprehends several logic families as the above mentioned. Six different full adder cells are redesigned, developed and simulated based on these logic styles.

Double pass transistor full adder cell has 48 transistors and operation of this cell is based on the double pass transistor logic in which both NMOS and PMOS logic network are used (Fig.3.a & h)[8]. This cell is similar in structure to the complementary pass transistor counterparts, hut it uses complementary transistors to keep full swing operation and reduce the power consumption. This eliminates the need for restoration circuitry. Disadvantage of this cell is the large area used due to the presence of PMOS transistors.

3.1. Complementary CMOS Full Adder


Complementary CMOS full adder (CMOS) [4] has 28 transistors and is based on the regular CMOS structure (pull-up & down networks) (Fig.1). One of the advantages of the complementary CMOS full adder cell is high noise margins and thus reliable operation at low voltages and arbitrary transistor sues (ratio less logic). The layout of CMOS gates is straightforward due to the complementary transistor pairs. An oftenmentioned disadvantage of complementary CMOS full adder cell is the substantial number of large PMOS transistors, resulting in high input loads, more power consumption and larger silicon area. This adder cell uses CO,, signal to generate Sum, which produces an unwanted additional delay.. Another drawback of CMOS is the relatively weak output driving capability due to series transistors in the output stage.

3.4. Transmission Gate CMOS Full Adder


Transmission gate full adder cell has 20 transistors (Fig. 4). This circuit generates A+ B and use it and its complements as a selected signal to generate the output signals (Sum & CO*) [9]. It also requires complementary input signals (A, B, C,) as the complementary CMOS full adder; however, it exhibits better speed than CMOS full adder at the same power dissipation due to the small transistor stack height [I].

3.5. Pseudo NMOS Full Adder

3.2. Complementary Pass-transistor Full Adder


Complementary pass-transistor full adder cell has 32 transistors (Fig.2). Using pass-transistor logic with CMOS output inverters, complementary pass-transistor full adder cell features complementary inputs and outputs, This circuit generates many intermediate nodes and their complements in order to generate the final signals (Sum and COu,).Having a signal and complement produces high rate of switching activities. Therefore complementary pass-transistor full adder cell is not a suitable for low power applications. In

Pseudo NMOS full adder cell operates based on pseudo logic, which is referred to ratioed style. This cell uses 14 transistors to realize the negative addition function (Fig. 5). The advantage of pseudo NMOS adder cell is its higher speed (compared to complementary full adder) and low transistor count. On the negative side is the static power consumption of the pull-up transistor as well as the reduced output voltage swing, which makes this cell more susceptible to noise. To increase the output swing two CMOS inverters are added to this circuit, which increases the total transistors count of this cell to 18 transistors.

3.6. XOR and Transmission Gate Full Adder


This adder cell has been developed based on a XOR gate presented in combined with the transmission gate,

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which requires a total of 14 transistors [11](Fig. 6). Generating the half sum by using XOR gate and hy using the transmission gate theory the second half of the circuit will generate the Sum and Cod. This cell occupies less area compared with complementary CMOS full adder cell. In terms of power dissipation this cell is superior, this is due to its low activity factor and passing a strong signal in less number of pass logic unlike the other cells where the signal had to go through more number of logic.

3. TEST CIRCUIT & SIMULATION


The comparisons are carried out based on the use of the adder cell in bigger structure such as pipelined multiplier where the inputs (A, B & C,) are fed to the adder fiom storage elements (latches or flipflop) and the outputs (Sum & CO",)feed to the adjacent pipelied stage (Fig. 7). Simulation results for the examined full adder cells using the test circuit at 1.8V are shown in Table I & 1 . 1 Fig. 2. Complementary pass-transistor full adder

Fig. 3.a Double pass transistor full adder cell (Sum)

Fig. 1. Complementary CMOS full adder

Double pass transistor

0.167

Table I. Measured results of speed optimized FAs Fig. 3.b Double pass transistor full adder cell (C,3

4. CONCLUSION
. .

n 761 0.367 Table 11. Measured results of power optimized FAs


Double mass transistor
Complementary pawtransistor

The Quantitative overview of performance of the full adder cells has been presented. Six adders cells were chosen based on CMOS static logic styles and

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two versions of each cell with a minimum size (lowpower) and maximum speed were implemented and simulated in 0 . 1 8 ~ CMOS technology using HSPICE simulations. The comparison was carried out based on the experimental result formed by a realistic test circuit. Adder cells are then ranked according to power consumption and delay. The results of this work help the designers to pick the full adder cell that satisfies their specific applications.

#
Fig. 5. Pseudo NMOS full adder

Fig. 6 . XOR & transmission gate full adder

Fig. 7. Test circuit structure Fig. 4. Transmission gate CMOS full adder [3] A. M. Shams, T. K Danvish and M. A. Bayoumi, Performance Analysis of Low-Power I-Bit CMOS Full Adder Cells, IEEE Trans. on Very Large scale Integration (l4LSI) Systems vol. 10, pp. 20-29, February 2002.
[ ] R. Zimmermann and W. Fichtner, Low-power Logic 4 Styles: CMOS versus Pass-Transistor Logic, IEEE J. Solid-

Stafe Circuits, vol. 32, pp.1079-90, July 1997.


[5]A. Parameswar et al., A High Speed, Low Power, Swing Restored Pass Transistor Logic Based on Multiply and Accumulate Circuit for Multimedia Applications, IEEE CICC3May 1994, pp. 278-281.

[6] Y. Sasak ef al., Pass Transistor Based on Gate Array Architectures, in 1 9 5 Symp. VLSI Circuifs, Dig. Tech. Papers, June 1995,pp. 123-124. [7] K.Yano, Y. Sasald, K. Rikino and K Seki, Top-Down Pass-Transistor Logic Design, IEEE J. Solid-State Circuits, vol. 31, pp. 792-803, June 1996. [XI M. Suzuki et al., A 1.5-ns 32-b CMOS ALU in Double Pass-TransistorLogic, IE J. Solid-State Circuifs, vol. 28, no. 11,pp. 1145-1151,November 1993. [9] N. Weste and K. Eshraghian ,Principles of CMOS VLSI Design, A System Perspective, MA Addison-Wesley, 1993.

References
[I] A. Shams and M. Bayoumi, A Modular Approach for Desiging Low Power Adders, Proc. ASILOMAR, June 1997. [2] H. Lee and G. Sobelman, A New Low-Voltage Full Adder Circuit, IEEE Int. Symp. on Circuifs and Systems, 1997,pp. 88-92.

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