Fifteenth National Power Systems Conference (NPSC), IIT Bombay, December 2008

A Study of Neutral Point Potential and Common Mode Voltage Control in Multilevel SPWM Technique
P. K. Chaturvedi, Shailendra Jain, and Pramod Agrawal, Member, IEEE

Abstract Conventional 2-level PWM inverters generate high dv/dt and high frequency common mode voltages which is very harmful in electric drives applications. It may damage motor bearings, conducted electromagnetic interferences, and malfunctioning of electronic equipments. Due to capacitor voltage unbalancing, neutral point potential also varies from zero. This paper presents a simple method to control the harmonics, common mode voltages and neutral point potential variation in neutral point clamped (NPC) inverters using different structures of sine-triangle comparison method such as Phase Disposition (PD), Phase Opposition Disposition (POD), and Common Mode Voltage off-set voltage addition method. Simulation results confirm the effectiveness of these simple methods to control common mode voltages. Neutral point potential variation is limited to less than 2% of dc capacitor voltage using a simple closed loop PI regulator. Experimental results presented have been obtained using dSPACE board DS 1104. Index TermsCommon Mode Voltage, Harmonics, Multilevel Inverter, Neutral Point Potential Control.

magnitude of common mode voltage is determined by dv/dt and number of commutations. Several methods have been suggested for solving this problem. Some methods are based on additional circuit like filters. Other methods use advanced modulation strategies avoiding the generation of common mode voltages. But, these methods work at higher switching frequency, thus increasing the losses [1]-[3]. Various multilevel inverter control techniques, using sine-triangle comparison, for harmonic reduction have been reviewed in [4]. But the issue of common mode voltage control was not covered. Opportunities of harmonic reduction in cascaded multilevel inverters were investigated in [5-6] using carrier based PWM techniques. Conventional multilevel SPWM techniques generate a significant amount of common mode voltage which may be around the dc voltage level.

I. INTRODUCTION ecently, multilevel inverters have been found wide spread acceptability in medium and high voltage applications. Multilevel inverters have the advantage of producing high voltage high power with improved power quality of the supply. It also eliminates the use of problematic series-parallel connections of switching devices. However, multilevel PWM inverters generate common mode voltages as in the case of conventional 2-level inverters. The problem of common mode voltage generation in multilevel inverters has been studied extensively during last decade [1-5]. Common mode voltages are generated due to shaft voltages, circulating leakage currents through parasitic capacitance between motor windings, rotor and frame. The number of current spikes and
P.K. Chaturvedi is Research Scholar at Electrical Engineering Department, National Institute of Technology, Bhopal, India; (e-mail: pradyumnc74@rediffmail.com). Shailendra K. Jain., is Assistant Professor with the Electrical Engineering Department, National Institute of Technology, Bhopal, India; (e-mail: shailjain02@rediffmail.com). Pramod Agarwal is Professor with the Electrical Engineering Department, Indian Institute of Technology, Roorkee, India (e-mail: pagarwal@iitr.ernet.in).

Fig. 1. Structure of 3-phase, 3-level diode clamped inverter.

Another problem which NPC inverter faces is neutral point potential (NPP) variation due to voltage unbalancing between two capacitors. Due to the variation in NPP, excessive high voltages may be applied across switching devices. Several methods have been investigated to control the NPP variation and neutral point current [7-10]. A neutral point voltage regulator has been modeled and designed in [10]. But it works at 5kHz switching frequency resulting in high switching losses. In this paper, a NPP regulator is presented which works at low switching frequency of 2 kHz. This paper also investigates the possibilities of using different multilevel SPWM techniques such as Phase Disposition (PD), Phase Opposition Disposition (POD) and Common Off-set voltage addition method (Bias method) to reduce the common mode voltages in 3-level diode clamped inverter. Results show drastic reduction in THD using modified SPWM methods. At the same time common mode voltages are also controlled up

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to nearly half of the magnitude as compared to conventional multilevel SPWM methods. Neutral point potential variation is also controlled by closed loop PI regulator. This regulator provides capacitor voltage balancing and harmonics reduction in load voltage and current below IEEE-519 standard. II. OPERATION OF 3-LEVEL SPWM

(4) V* = v(r, y, b) + Voffset where, v(r, y, b) is given by equation (1). Fig. 4 and Fig. 5 give the reference 3-phase waves as obtained from equation (4). The max, min, one phase voltage vr and off-set voltage signals, as obtained from equation (3) and (4), are shown in Fig. 6 for PD SPWM case.
carrier 1 1 vr vy vb

Fig. 1 shows the very popular topological structure of diode clamped 3-phase, 3-level inverter considered here for study. The switching states of the inverter are shown in Table I for one leg. It gives the output pole voltage VAO, output line voltage VAB and switch state. Switch state 1 means on and 0 means off. This switching pattern can be achieved by means of different multilevel control strategies such as square wave switching, sine-triangle comparison method (SPWM), space vector modulation (SVM), selective harmonic elimination technique, hysteresis current control, sigma-delta modulation etc. Of these methods, sinusoidal pulse width modulation (SPWM) is the simple and cost effective method to implement, therefore considered here.
TABLE I SWITCHING STATES OF 3-LEVEL DIODE CLAMPED INVERTER Switch States VAB Output Pole Voltage (VAO) Sa1 Sa2 Sa1 Sa2 - Vdc/2 0 0 0 1 1 0 Vdc/2 0 1 1 0 Vdc/2 Vdc 1 1 0 0

0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 carrier 2

0.002 0.004 0.006 0.008

0.01

0.012 0.014 0.016 0.018

0.02

Fig. 2. Modulation and carrier waveforms with PD SPWM technique.

carrier 1 1 0.8 0.6 0.4 0.2 carrier 2 0 -0.2 -0.4 -0.6 -0.8 -1 vr vy vb

SPWM technique is again subdivided into following categories: Phase Disposition (PD) method, Phase Opposition Disposition (POD) method, Phase Shifted (PS) method, Hybrid method, Third Harmonic Injection (THI) method. Basic principles of pulse generation for 3-level PD and POD SPWM techniques are shown in Fig. 2 and 3. Fundamental frequency three-phase sinusoidal reference waves vr, vy and vb are compared with two high frequency triangular carrier waves carrier 1 and carrier 2. Each intersection gives rise to the control pulses for switching devices of inverter. The reference sinusoidal waves can be represented by, vr = Vm sin ( t) vy = Vm sin ( t-1200) (1) vb = Vm sin ( t-2400) PD and POD SPWM techniques have been selected for study without and with addition of common mode voltage off-set as shown in Fig. 2 to Fig. 5. Common mode voltage or zero sequence voltage in output voltage of inverter can be represented by, Vcm = (vr+vy+vb)/3 (2) where, vr, vy and vb are the phase voltages of inverter. This voltage is around 150-200 volts (peak) in conventional 2-level inverters for a dc voltage of 200 volts. To reduce it, following common mode off-set voltage is to be added, Voffset = - [min(vr, vy, vb) + max(vr, vy, vb)] /2 (3) Therefore the new reference or modulation wave becomes,

0.002 0.004 0.006 0.008

0.01

0.012 0.014 0.016 0.018

0.02

Fig. 3. Modulation and carrier waveforms with POD SPWM technique.

carrier 1 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 carrier 2 vr vy vb

0.002 0.004 0.006 0.008

0.01

0.012 0.014 0.016 0.018

0.02

Fig. 4. Modulation and carrier waveforms with addition of common mode off-set voltage in PD SPWM technique.

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Fifteenth National Power Systems Conference (NPSC), IIT Bombay, December 2008
carrier 1 1 0.8 0.6 0.4 0.2 carrier 2 0 -0.2 -0.4 -0.6 -0.8 -1 vr vy vb

0.002 0.004 0.006 0.008

0.01

0.012 0.014 0.016 0.018

0.02

Fig. 5. Modulation and carrier waveforms with addition of common mode off-set voltage in POD SPWM technique.
1 0.8 0.6 0.4 0.2 0 -0.2

Vr
Vmax

phase inverter output voltages are sensed and converted into per unit system. These per unit voltages are converted into dqo axis using following 3-phase to two-phase conversion, Vd = 2/3 [Va sin( t) + Vb sin( t-1200) + Vc sin( t-2400)], Vq = 2/3 [Va cos( t) + Vb cos( t-1200) + Vc cos( t-2400)], (5) Vo = (Va + Vb + Vc)/3 These dqo voltages, Vdqo, are compared with set values of dqo voltages Vdqo*. It results in voltage error which is processed through a proportional-integral (PI) controller to generate two axis command signals Vdq. Then three phase reference voltage signal for PWM generator is synthesized using following two-to-three phase conversion, Va = [Vd sin( t) + Vq cos( t) + Vo], Vb = [Vd sin( t-1200) + Vq cos( t-1200) + Vo], (6) Vc = [Vd sin( t-2400) + Vq cos( t-2400) + Vo], Amplitude modulation index, m, is defined as, (7) m = sqrt(Vd2 + Vq2) and the gain of PI controller is, (8) G = Kp + [Ki *Ts/(Z-1)] Values of Kp, Ki and limits of integration are tuned to achieve fast response of modulation index and to reduce NPP variation below 2%. Output of 3-level PWM generator block is the 3phase sinusoidal reference signals to be applied to the PD SPWM scheme as discussed in previous section. IV. SIMULATION RESULTS A simulation model has been developed in Matlab environment. Simulation parameters are given in Appendix I. Fig. 8 and Fig. 9, show the waveforms and harmonic spectrum of line voltage with PD SPWM without and with filter. It is observed that fundamental voltage is increased from 173.2 volts to 181.2 volts with reduction in % THD from 29.34% to 2.00%. Switching frequency used is 1 kHz. Table II gives the % THD and fundamental value of line voltage (V1ab) and current (i1a) without and with filter. From this table, it is clear that the fundamental voltage increases with filter and maintaining the low THD, well below the IEEE-519 standard.
200

Voffset
-0.4 -0.6 -0.8 -1

Vmin

0.005

0.01

0.015

0.02 0.025 time (sec)

0.03

0.035

0.04

Fig. 6. Signals Vmax, Vmin, vr and off-set voltage Voffset in PD SPWM technique with addition of offset voltage to the reference signals.

III. DESIGN OF NEUTRAL POINT POTENTIAL REGULATOR Fig. 7 shows the closed loop scheme of proportionalintegral (PI) neutral point potential (NPP) regulator.
Ld Pos

100

C1 Uncontrolled Bridge Rectifier O 3-Level Diode

Clamped

Passive Filter

Inverter C2 Neg

L O A D

-100 -200 0.02

0.025

0.03

0.035

3- Phase AC Source

0.04 0.045 Time (s)

0.05

0.055

Vabc
abc to per unit conversion Vabc (pu) abc-dqo Vdqo
Mag (% of Fundamental)

Fundamental (50Hz) = 173.2 , THD= 29.34% 100 80 60 40 20 0

Control Pulses ........ (12)

High Frequency Triangular Carrier Signals

3-Level PWM Generator

Ref. Sinusoidal Modulating Signal

Vabc * Vdqo*
PI

dqo to abc conversion

Ref. Vdqo

Fig. 7. Block diagram of closed loop voltage regulator.

10

20 30 Harmonic order

40

50

Fig. 8. Line voltage and its harmonic spectrum with PD SPWM.

The proposed PI voltage regulator aims to stabilize the dc link voltage to control neutral point potential variation by controlling the charging and discharging of upper and lower dc bus capacitors without dc capacitor voltage sensing. Three-

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Fifteenth National Power Systems Conference (NPSC), IIT Bombay, December 2008

200 100

The variation in NPP was observed at 1.4 % of dc bus voltage across one capacitor.
Vdc1 272
6 4 2 Neutral Point Potential

0
270

-100 -200 0.02

268 266 264 0.65

0 -2 -4

0.025

0.03

0.035

0.04 0.045 Time (s)

0.05

0.055

Fundamental (50Hz) = 181.2 , THD= 2.00% 100 Mag (% of Fundamental) 80 60 40 20

0.655

0.66

0.665

0.67 0.675 Time (s)

0.68

0.685

-6 0.65

0.652

0.654

0.656 0.658 Time (s)

0.66

0.662

Fundamental (150Hz) = 3.978 , THD= 3.00%

Vdc2 272
Mag (% of Fundamental)

100 80 60 40 20 0

270 268 266 264 0.65

0.655

0.66

0.665

0.67 0.675 Time (s)

0.68

0.685
0 10 20 30 Harmonic order 40 50

10

20 30 Harmonic order

40

50

Fig. 9. Line voltage and its harmonic spectrum in PD SPWM with filter.

Mag (% of Fundamental)

Fig. 10 gives the common mode voltages with normal and modified PD and POD SPWM techniques. It is clear from the Fig. 10, that peak of the common mode voltage (Vcm) is less sharp in the case of Fig. 10(c) and amplitude is reduced from around 60 volts in PD SPWM to around 34 volts in POD SPWM. Also frequency of Vcm is reduced in Fig. 10(d) as compared to its counterpart in Fig. 10(b). Therefore, PODSPWM technique will be advantageous in view of the common mode voltage amplitude and frequency stress on motor windings.
100 50 0 -50 -100 0.02 40 20 0 -20 -40 0.02

Fig. 11. Voltages across capacitors, Vdc1, Vdc2 and neutral point potential with its frequency spectrum.
1000 500 0 -500 -1000

0.605

0.61

0.615

0.62 0.625 Time (s)

0.63

0.635

0.64

Fundamental (50Hz) = 376.8 , THD= 17.17% 100 80 60 40 20 0

0.025

0.03

0.035

0.04 0.045 Time (s)

0.05

0.055

10

20 30 Harmonic order

40

50

Fig. 12. Inverter output voltage, Vab, and its harmonic spectrum at 2 kHz switching frequency.
400 200
0.025 0.03 0.035 0.04 0.045 Time (s) 0.05 0.055

0 -200 -400

100 50 0 -50

0.605

0.61

0.615

0.62 0.625 Time (s)

0.63

0.635

0.64

Fundamental (50Hz) = 371.1 , THD= 2.05% 100 Mag (% of Fundamental)

0.205 0.21 0.215 0.22 0.225 Time (s) 0.23 0.235

-100 0.2

40 20 0 -20 -40 0.2

80 60 40 20 0

0.205

0.21

0.215

0.22 0.225 Time (s)

0.23

0.235

10

20 30 Harmonic order

40

50

Fig. 10. Common mode voltages with (a) PD, (b) POD, and (c) common mode voltage PD and (d) common mode voltage POD SPWM techniques.

Fig. 13. Load voltage and its harmonic spectrum at 2 kHz switching frequency.

Fig. 11-15 shows, the results of closed loop control of inverter voltages and neutral point potential control with PI regulator. Upper and lower dc link voltage and neutral point potential is shown in Fig. 11. It is observed that % THD in NPP is well below the IEEE-519 standard of 5 %. The frequency of NPP was observed at 150 Hz. Average dc bus voltage across capacitors is 268 volts with % THD of 0.76.

Inverter output voltage its harmonic spectrum for two cycles is shown in Fig. 12. Voltage across load is shown in Fig. 13. It is observed that % THD in voltage is reduced from 17.17 to 2.05 when using LC passive filter with 2mH inductance and 2kVar capacitive reactive power. Inverter line currents without and with filter are shown in Fig. 14 and Fig. 15. Current THD also reduces from 12.20 % to 1.27 % using suitable passive filter.

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Fifteenth National Power Systems Conference (NPSC), IIT Bombay, December 2008
Current, ia, Before Filter 40 20 ia (amp) 0 -20 -40 0.8

0.805

0.81

0.815

0.82 0.825 Time (s)

0.83

0.835

Fundamental (50Hz) = 19.58 , THD= 12.20% 100 Mag (% of Fundamental) 80 60

(a)
40 20 0

10

20 30 Harmonic order

40

50

Fig. 14. Inverter output current and its harmonic spectrum at 2 kHz switching frequency.
Current, ia, After Filter 20 10 ia (amp) 0 -10 -20 0.8

0.805

0.81

0.815

0.82 0.825 Time (s)

0.83

0.835

(b) Fig. 16. Firing pulses for switches (a) Sa1, Sa2, Sa1, and Sa2 of one phase, and (b) Sa1, Sb1, and Sc1 of three phases, with PD SPWM technique.

Fundamental (50Hz) = 18.75 , THD= 1.27% 100 Mag (% of Fundamental) 80 60 40 20 0

10

20 30 Harmonic order

40

50

Fig. 15. Filtered inverter output current and its harmonic spectrum at 2 kHz switching frequency.

V. EXPERIMENTAL VERIFICATION A laboratory prototype of 3-phase, 3-level diode clamped inverter has been developed using IGBTs. Control logic has been developed in Matlab environment and interfacing was performed using dspace DS-1104. A dc link capacitor of 2200 F is used. Three-phase uncontrolled diode bridge rectifier is used to supply input dc voltage to 3-level inverter at 40 volts. Only few selected results have been presented. Fig. 16 shows firing pulses generated with PD SPWM. Fig. 17 shows phase voltage and line voltage waveforms at 2 kHz switching frequency. It is in agreement with simulation result shown in Fig. 8. Harmonic spectrums of phase and line voltages are shown in Fig. 18. Harmonic contents in inverter output phase and line voltages are 36.9 % and 15.1 %, which are comparable with simulation results of 40 % and 19.60 %. Common mode voltage and neutral point potential control study are in progress experimentally and will be reported in future.

(a)

(b) Fig. 17. Inverter output voltages, (a) phase voltage, and (b) line voltage, with PD SPWM technique.

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A. M. Massoud, S. J. Finney, and B. W. Williams, Control Techniques for Multilevel Inverters, in Proc. 34th Annu. Power Electronics Specialist Conf. (PESC) Rec., June 2003, vol. 1, pp. 171-176. [5] Thomas Bruckner, and D. G. Holmes, Optimal Pulse-Width Modulation for Three-Level Inverters, IEEE Trans. Power Electronics, vol. 20, no. 1, pp. 82-89, Jan 2005. [6] P. Srikant Varma, and G. Narayanan, Space Vector PWM as a Modified Form of Sine-Triangle PWM for Simple Analog or Digital Implementation, IETE Journal of Research, vol. 52, no. 6, pp. 435-449, Nov/Dec 2006. [7] Ashish Bendre, and Giri Venkataramanan, Neutral Current Ripple Minimization in a Three Level Rectifier, IEEE Trans. On Industry Applications, vol. 42, no. 2, pp.582-590, Mar/Apr 2006. [8] H. du Toit Mouton, "Naturtal Balancing of Three-Level Neutral Point Clamped PWM Inverter," IEEE Trans. Industrial Electronics, vol. 49, no. 5, pp. 1017-1025, Oct 2002. [9] Annette ve Jouanne, Shaoan Dai, and Haoran Zhang , "A Multilevel Inverter Approach Providing DC-Link Balancing, Ride Through Enhancement, and Common Mode Voltage Elimination," IEEE Trans. Industrial Electronics, vol. 49, no. 4, pp. 739-745, Aug. 2002. [10] Ashish Bendre, Giri Venkataramanan, V. Srinivasan, and D. Rosene, Modeling and Design of a Neutral Point Voltage Regulator for a Three Level Diode Clamped Inverter Using Multiple Carrier Modulation, Research Report, 2003-26, WEMPEC, University of WisconsinMadison. [4]

(a) (b) Fig. 18. Harmonic spectrum of inverter output voltages, (a) phase voltage, and (b) line voltage, with PD SPWM technique.

VI. CONCLUSION Common mode voltage generated in PWM inverter output may damage the motor windings, shaft, and bearings. Although, some methods have been developed for completely eliminating common mode voltages (with space vector PWM techniques) which is very complex to implement, it may be possible control it via simple SPWM techniques and their modified forms such as addition of common mode voltage offset to the actual reference voltage wave as presented in this paper. Simulation results show that modified SPWM technique not only controls the THD in output voltage of inverter but also reduces the amplitude, switching transients and frequency of common mode voltages. Simple closed loop PI voltage regulator has been proposed to control neutral point potential without sensing dc capacitor voltages. Experimental work on control of common mode voltage and neutral point potential control is in progress and will be presented in future work. VII. APPENDIX-I: SIMULATION PARAMETERS Load : 50 kW, 1 kVAr (inductive), 400 volts, 50 Hz. Source: 3-phase, 10 MVA, 11kV, 50 Hz. Step Down Transformer :10 MVA, 50 Hz, 11kV/400 Volts. Inverter Output LC Filter : 50 mH, 1 kVar (capacitive). (open loop), and 2mH, 2kVar (closed loop PI regulator) Voltage Regulator Gains: Kp = 0.1, Ki = 10. Switching Frequency: 2 kHz. VIII. ACKNOWLEDGEMENT This work was supported in part by the MHRD sponsored R & D project Development of DSP Controlled Multilevel Inverter, F.26-12/2005, TS V, and AICTE New Delhi under Career Award Scheme for Young Teachers Grant F. No. 151/FD/CA/(011)/2003-05. IX. REFERENCES
[1] Jose Rodrihuez, J. Pontt, et. al, "A New Modulation Method to Reduce Common Mode Voltages in Multilevel Inverters," IEEE Trans. Industrial Electronics, vol. 51, no. 4, pp. 834-839, Aug. 2004. H. Zhang, A. V. Jouanne et. al., "Multilevel Inverter Modulation Schemes to Eliminate Common Mode Voltages," IEEE Trans. On Industry Applications, vol. 36, no. 6, pp. 1645-1653, Nov/Dec 2000. A. K. Gupta, Ashwin M. Khambadkone, A Space Vector Modulation Scheme to Reduce Common Mode Voltages for Cascaded Multilevel Inverters, IEEE Trans. Power Electronics, vol. 22, no. 5, pp. 16721681, Sept. 2007.

X. BIOGRAPHIES
Shailendra Jain received the B.E. degree from Samrat Ashok Technological Institute, Vidisha, India, in 1990, the M.E. degree from Shri Govindram Seksaria Institute of Technology and Science, Indore, India, in 1994, and the Ph.D. degree from the Indian Institute of Technology, Roorkee, India, in 2003. He was a Post Doctorate Fellow at University of Western Ontario, Canada in 2007. Currently, he is Assistant Professor in the Department of Electrical Engineering at Maulana Azad National Institute of Technology (Deemed University), Bhopal, India. His fields of interest include power electronics, electrical drives, active power filters, Fuel Cell technology and high power factor converters. Pramod Agarwal (M99) received the B.E., M.E., and Ph.D. degrees in electrical engineering from the University of Roorkee, Roorkee, India, in 1983, 1985, and 1995, respectively. Currently, he is Professor in the Electrical Engineering Department at the Indian Institute of Technology, Roorkee, India. He was a Lecturer in the Department of Electrical Engineering at the University of Roorkee in 1985 and became an Assistant Professor in 1996. He was a Post-Doctoral Fellow at the University du Quebec, Montreal, QC, Canada, from 1999 to 2000. He has guided more than 50 B.E. and 25 M.E. projects, and published many papers in various national and international journals and conferences. He has developed a number of educational units for laboratory experimentation. His fields of specialization are electrical machines, power electronics, microprocessor- and microcomputer-controlled ac/dc drives, active power filters, and high power factor converters. P. K. Chaturrvedi received B.E. and M.E. degree from Samrat Ashok Technological Institute, Vidisha (MP), India, in 1996 and 2001 respectively. He has been with the department of Electrical Engineering as Lecturer at Samrat Ashok Technological Institute, Vidisha (MP), India. Currently, he is working towards Ph.D. degree at Maulana Azad National Institute of Technology (Deemed University), Bhopal, India. His fields of interest are electrical drives, high power factor converters and multilevel inverters.

[2]

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