University of Portland School of Engineering EE438 Introduction to Digital VLSI Design (3 credit hours) Course Syllabus Spring, 2011

Prerequisites: Lecture Hours: Course Purpose: EE231 and EE351 TR, 2:30pm-3:55pm, Shiley Hall 123 Introduction to digital CMOS VLSI integrated circuit chip design, layout and electrical performance analysis. This is a hands-on practical course with use of simple, intuitive theory. Students will use CMOS VLSI design, layout and analysis CAD tools, specifically: L-EDIT and PSPICE. Topics include CMOS VLSI IC circuit design and chip layout, DRC's (Design-Rule-Checks), layout extraction for chip layout verification (LVS) and PSPICE IC circuit modeling, Other topics include MOS transistors, CMOS gate logic, CMOS scaleable design rules, CMOS chip speed, power and electrical performance considerations, semicustom standard-cell VLSI IC chip design and automated standard-cell IC Place and Route (SPR). Students will complete a modest sized CMOS VLSI IC chip design project through layout, simulation and verification. 1) 2) 3) 4) 5) 6) Instructor: Text: Assessment Tools: Review semiconductor device physics with special emphasis on the MOSFET. Learn digitial VLSI circuit design based on CMOS technology. Cover VLSI design from its origins to present day state-of-the-art. Cover future trends and research in VLSI technology. Learn the basic Planar Silicon CMOS Fabrication Process. Learn CMOS logic and VLSI integrated circuit layout techniques. Learn the Tanner L-EDIT Pro VLSI layout CAD tool. oster@up.edu, https://faculty.up.edu/oster,

Learning Objectives:

Dr. Peter M. Osterberg, Shiley Hall 225, 943-7416 Optional:

Physical Design of CMOS Integrated Circuits Using L-EDIT, John P. Uyemura, PWS Publishing Company, 1995.

15% Homework 20% Design Project 30% Midterm Exam 35% Final Exam 90% - 100% 80% - 89% 70% - 79% 60% - 69% Below 60% = = = = = A A B B+ C C+ D D+ F

Grading Scale:

University of Portland's Code of Academic Integrity: Academic integrity is openness and honesty in all scholarly endeavors. The University of Portland is a scholarly community dedicated to the discovery, investigation, and dissemination of truth, and to the development of the whole person. Membership in this community is a privilege, requiring each person to practice academic integrity at its highest level, while expecting and promoting the same in others. Breaches of academic integrity will not be tolerated and will be addressed by the community with all due gravity (taken from the University of Portlands Code of Academic Integrity). The complete Code may be found in the 2004-05 University of Portland Student Handbook and as well the Guidelines for Implementation. It is each student's responsibility to inform himself or herself of the Code and Guidelines. Accommodation for Disability & Emergency Information: If you have a disability and require an accommodation to fully participate in this class, contact the Office for Students with Disability, located in the University Health Center (503-943-7134), as soon as possible.

Course Outline

Date 1/18 1/20 1/25

Topic Intro to CMOS Digital VLSI Design and L-EDIT L-EDIT Training Day MOSFET and CMOS Inverter layout using L-EDIT including Design Rules, -Rules and DRCs

1/27 2/1 2/3 2/8 2/10 2/15 2/17 2/22 2/24 3/1 3/3 3/8 3/10 3/15 3/17 3/22 3/24 3/29 3/31 4/5 4/7 4/12 4/14 4/19 4/21 4/26 4/28 5/3

Video, CMOS physical design, layout and masks IC Reps, Cross-Sections, Intro to CMOS fabrication CMOS fabrication CMOS fabrication CMOS logic, NAND, NOR, Euler Walk, Ratioing, EXTRACT, LVS IC Parasitics: RLC and interconnect modeling CMOS Compound Gates, Standard Cells MOSFET device theory, DC/AC characteristics The CMOS Inverter, DC/AC characteristics The CMOS Inverter, DC/AC characteristics Exam review Mid-Term Exam Graded exam review Spring Break (no class) Spring Break (no class) CMOS modeling, EXTRACT and PSPICE; Design Project assigned CMOS semicustom chip layout: SPR, tpr file SPR, tpr file, FSM CMOS IC design example SPR, tpr file, FSM CMOS IC design example CMOS full custom, semicustom S/Cs, gate-arrays CMOS Bond Pads, Power and Clock Distribution, Latch-Up CMOS Chip Yield CMOS Scaling Properties; Design Project discussion Founders Day (Please attend Sr Design Presentations) CMOS Design Margining; Design Project due Special Topic: Intro to Nanoelectronics and Thermoelectronics Final Exam review Final Exam (8am-10am)