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DEL620S Notes

1. Further characteristics of flip-flops
1.1Asynchronous Preset and Clear Inputs
Most integrated circuit flip-flops have asynchronous inputs. These are inputs that
affect the state of the flip-flop independent of the clock. These are normally called
Preset(PRE) and clear(CLR), or direct set (S
D
) and direct reset (R
D
)
.

An active level on the preset input will set the flip -flop and an active level on the
clear input will reset it.
A JK flip-flop with preset and clear inputs is shown in fig 1.0.






Fig 1.0 JK flip-flop with PRESET and CLEAR inputs
These inputs are active-LOW, as indicator by the bubbles. That means for them to be
active, the input must be logic 0. For synchronous operation (ie When we want the
flip-flop to be respond to triggering clock), both preset and clear inputs must be kept
HIGH.


1.2 Flip-flops operating characteristics
1.2.1 Propagation delay times
A propagation delay time is the interval of time required after an input signal has
been applied for the resulting output change to occur. These are four categories of
propagation delay;
1. Propagation delay t
PLH
as measured from the triggering edge of the clock pulse to
the LOW to HIGH transition of output Fig 1.1





Fig 1.1 LOW-to-HIGH transition delay time
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2. Propagation delay t
PHL
as measured from the triggering edge of the clock pulse to
the HIGH-to-LOW transition of the output (Fig 1.2).





Fig 1.2 Propagation delay time for HIGH-to-LOW transition
3. Propagation delay t
PLH
as measured from the leading edge of the preset input to
the LOW-to-HIGH transition of output(Fig 1.3).





Fig 1.3 Propagation delay time for Preset input to LOW-to-HIGH transition
4. Propagation delay t
PHL
as measured from the leading edge of the clear input to
the HIGH-to-LOW transition of the output(Fig 1.4).





Fig 1.4 Propagation delay time of the clear input to the HIGH-to-LOW transition of
output.

1.2.2 Set-up Time
Set-up time (t
S
) is minimum interval required for the logic levels to be maintained
constantly on the inputs (of J and K, or S and R or D flip -flops) prior to the triggering
edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop.
(Fig 1.5)






Fig 1.5 Set-up-time
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1.2.3 Hold time (t
h
)
It is the minimum interval required for the logic levels to remain on the inputs after
the triggering edge of the clock pulse in order for the levels to be reliably clocked
into the flip-flop (Fig 1.6).





Fig 1.6 Hold time
1.2.4 Maximum clock frequency
Maximum clock frequency (f
max
) is the highest rate at which the flip-flop can be
reliably triggered. At clock frequencies above the minimum, the flip-flop would be
unable to respond quickly enough, and its operation would be impaired.

1.2.5 Power dissipation
Power dissipation of any digital circuit is the total power consumption of the device.
If the flip-flop operates on a +5V dc source and draws 5 mA of current, power
dissipation is P v

mW
If there are ten flip-flops then
P

mW W
If the flip-flops operate on a 5V dc, then the amount of current that the supply must
provide is I

mA ie. You must use a +5V dc supply that is capable of


supplying at least 50mA of current.

2.0 Counters
2.1 Introduction
Flip-flops can be connected together to perform counting operations. Two broad
categories of flip-flops are:
1. asynchronous counters- also called ripple counters where the first flip flop is
clocked by external clock and the successive flip-flops are clocked by the output
of the preceding flip-flops.
2. synchronous counters The external clock is connected to all flip- flops.




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2.2 A 2-bit Asynchronous Binary Counter






Fig 2.0 2-bit asynchronous counter

Table 1 counting sequence
Clock pulse B A Decimal No.
Initially 0 0 0
1 0 1 1
2 1 0 2
3 1 1 3
4 0 0 0 counting restarts

The flip-flops are positive-edge-triggered. The clock (CLK) is only applied to the first
flip-flop (FF
0
). This counter counts up to 3, so it s a mod-4 counter.

Timing Diagram
Let us examine the operation of the counter Fig 2.1 illustrates the changes in the
output of the flip-flop outputs in response to clock pulse.







Fig 2.1 Timing diagram of 2-bit counter in Fig 2.0







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Both flip-flops are connected for toggle operation (J=K=1) and assumed to be initially
RESET (Q LOW)

The positive-going edge of CLK 1 (clock pulse 1) causes the Q output of FF
0
to go
HIGH. At the same time Q
0
output goes LOW, but it has no effect on FF
1
because a
positive-going transition must occur to trigger the flip-flop. After the leading edge of
CLK1, A = 1 and B = 0. The positive-going-edge of CLK2 causes A to go LOW. Output
Q
0
goes HIGH and triggers FF
1
, causing B to go HIGH. After the leading edge of CLK2,
A= 0 and B = 1. The positive-going-edge of CLK3 causes A to go HIGH again. Output
Q
0
goes LOW and has no effect on FF
1
. Thus after leading edge of CLK3, A= 1 and B =
1. The positive-going-edge of CLK4 causes A to go LOW, while Q
0
goes HIGH and
triggers FF
1
, causing B to go LOW. After the leading edge of CLK4, A=0 and B = 0.
Both flip-flops are RESET. The counter has now recycled.


2.3 4-bit synchronous binary counter










Fig 2.2 4 bit synchronous counter
Fig 2.2 is a synchronous counter which will count from 0 to 15 so this is a mod-16
synchronous counter. We can see that the external clocks are fed directly to each JK
flip-flop. A is the LSB and D is the MSB. When the counting reaches 15 (ie 1111
binary) the flip-flops must all clear, and recounting starts from 0000 on next clock
pulse.






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2.4 Decade 4-bit synchronous counter










Fig 2.3 Mod-10 up counter
Fig 2.3 is a mod-10 counter with a counting sequence of 0 to 9. After reaching a
count of 1001, the counter recycles back to 0000. The additional AND gates detect
when the sequence reaches 1001, and causes flip-flop FF3 to toggle on the next clock
pulse. FF0 toggles on every clock pulse. Thus the counter shorts to count again from
0000.

2.5 Mod-6 ripple counter with manual Reset button









Fig 2.4 Mod-6 ripple counter with manual Reset
The ripple counter in Fig 2.4 will have a counting sequence o 0-1-2-3-4-5 when 6
(binary 110) is reached, the output of the AND gate will go HIGH, causing a NOR gate
to have a LOW output resetting all flip-flops to zero.

As soon as all outputs return to zero, the AND gate output will go LOW, caus ing the
NOR to go HIGH enabling count to restart.
Pushing the manual Reset button will give a HIGH to the NOR gate input amd zero
output at the NOR gate will clear the flip-flops. The 100 ohm resistor will keep the
input to the NOR gate LOW when the push button is in open position.
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2.6 Application example
Let us consider an application that requires an LED indicator to illuminate for 1s
every 13s to signal an assembly line worker to perform some manual operation.

Solution:
First we will used a clock that produces 60 pulses per second (PPS). Then we will
used a mod-10 connected to mode-6 counter.




Fig 2.5
The next step in the design is to use the 1-pps clock to turn on an LED for 1s once
every 13s. It sounds like we need mod-13 counter.




Fig 2.6
2.7 Ripple counter integrated circuit
4-bit binary ripple counters are available in a single IC package. The most
common ones are 7490, 7492 and 7493 TTL ICs.

The 7493 IC
Fig 2.7 shows the logic diagram and pin configuration for the 7493-4-bit binary
ripple counter.












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Fig 2.7 Logic Diagram and pin configuration of 7493.
The 7493 has 4 J-K flip-flops in a single package. Its divided into two sections; a
divide-by-2 and divide-by-8. The second group has 3 flip-flops connected
sequentially to each other and provides a divide-by-8 via CLK1 input and Q
1
Q
2
Q
3

outputs. To get a divide by 16 Q
0
is externally connected to CLK1.

The two Master Reset inputs (MR
1
and MR
2
) are used to asynchronously Reset all
flip-flops. When MR
1
=MR
2
=1, all Qs will be Reset to 0. MR
1
or MR
2
must be held
LOW to enable count mode.

The 7493 can be used to from any modulus counter less than or equal to mod -16
by utilizing the MR
1
and MR
2
inputs.

The 7492 IC









Fig2.8 Logic diagram of 7492.
The 7492 IC (Fig 2.8) is a 4-bit ripple counter consisting of a divide-by-2 section
and divide-by-6 section. Mod-12 can be made by externally connecting Q
0
to
CLK
1
and using CLK
0
as the clock input. A divide-by-6 frequency divider can be
obtained by not connecting CLK
0
, but using CLK
1
.

One peculiarity (strange) of the Mod-12 connection of 7492 is that it does not
count sequentially from 0 to 11; instead it counts from 0 to 13, skipping 6 and 7,
but still functions as a vidived-by-12 counter.

The 7490 IC




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Fig 2.9 Logic Diagram of 7490 IC.
The 7490 IC (Fig 2.9) is a 4-bit ripple counter consisting of a divide-by-2 section
and divide-by-5 section. The two section can be connected together to form a
divide-by-10 counter (Decade counter) by connecting externally Q
0
to CLK
1
. The
7490 is commonly used in applications requiring a decimal (0 to 9) display. In
addition to the MR
1
and MR
2
inputs, the 7490 has Master Set inputs (MS
1
and
MS
2
). When both MS
1
and MS
2
are made HIGH, the clock and MR inputs are
overridden, and the Q outputs will be asynchronously set to a 9 (1001)

3.0 Seven-Segment LED Display Decoder
3.1 Introduction
In the last chapter we discussed counter circuits that can count from 0 to 9. Now
we need to display those numbers.

If the counter is to display a decimal number, the counter on each 4 -bit counter
cannot exceed 9(1001). In other words, the counters must be outputting a
binary-coded decimal (BCD). Recall that a BCD is a 4-bit number used to
represent 10 decimal digits. However for the BCD to be useful, it must be
decoded by a decoder into a format that can be used to drive a decimal numeric
display. The most popular display technique is the seven-sequent LED display.
The job of the decoder is to convert the 4-bit BCD code into a seven segment
code that with turn on the appropriate LED segments to display the correct
decimal digit. For example, if the BCD is 0111 (7) the decoder must develop a
code to turn on the top segment and the two right segments ( ).

3.2 Common-Anode LED display






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Fig 3.0 seven segment display
Fig 3.0(a) shows the physical layout of the seven segment LED display. Note that
the anode of each LED segment is connected to +5V supply.

To illuminate an LED, its cathode must be grounded through a series resistor as
shown in Fig 3.1.




Fig 3.1 illuminating a segment
The voltage drop across LED is 1.7V, and it takes 10mA to illuminate it.

ohm
Common-anode displays are active-LOW (Low-enable) devices become it takes a
LOW to turn on a segment.
The decoder IC used to drive a common-anode LED display must have
active-LOW outputs.

Common-Cathode LEDs and decoders are also available but are not popular.

3.3 BCD-to-seven-segment Decoder or Driver ICs
The 7447 is the most popular common-anode decoder/LED driver (Fig 3.2).




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Fig Logic Symbol for 7447 decoder
Basically the 7447 has 4-bit BCD input and seven individual active-LOW outputs
(one for each LED system). It also has a lamp test (LT) input for testing all
segments, and it also has a ripple blanking input and output (BCI and BCO) are
used to suppress zeros (ie display 1.4 or 01.4 or 0046.0910 or 46.091).

To complete the connection between the 7447 and seven-segment LED, sevem
330 ohm resistors (or eight if decimal point is included) for curren t limiting are
needed. There resistors are usually Dual-in-line package resistor (DIP)









Fig 3.3 Logic Circuit connection for seven segment display
Fig 3.3 shows the logic circuit connection. For example if a mod-10 counters
outputs are connected to the BCD input, and the count is at 6 (0110
BCD
), the
decoder will determine that a 0110
BCD
must send the c, d, e, f, g; outputs
LOW (a, b will be HIGH) for a .
The counter will always count from 0 to 9 when dp is 0V.


3.4 Synchronous up/down-counter ICs
Four-bit synchronous binary counters are available in single ICs. Two popular
synchronous ICs, are 74192 and 74193

74192 and 74193 ICs
These ICs can count up or down that is desired. The 74192 is a BCD diode counter
which counts up or down. The 74193 is a 4-bit binary up/down counter. The
logic symbol of the device is drawn in Fig 3.4.



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Fig 3.4 Logic Symbol of 74192 and 74193 ICs
There are two separate clock inputs namely
Cpu for counting up
Cpd for counting down
One clock must be held HIGH while counting with the other.
Q
0
to Q
3
give binary output count (these are outputs of 4 J -K flip-flops)The
Master Reset for resetting Q outputs to zero. The counter can be preset by
placing any binary value on the parallel data inputs D
0
to D
3
and then driving the
parallel load (PL) line LOW. The parallel load operation will change the counter
outputs regardless of the condition of the clock inputs.

The Terminal Count up TCu and terminal Countdown TCd are normally HIGH.
TCu us used to indicate that maximum count is reached and the count is about
to recycle to zero. The TCu line goes LOW for the 74193 when the count reaches
15 and input clock (Cpu) goes HIGH to LOW. TCu remains LOW until CPu returns
HIGH. The TCu output for 74192goes LOW at 9 and when Cpu goes LOW. The
Terminal Count Down TCD is used to indicate that the minimum count is
reached and is about to recycle to the maximum (15 or 9) count. In this case
TCD goes LOW when the down count reaches zero and the input cloc k CPD goes
LOW.

4.Shift Register
4.1 Introduction
Register are required in digital systems for temporary storage of data bits.

Data bits traveling through a digital system may have to be temporarily stopped,
copied, moved or even shifted to the right or left side.

A shift register facilities this movement and storage of data bits. Shift register can
also be used to convert parallel data bits to serial or vice versa.

Computers operate on data internally on parallel format, but to communicate over a
serial cable like the one on RS232 standard or telephone line data has to be
converted to serial format.

4.2 Parallel-to-Serial Conversion
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The data storage elements can be D, S-R or J-K flip-flops. Let us look at the operation
of J-K flip-flops Registers.

Recall the truth table of JK flip-flops:
J K Q
n+1+
0 0 Q
n
1 0 1
0 1 0
1 1 Q
n
Toggle

4-bit Parallel in-Serial out register










Fig 4.0 4-bit Parallel-to-serial register
Fig 4.0 shows a 4-bit parallel-to-serial register that is first Reset and then parallel
braded with an active-LOW 7(1000) and then shifted right four positions. Note: 7 in
binary 0111.

Because every J-K input is connected to the preceding stage output, then at each
negative edge of clock, each flip-flop will change to the state of the flip-flop to the
left. In other words all data bits will be shifted one position to the right. Initially R
D

goes LOW, resetting Q
3
to Q
0
to zero. Next, the parallel data are input via D
0
to D
3

input lines. Because the S
D
inputs are active LOW, the complement of the number to
be braded must be used. The S
D
must be returned HIGH before shifting can be
initiated. The complement of 7 is 1000.

The serial output data comes out of the right -end flip-flop (Q
0
).