AN027 Using a CMOS Camera with the eCOG1k Version 1.

This application note describes how to interface and use the OV7660-FSL camera module from OmniVision Technology with the eCOG1k development board.

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Confidential and Proprietary Information

Cyan Technology Ltd, 2008 This document contains confidential and proprietary information of Cyan Technology Ltd and is protected by copyright laws. Its receipt or possession does not convey any rights to reproduce, manufacture, use or sell anything based on information contained within this document. Cyan TechnologyTM, the Cyan Technology logo and Max-eICETM are trademarks of Cyan Holdings Ltd. CyanIDE and eCOG are registered trademarks of Cyan Holdings Ltd. Cyan Technology Ltd recognises other brand and product names as trademarks or registered trademarks of their respective holders. Any product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by Cyan Technology Ltd in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded. This document is intended only to assist the reader in the use of the product. Cyan Technology Ltd shall not be liable for any loss or damage arising from the use of any information in this guide, any error or omission in such information, or any incorrect use of the product. This product is not designed or intended to be used for on-line control of aircraft, aircraft navigation or communications systems or in air traffic control applications or in the design, construction, operation or maintenance of any nuclear facility, or for any medical use related to either life support equipment or any other life-critical application. Cyan Technology Ltd specifically disclaims any express or implied warranty of fitness for any or all of such uses. Ask your sales representative for details.

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Revision History
Version V1.1 V1.2 V1.3 V1.4 V1.5 V1.6 V1.7 Date 25/01/2002 10/06/2004 09/08/2004 23/09/2004 04/11/2004 14/02/2005 12/09/2005 Notes Initial revision Document format updated Changed to newer register naming style Corrected clock frequencies Updated list of trademarks Changed font sizes Updated for CyanIDE Updated serial buffer indexing code

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Contents
List of Figures ............................................................................................ 5 List of Tables ............................................................................................. 5 1 2 3 Introduction.......................................................................................... 6 Glossary .............................................................................................. 6 Description........................................................................................... 6
3.1 3.2 3.3 The OV7660-FSL Module.......................................................................... 7 Control Signals .......................................................................................... 8 Clocks and Timing ................................................................................... 10 Hardware ................................................................................................. 11 Software .................................................................................................. 13 eCOG1k Configuration ............................................................................ 14 Memory Organisation .............................................................................. 15 Objects .................................................................................................... 16 Camera Control ....................................................................................... 17 Image Processing and Reconstruction.................................................... 18 SCCB Interface........................................................................................ 18 UART Interface and User Interface ......................................................... 19 Extract the Project from the Archive ........................................................ 20 Start and Configure HyperTerminal......................................................... 20 Start and Configure CyanIDE .................................................................. 20 Program Operation .................................................................................. 20 Example Images...................................................................................... 21

Hardware and Software ..................................................................... 11

4.1 4.2

Software Operation............................................................................ 14
5.1 5.2 5.3 5.4 5.5 5.6 5.7

Example............................................................................................. 20
6.1 6.2 6.3 6.4 6.5

Further Directions .............................................................................. 22 Application Program Interface............................................ 23

A.1 CamInterface.c ........................................................................................ 23 A.2 SCCB.c.................................................................................................... 24 A.3 ymodem.c ................................................................................................ 25 A.4 UARTUtility.c ........................................................................................... 27 A.5 ImageUtility.c ........................................................................................... 29 A.6 utility.c...................................................................................................... 30

Appendix A

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List of Figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Colour filter pattern Camera Daughter Board Schematic Line and Pixel Output Timing Diagram System Functional Overview Menu Options HyperTerminal Receive File Dialogue Example Image 1 7 8 10 11 20 21 21

List of Tables
Table 1. Connections to the OV7660-FSL Camera Daughter Card 12

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1 Introduction
This application note describes an implementation of the OV7660-FSL camera module from OmniVision Technology on the eCOG1k development board. The camera module is implemented as a full colour single shot camera in VGA mode, with support for raw image or bitmap (BMP) output. Control of the application is via the serial port and a simple menu system is provided via a serial port. External SDRAM is used for storage and processing of acquired images.

2 Glossary
A table of abbreviations used in this document. ADC eCOG1 EMI GPIO OV7660 PIO SCCB UART Analogue to digital converter Cyan Technology target microcontroller External Memory Interface General Purpose Input/Output OmniVision Camera chip Parallel Input/Output Serial Camera Control Bus Universal Asynchronous Receiver Transmitter

3 Description
This application is a basic implementation of the OV7660-FSL camera module using the Cyan Technology eCOG1k microcontroller. The application is designed as a single shot camera with a resolution of 640x480 (VGA) in 24-bit colour. The camera is controlled by programming the internal registers of the OV7660 via the SCCB control interface. Data is captured by the eCOG1k via parallel I/O and stored directly in external SDRAM, allowing the capture of up to 16Mbytes of image data via the digital video port. All data processing is carried out on the eCOG1k including reconstruction and conversion to bitmap format for direct output. The application provides the following features 640x480 (VGA) mode resolution UART Interface Image capture directly to SDRAM On chip image reconstruction Supports Bitmap (.bmp) format output Robust serial transmission via YModem transfer protocol

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3.1

The OV7660-FSL Module

The OV7660 is a 320K pixel digital CMOS sensor designed for video and still image capture. The sensor consists of 640x480 pixels and incorporates a fast 10-bit ADC. The OV7660-FSL is a module that incorporates the OV7660 camera chip, lens, and connectors.

3.1.1

Array Organisation

The OV7660 CMOS sensor array contains a total of 640x480 pixels. The colour filters for the pixels are arranged in a Bayer pattern (see Figure 1). In the cameras raw data mode, the device performs analogue to digital (A/D) conversion on a pixel-by-pixel basis, working along each row and outputting the data after each conversion. Using this mode, a maximum frame rate of 7.5fps can be achieved when using a 24MHz clock.
Column 0 Row 0 Row 1 Row 2 Row 3 G R G R 1 B G B G 2 G R G R 3 B G B G 478 G R G R 479 B G B G

Row 638 Row 639

G R

B G

G R

B G

G R

B G

Figure 1.

Colour filter pattern

3.1.2

Supporting Hardware

The OV7660-FSL requires three power supplies, including an I/O voltage that can range between 2.25V and 3.6V (depending on the requirements of the host system), a 2.5V analogue supply, and a 1.8V digital supply. The 3.3V supply from the eCOG1k development board can be connected directly to the I/O supply on the OV7660-FSL. This ensures that the image samples and signals used by the microcontroller meet its voltage level switching requirements. One possible solution for the other power supplies is to use the National Semiconductor LP5900-SD2.5 regulator to generate the 2.5V analogue supply, and the LP5900-SD1.8 regulator to generate the 1.8V supply. These devices and supporting documentation (including details of required decoupling capacitors and board layout) can be obtained directly from National Semiconductor. The 3.3V system voltage can be used as the input voltage to both of these regulators. The connections on the OV7660-FSL are fine pitch (0.5mm), and a MOLEX524372491 flat-flex cable connector is required. This application note uses a small daughter board to support both the MOLEX524372491 adaptor and the regulators described above. The schematic for this daughter board is shown in figure 2.

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Figure 2.

Camera Daughter Board Schematic

The J1 connector shown in figure 2 is a standard 20-pin (2x10) socket. This can be interfaced with a 2.54mm pitch male connector, fitted to the eCOG1k development board in the matrix of through-hole pads in the prototyping area. The signal connections between J1 and the eCOG1k are detailed in section 4. Samples of the camera daughter board can be obtained from Cyan Technology Ltd upon request. If the target system directly incorporates the MOLEX524372491 connector, then socket J1 is not required.

3.2

Control Signals

This section describes the different control signals available as outputs from the OV7660 module, as used in this application. Refer to the OmniVision website for a complete datasheet for the OV7660 at www.ovt.com. Section 4.1.4 contains a schematic and connections for the example described here.

3.2.1

Reset and Clock

For synchronous operation, the external clock input XCLK1 is connected to the EMI clock output of the eCOG1k, operating at 50MHz. This allows completely synchronous operation with the application software, and facilitates precise timing for data acquisition. Hardware reset and power down are also provided as external inputs. They are connected to the eCOG1k via GPIO4 and GPIO5 respectively, allowing supervisory hardware control via software by asserting these outputs.

3.2.2

SCCB Interface

The device uses an implementation of a serial control bus for serial communication between the OV7660 and the host processor. This is predominantly used for programming of the OV7660 control registers for different device configurations and options. This interface is termed the Serial Camera Control Bus or SCCB and is very similar to the I2C standard. The bus consists of two connections: a clock signal, SIOC, connected to GPIO13 on the eCOG1k, and a data signal, SIOD, connected to GPIO14 on the eCOG1k. Refer to the document OmniVision Serial Camera Control Bus (SCCB) Functional Specification, available from the OmniVision website, for a complete description. The device ID is 0x42 for write and 0x43 for read.

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3.2.3

Digital Video Port

After configuration, the OV7660 outputs frames at a constant rate via the digital video port. Four signals and a data bus are provided as outputs from the OV7660 to allow the host system to synchronise with the incoming data. The polarity of all of the framing signals is selectable via the OV7660 registers. The digital video port can also be configured to work in slave mode by providing the clock, horizontal sync and vertical sync signals externally. VSYNC This is the vertical synchronisation output signal. By default, the signal is asserted once per frame for 4 times the line duration, a short time prior to the assertion of the HREF signal. The main purpose of the signal is to provide the host system with a signal to indicate that a new frame is about to be transmitted, and to allow enough time for the system to configure itself prior to receiving data. HSYNC This is the horizontal synchronisation output signal. The signal is asserted a few hundred pixel clocks prior to the assertion of HREF (see below), and is deasserted a few hundred pixel clocks after the deassertion of HREF. The signal is deasserted between the transmissions of each horizontal scan lines for 80 pixel clock periods. The signal is used to synchronise the host to allow it to prepare for the receiving of the next scan line. The number of HSYNC assertions in a frame is equal to the number of scan lines. HREF This is the horizontal reference output signal. The signal is asserted synchronously with the start of the scan line data and de-asserted once the entire line has been transmitted. The signal is used to indicate the precise start and end of the scan line data, and is asserted the same number of times per frame as there are scan lines. PCLK This is the pixel clock output signal. The image data signal is clocked at the pixel clock output frequency. This signal is used by the receiving system to clock in each pixel in an image. Data Bus The data interface from the sensor array ADC is via an 8-bit parallel data bus, offering a maximum 24-bits colour per pixel. The data is configurable to output either the most or the least significant bit at D0.

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3.3

Clocks and Timing

This describes provides a basic overview of the detailed timing and operation of the OV7660 camera. Datasheets providing more a detailed description can be obtained directly from Omnivision.

3.3.1

Clocks and Frame Rate Adjustment

The OV7660 is designed to run from a 48MHz or 24MHz source. An internal frequency doubler is available to generate 48MHz from a 24MHz source. Registers are available to adjust the clock rate by use of a divider, offering a maximum divider ratio of 64:1, giving an operational speed of ~390kHz when using a 24MHz system clock. Dummy lines and pixels can be added to further decrease the frame rate by inserting extra sample spaces before data is output.

3.3.2

Line/Pixel Timing

The line/pixel timing is effectively the same for each mode of operation when operating the device in master mode. Figure 3 shows a basic diagram of the timing of the signals for the digital video port.

Figure 3.

Line and Pixel Output Timing Diagram

On the first line of an image, VSYNC is asserted and deasserted to indicate that a new frame is about to begin. Next, HSYNC is asserted, followed some time later by HREF. Data transfer starts synchronously with HREF, and PCLK clocks each bit of the data. HREF is de-asserted immediately following the last pixel data transmission, and HSYNC is deasserted some time later. The HSYNC and HREF signals are then asserted for the next line.

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4 Hardware and Software

4.1
4.1.1

Hardware
Functional Overview

Figure 4 is a graphical overview of the functional components of the application, and the following sections contain a description of the hardware used.
PC User Interface

UART

DV Port OV7660-FSL Daughter Card SCCB Ctrl/Pwr/Clk eCOG1k

Emem0 Emem1

32M SDRAM Image Storage

Figure 4.

System Functional Overview

4.1.2

PC to eCOG1k Development Board

This application requires the eCOG1k development board to be connected to the PC, with a serial port for communication and either the parallel or USB cable for debugging and programming, as required for the board in use. The serial port is configured in the application software for 8 data bits, no parity, 1 stop bit and no flow control.

4.1.3

eCOG1k Development Board (Iss 2.1) Configuration

Prior to using the application, it is necessary to configure the development board such that other onboard peripherals do not interfere with the correct operation of the application. The following steps must be taken prior to using the development board with this application. Remove all jumpers on J20 to disable the onboard LEDs. Remove J9 to disable the onboard speaker. Ensure all switches (SW2) are set to the off position.

4.1.4

OV7660 Daughter Card to eCOG1 Connections

Table 1 shows example connections between the OV7660 daughter card and the eCOG1k development/evaluation board. The table shows the flat-flex connector pins and functions for the OV7660, the IC pin, port and software functions for the eCOG1k, and the header and pin connections for the development board. The interface uses an 8-bit parallel input/output port connected to the least significant byte of PIOB. The HREF, VSYNC, SCCB and hardware reset signals are connected to GPIO signals. The external clock input is connected to the EMI clock output and the 3.3V supply input is connected to the power supply regulators.

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CAMERA DAUGHTER CARD Pin Signal 1 V33 2 V33 3 SIOC/SERIAL_CLK1 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SIOD/SERIAL_DTA1 CAMERA_D0 CAMERA_D1 CAMERA_D2 CAMERA_D3 CAMERA_D4 CAMERA_D5 CAMERA_D6 CAMERA_D7 CAMERA_VSYNC CAMERA_HREF CAMERA_PWDN CAMERA_RESET CAMERA_PCLK EMI_CLK AGND GND

Port C0 C1 K0 K1 K2 K3 K4 K5 K6 K7 A1 A3 1 A4 A5 A0 I7 -

Pin 58 59 77 78 83 84 20 19 14 13 41 43 44 45 40 93 -

eCOG1k Signal 3.3V 3.3V GPIO_13 (out) GPIO_14 (in/out) PIOB_0 PIOB_1 PIOB_2 PIOB_3 PIOB_4 PIOB_5 PIOB_6 PIOB_7 GPIO_1 (in) GPIO_3 (in) SETUP_0 SETUP_1 GPIO_0 (in) EMI CLOCK GND GND

Dev Board Header Pin J11 J11 J22 J22 J22 J22 J22 J22 J22 J22 J11 J11 J11 J11 J11 J12 26 27 11 12 13 14 15 16 17 18 9 11 12 13 8 29 -

Table 1.

Connections to the OV7660-FSL Camera Daughter Card

Note that analogue and digital grounds AGND and GND may be connected together on the Development Board.

4.1.5

Additional Connections

The interface described in section 4.1.4 uses only the VSYNC and HREF signals for synchronisation by the software, and relies on explicitly timed software control for image line acquisition. Additional connections such as the slave interface can be connected directly to eCOG1k GPIO pins. The additional data bits can be interfaced with the most significant byte of the 16-bit PIO ports on the eCOG1k microcontroller. Note that port K is not available on the eCOG1i device used on earlier development boards, and it is not possible to use the lower byte of PIO B when using this device with the EMI peripheral enabled. While additional GPIO connections could be used in this case, the additional data acquisition and processing overhead would be very large in comparison to using only the PIO functions.

This has been updated for Iss2.1 as it is hard wired to the DAC output pin.

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4.2
4.2.1

Software
Application Software

This application is built using CyanIDE V1.3, which is available for download from www.cyantechnology.com/support/updates.php. The example software application to accompany this application note is also available from the application notes page as AN027SW.zip.

4.2.2

Additional Software

This application uses an external terminal program for communication with the eCOG1k via the serial port. The terminal program is used for transmitting control codes to the eCOG1k for device configuration and control, and for receiving image data from the eCOG1k after acquisition. This application has been tested using HyperTerminal under Windows 2000 and Windows XP.

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5 Software Operation
This section describes the operation of the application software. The application is designed as a still image camera with VGA resolution, using the SDRAM as temporary storage and processing memory for the images. All processing and reconstruction is carried out by the eCOG1k and the image data is transferred via the UART. A simple menu system is provided via the UART offering control of the user application. The application code is organised into a modular structure, with modules for object definition, utilities, image utilities, camera interface, SCCB interface and the UART. Assembly code routines are also provided for acquiring single lines or single frames. These modules are designed to be expandable. Two versions of the camera application software are available. The first (AN027SW.zip) supports the Bitmap imaging format. The second (AN028SW.zip) also supports JPEG compression, and is described in more detail in application note AN028.

5.1

eCOG1k Configuration

The eCOG1k is configured to run at 25MHz from the high reference PLL. The EMI is configured to connect to the external SDRAM using a 25MHz synchronous clock. UART A is configured to operate at 115,200 baud, with 8 data bits, no parity, 1 stop bit and no flow control. To maximize operational speed during acquisition, program execution is from the internal SRAM instruction cache. To achieve this, the application code is copied to the instruction cache, which is subsequently locked. This is performed in the ASMGetFrame() function of the CamInterface.c file, before the acquisition routine is executed. The eCOG1k architecture implements a pre-fetch system for each instruction, such that the next instruction is fetched while the current instruction is being executed. When using a locked cache memory, the result is deterministic behaviour, and execution can be precisely timed and repeated.

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5.2
5.2.1

Memory Organisation
Overview

The application code has access to 32Mbytes of external SDRAM on the eCOG1k development board for temporary storage of acquired images. The memory is addressed via two internal address translators with a size of 32Kbytes (0x4000 words) each. These translators can be used together as a 64Kbyte block as used in the frame capture assembly code, or separately when input and output memory are required such as when converting one image format to another. Mapping between contiguous blocks (paging) is provided where required by each function and generic functions are provided for memory management. Previous software versions included dynamic memory mapping of the MMU module during acquisition to provide a robust interface, allowing acquired data to be sequentially stored in SDRAM. The acquisition software automatically remapped SDRAM when the end of the translator block was reached, as part of the acquisition loop. This involved executing a number of NOPs (no operation) whenever an MMU update was not required, and significantly increased the size of the acquisition software and execution time. While this feature is useful, only 1 in 16384 cycles require the translators to be remapped, and thus the acquisition loop was largely redundant. To improve the speed of the acquisition loop, this feature has been removed, and memory mapping is now performed only after a complete line has been acquired. This results in a large reduction in the size of the timing critical loop, and a subsequent large increase in acquisition speed. The entire time-critical pixel sampling loop now occupies only five assembly language instructions, and is executed within eight instruction cycles. The OV3620 interface (i.e. the previous camera module) relied on either fitting an image within one mapped MMU block, or performing a memory mapping operation every 16 lines (i.e. for 16384 image bytes). The 1024 samples generated by the OV3620 per line, allowed this boundary to fall conveniently at the end of a line. However, the set of 640 samples per line generated by the OV7660 module does not meet these conditions, and therefore may result in a memory exception whilst the MMU attempts to access data outside its current configuration. An updated version of the software tests how much memory is available within the currently mapped block at the end of each line, and maps in a new block of memory if there is insufficient memory to hold a complete line. This same process must also be performed when building the acquired image into bitmap format.

5.2.2

SDRAM Interface

Images are acquired and stored directly to SDRAM, which requires continuous refreshing to ensure data integrity. This must be carried out periodically, and is usually under the automatic control of the eCOG1k SDRAM interface. When acquiring data sequentially, this cycle can often interrupt the periodicity of the sampling process, resulting in missing data and image corruption. To avoid image corruption, hardware controlled automatic refresh is disabled during frame acquisition, and instead auto refresh is performed manually after every line acquisition. The SDRAM data sheet specifies that refresh must be carried out for 4096 rows every 64ms. If two frames are acquired per second (based on XGA mode, 25MHz using divide by 10), then the system acquires 1536 lines per second. This means that 42 SDRAM rows are refreshed after every line, requiring a refresh period of 1024 under normal operating conditions (hardware control). This configuration ensures that the memory contents are maintained whenever the frame rate is maintained. To allow user control of refresh burst timing, manual refresh is performed by setting the refr_per register of the EMI interface to zero. When the hardware auto refresh function is subsequently enabled, the interface immediately begins refreshing the specified number of rows (determined by ref_cnt). If the interface is disabled immediately, the auto refresh continues to execute the current refresh burst and automatically disables when complete, thus allowing manual software control of the timing of the refresh bursts. See AN003 eCOG1k SDRAM Interface for more information on the SDRAM interface and refresh techniques.

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5.3

Objects

Three structure prototypes are provided for use within the application, designed to offer a common method of accessing object properties to allow ease of implementation. Functions that use the objects are passed pointers to the object. These objects can be empty after creation. In an environment using malloc() and free(), these structures can be used to allow option profiles to be created, and to manage an image file system effectively.

5.3.1

Camera Object

This structure provides options for the configuration of the camera and is used by the camera interface for initialisation and image acquisition. Options are currently provided for acquisition mode, internal clock divider (and hence module speed) and windowing size. The options have to be set explicitly and passed when initialising the camera or changing the settings.

5.3.2

Image Object

This is a generic structure designed to contain information about an image and point to the image in memory. The structure contains information on the dimensions of an image, the file size of the image and a pointer to the location of the image in the external SDRAM. The structure does not form part of the image, it only contains the image properties and is updated automatically when acquiring or processing an image. Several of these structures could be allocated in memory using malloc() to provide multiple image support.

5.3.3

Bitmap Object

This is a specific structure indicating the properties and parameters of a bitmap image in SDRAM. The object properties indicate the complete structure of the bitmap image, including the size, dimensions, resolution and colour information. It is different from an image object in that it actually forms part of the image, and all fields are written as they are stored in littleendian format. The bitmap object is updated with information from the image object as part of the bitmap creation process. As with image objects, multiple bitmap objects could be allocated in RAM if required.

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5.4

Camera Control

The camera control is provided by a set of C functions and assembly code routines that jointly provide initialisation, configuration and acquisition of images.

5.4.1

Camera Initialisation

The initialisation routines use the SCCB interface to configure the OV7660 to the required mode of operation, and contain all of the necessary register writes to initialise the device correctly. The routines reset the camera module before checking the device ID via the SCCB interface. If this is not recognised then the routine returns an error. If the device is recognised then the registers are programmed with option specific parameters. This module is expandable when using different hardware. The normal operation of the camera is set to filter 60Hz flicker, at a frame rate of 7.5 frames per second. This ensures that the effects of mains flicker are synchronised with the frame rate (this is a requirement of the filtering algorithms performed by the OV7660). Lines per frame Sync between lines Total line durations per frame Pixels per line Delay per line Total PCLK per line Total PCLK per frame PCLK Frequency Hz PCLK Divider Frames per second 480 30 510 640 144 784 399840 24000000 8 7.50 Frames per second PCLK periods PCLK periods PCLK periods PCLK periods

The camera is however operating at 25MHz (EMI_CLK); and should be set for 50Hz mains flicker (in the UK and Europe). This requires the frame rate to be reduced to 6.25 frames per second by adding dummy lines and dummy pixels. Lines per frame Sync between lines Dummy lines per frame Total line durations per frame Pixels per line Delay per line Dummy pixels per line Total PCLK per line Total PCLK per frame PCLK Frequency Hz PCLK Divider Frames per second 480 30 126 635 640 144 3 787 499745 25000000 8 6.25 Frames per second PCLK periods PCLK periods PCLK periods PCLK periods PCLK periods

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5.4.2

Frame Capture

The frame capture interface exploits the predictability of the eCOG1k instruction cycle timing. The entry point is at the start of the assembly code function and the address translator is pointed at the first block to be written. After initialisation, the processor then begins by waiting for VSYNC high, indicating the beginning of the image frame. Once the VSYNC high is received, the SDRAM automatic refresh is disabled. Each line acquisition begins with an initial wait for the HREF low-high signal transition. The software then proceeds into a critically timed pixel acquisition loop for the duration of the line, sampling the current pixel value once per loop. For each loop the current pixel value is sampled and stored in the next available memory location, and the pointers are incremented. After each line has been acquired, the following sequence of events follows: 1. An automatic refresh burst is applied to the SDRAM 2. The end of frame is checked. If found, then the hardware automatic refresh is reenabled, registers are restored, and control returned to the calling function. 3. The current position within the MMU translator block is checked, and if the end has been reached then the next MMU block is mapped. 4. The software returns to waiting for the HREF signal, ready to acquire the next line.

5.5

Image Processing and Reconstruction

The captured images are stored as raw data in the Bayer pattern as they are acquired. A simple reconstruction technique is implemented in software to obtain a 24-bit RGB image when required. For raw data, the pixel sample values are output exactly as they are acquired, in the pattern described in section 3.1.1. A simple RGB reconstruction is then performed; where each line is scanned 640 times and the nearest red, blue and green values are extracted from the raw image. In the case of the green value, an average of the two adjacent green samples is taken for every other pixel (i.e. when the raw image is either red or blue in the Bayer pattern). This ensures that no information is lost during the reconstruction process. The software also allows the addition of a bitmap header to the data such that a bitmap image file can be created completely on the eCOG1k. Image storage requirements for an original 640x480 acquisition are: 307.2K words for the original Bayer image (upper half of 16 bit word is not used) 921.6K bytes for the reconstructed RGB image (plus 54 bytes BMP header) The Windows bitmap format uses the Intel machine little-endian byte ordering for storage of image data. When using 24-bit data, this requires that each reconstructed RGB component is re-ordered such that the data is stored in BGR data component order. This involves a time delay when creating the bitmap file from the reconstructed image data. This delay could be reduced by modifying the image reconstruction routine to output data directly in BGR byte order instead of RGB. The bitmap creation routine then needs only to generate and append a header to the image data for output, which would significantly reduce the time required for image generation. The mapping of an image into the compressed JPEG format is also supported by the application software, and is described in application note AN028. This achieves considerable image compression, reducing the 640x480 image to approximately 30Kbytes of storage.

5.6

SCCB Interface

The OV7660 incorporates a serial interface for reads from and writes to internal registers. The example software contains routines for reading and writing these registers according to the manufacturers protocol.

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5.7

UART Interface and User Interface

The application uses the UART for communication with a host PC and to provide a basic user interface for control of the application. The menu function acts as the front end of the application, and is responsible for controlling the use of the various data objects within the code. The user interface is responsible for calling the necessary routines based on the user selection. The options are as follows. 1. Display this menu 2. Request a bitmap image 3. Request a JPEG image Options 2 and 3 above are used to map the captured image to the specified format, and transfer the image to the host PC for viewing. This is achieved by YModem transfer protocol for robust transmission of the image data to the host PC. This file transfer is supported under HyperTerminal, and is controlled by the application software.

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6 Example
This section describes an example using the application software. The example covers the acquisition of a single image, reconstruction, conversion and output to a PC. This example is based on the OV7660 Daughter Card connected to an eCOG1K development kit and a PC using the method described in section 4.

6.1

Extract the Project from the Archive

The software for this example application is available in a zip file <AN027SW.zip>, which can be downloaded from the Cyan website at www.cyantechnology.com, on the application notes page. Extract the example application files from the archive to the CyanIDE examples directory, usually <C:\Program Files\Cyan Technology\ CyanIDE\examples\eCOG1 dev board\>.

6.2

Start and Configure HyperTerminal

Start HyperTerminal and configure it to use the correct COM port with settings of 115,200 baud, eight data bits, no parity, one stop bit and no flow control. Then connect HyperTerminal to the port.

6.3

Start and Configure CyanIDE

Launch CyanIDE and open the project file OV7660.cyp, using Project->Open from the main menu. The application software contains pre-built ROM image files that can be directly downloaded to the target system without needing to rebuild the application software. If required, the software can be rebuilt by selecting Build->Rebuild All from the menu. Run the software by selecting Debug->Run from the menu or by pressing F5. The software is downloaded to the development board and execution starts.

6.4

Program Operation

When run, the application begins by sending the program version information to the serial port, followed by the user menu indicating the following options:

Figure 5.

Menu Options

Status information is then provided via the HyperTerminal window on the progress made in acquiring an image and processing the image into the required format (i.e. Bitmap or JPEG). Once the image is ready to be transferred, a prompt message is displayed to indicate that the YModem transfer is about to begin. This waits until the transfer is started from the HyperTerminal menu.

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From the HyperTerminal menu, select Transfer->Receive File to open the file received dialogue. Change the Use receiving protocol: to YModem and select the destination as shown in Figure 6. Note that the YModem protocol requires the filename to be sent in the first packet, and the application software deals with correctly naming the file and extension, therefore it is not necessary to include the target filename. Then press the Receive button to initiate the transfer.

Figure 6.

HyperTerminal Receive File Dialogue

A progress dialogue appears indicating the current state of the transfer, including the number of packets sent and information on any errors that occur. The dialogue is closed on successful completion of the file transfer. The image file is then available for viewing in the chosen destination folder, with the filename <OV7660_OUT.bmp>.

6.5

Example Images

The following image was acquired using the method described above. The image is representative of a 640x480 image acquisition in 24-bit colour, stored as either a bitmap or JPEG image.

Figure 7.

Example Image 1

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7 Further Directions
Images are currently stored in volatile SDRAM. These images are stored incrementally at locations throughout memory. A simple file system could be used, within a volatile memory, to allow the management of the images in memory, although this is beyond the scope of this document.

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Appendix A Application Program Interface

A.1 CamInterface.c

int InitialiseCamera(OPTION_PTR options) This function is responsible for the initial configuration of the camera module prior to use. The function starts by forcing a hard reset that returns the camera module to default operation, and then entering the manufacturers recommended configuration. Any previous camera parameters are permanently discarded. Parameters options Returns TRUE for successful initialisation, FALSE if initialisation fails. Example
if (InitialiseCamera (options)) { // Success ... } else { // Initialisation failed, error ... }

Pointer to a structure containing camera configuration options

void GetFrame(OPTION_PTR options, IMAGE_PTR image); This provides a wrapper function for the assembly code routine that captures individual lines from the camera. The camera module must be correctly initialised before using this function. The function also maps in the correct memory address to point to the location of the image and turns off the cache. Directly calls the assembly code routine asm_get_frame to acquire the image before turning the cache back on. Parameters options image Returns None Example GetFrame(options, image1); Pointer to a structure containing camera configuration options Pointer to a structure containing image acquisition parameters

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A.2

SCCB.c

int SCCB_wr(unsigned char address, unsigned char data); Write to a camera register using the SCCB interface. This function writes correctly to a register using the specification described in the SCCB documentation. Parameters address data Returns TRUE on successful completion. Example
// Set the AGC gain to 1 int SCCB_wr(0x00, 0x80);

Address of the register to be written Data to be written to the specified register address

unsigned char SCCB_rd(unsigned char address); Read a camera register using the SCCB interface. This function reads correctly from a control register using the SCCB specification. Parameters address Returns The current value of the register specified by address. Example
// Read the AGC gain value AGC_gain = SCCB_rd(0x00);

Address of the register to be read

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A.3

ymodem.c

int YM_init(int timeout, int mr); Initialises the YModem session. This initialisation routine should be used to ensure correct configuration prior to performing any operations using the ymodem transmit or receive functions. This function configures counter 1 (cnt1) for use as the timeout counter. Parameters timeout mr Returns S_INIT if the initialisation was successful. Example
// Initialise YModem for 2 second timeout, and 10 retries if (S_INIT != YM_init (2048, 10)) { // Error ... }

Specifies the time allowed for the software to transmit or receive a packet in 1/1024 second intervals Maximum number of retries allowed before the operation is abandoned

int YM_rxp(unsigned int *packet_buff); Receives a packet using the YModem protocol. The function returns when the data is received correctly or on a fatal error. Retransmission is requested automatically and error handling is provided internally. The YModem transfer must be initialised with YM_init() before calling this function. Parameters *packet_buff Returns S_PKT128 S_PKT1024 S_EOT S_MAXRETRY Example
// Loop till end of file received do { r = YM_rxp (packet_buffer); if (S_MAXRETRY == r) { // Transmission channel too noisy? ... } // Packet received, do some work ... } while (S_EOT != r)

Pointer to the buffer into which the received packet is stored

if a 128 byte packet is successfully received. if a 1024 byte packet is successfully received. if the end of transmission packet has been successfully received. if the maximum number of retries has been exceeded.

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int YM_txp(unsigned char *packet_buffer, int packet_length); Transmits a packet using the YMmodem transfer protocol. Error handling and packet retransmission is controlled internally. End of transmission is initiated by setting the packet length to 0. The first packet contains the destination filename in ASCII format, padded to the length of the packet with zeros. The second packet sent is the first data packet. The YModem transfer must be initialised with YM_init() before calling this function. Parameters *packet_buff packet_length Pointer to a character array containing the data to be transmitted The length of the packet to be transmitted. Integer values up to 1024 are allowed. The value 0 is reserved for EOT transmission. Any other value returns an error.

Returns S_OK S_MAXRETRY Example

unsigned unsigned unsigned unsigned char char char char *filename_ptr = YM_out.txt; *tx_buffer; // Pointer to packet transmit buffer *bufptr; // Buffer pointer *outbuf; // Pointer to transmit data in memory

if a packet was transmitted successfully. if the number of retries exceeds the maximum allowed.

// Create the filename packet do { *bufptr++ = *filename_ptr++; c = *filename_ptr; } while (c != '\0'); // Pad out to end of packet (128) with 0x00 while (bufptr < (unsigned char *)(tx_buffer + 0x80)) { *bufptr++ = 0; } bufptr = tx_buffer; // Reset the buffer pointer r = YM_txp(tx_buffer, 128); // Transmit filename packet // Now transmit the file data via the buffer // Transmit the remaining packets, i.e. the file do { // Determine the length of the packet to transmit packlength = 1024; if ((length - i) < 1024) { r = S_EOT; packlength = (int)(length - i); } // Copy the next packet of data to the buffer // Note that file variables are all controlled in this loop bufptr = tx_buffer; // Reset the buffer pointer for (j = 0; j < packlength; j++) { *bufptr++ = *outbuf++; } // Transmit the packet and update the variables r = YM_txp(tx_buffer, packlength); file_ptr += packlength; i += packlength; } while (i < length); // Send EOT, which will be ACK'd followed by the null packet r = YM_txp(file_ptr, 0);

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A.4

UARTUtility.c

void UART_UI(OPTION_PTR options); UART user interface. Provides external control of the application via the serial port and a simple text menu. This is the main user interface for the application. Camera and image objects are created, updated and maintained within the routine. A structure containing the camera options must be created and the camera initialisation must be performed prior to calling this function. Parameters options Returns This function never returns. Example
CAMERA_OPTIONS options1; // Configuration - Parallel IO fd.io.p_cfg.b_dis = 1; // Disable output - PIO input // Set the options to use in this example options1.frame_start_h = 0; options1.frame_size_h = 640; options1.frame_start_v = 0; options1.frame_size_v = 480; options1.mode = VGAMode; // VGA Mode options1.divider = 0x3b; // Divide by 60 cam_init(&options1); // Run initialisation routines cam_defaults(&options1); // Set Camera default options UART_UI(&options1); // Launch the user interface

Pointer to a structure containing camera configuration options

int RawSendFile(unsigned char *address, unsigned long size); Transmits a file in external memory via UART A. This is primarily intended to output image data via the serial port where no transmission channel errors are present and a suitable capture program is running on the destination host system. Parameters *address Size Returns TRUE on successful completion Example
// Wait 5 seconds then transmit the image stored as object image1 msec_delay(5000); RawSendFile(image1.address, image1.size);

Pointer to the byte address of the file to send The length of the file in bytes

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int YMSendFile(const char *filename, unsigned char *file_ptr, unsigned long length); Transmits a file in external memory via UART A using the YModem protocol. Provides all the necessary address translations, packet creation and ordering, buffering and error control for complete file transmission from SDRAM via the UART. Parameters *filename *file_ptr Length Returns S_OK on successful file transmission. Example
// Transmit the bitmap image object bmp_image1 using Ymodem YMSendFile("OV7660_OUT.bmp", bmp_image1.address, bmp_image1.filesize);

Pointer to a character array containing the name of the destination file. Byte pointer to the start of the file The length of the file to transmit in bytes

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A.5

ImageUtility.c

void ImageReconstructRGBFast(IMAGE_PTR image); Reconstructs an image stored as a Bayer pattern into a 24-bit RGB image using a fast method. This function implements a simple reconstruction method. Single Red, Green and Blue pixels are extracted from each block of 4 pixels and stored as 24-bit colour samples. The original image is replaced by the reconstructed image. The image dimensions are reduced to half of the original and memory requirements are reduced to 75% of the original. Parameters image Returns None Example
ASMCamGetFrame(options, &image1); ImageReconstructRGBFast(&image1); // Get an image frame // Reconstruct the image

Pointer to the Bayer image data structure in memory

void CreateBMP(IMAGE_PTR image, BMP_PTR bmp_image); Creates a bitmap (bmp) image from a reconstructed image. A new bitmap image is generated from a reconstructed RGB image by adding the bitmap header to the image. The original image is unchanged. The bitmap image output file has a standard header and an array of BGR ordered (little-endian) data samples. Parameters image bmp_image Returns None Example
IMAGE_PTR image1; BMP_PTR bmp_image1; ASMCamGetFrame(options, &image1); ImageReconstructRGBFast(&image1); CreateBMP(&image1, &bmp_image1); // Get an image frame // Reconstruct the image // Create a bitmap image

Pointer to a structure describing an RGB image Pointer to an object describing a bitmap

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A.6

utility.c

void MapSDRAM(int translator, unsigned long logical, unsigned long physical, unsigned long size); Updates the current SDRAM (external chip select 0) translators to map in the requested memory. This function overwrites any previous mappings assigned to this translator, which may make some memory temporarily unavailable. The function arguments must be the actual values required. The bit shifts required for the MMU register values are controlled by the function. Parameters translator logical physical size Returns None Example
// Map 0x4000 words of SDRAM at address 0x0000 to logical address 0x8000 MapSDRAM(0, 0x8000, 0x0000, 0x4000);

The translator to use, either 0 or 1 The logical address for the mapped memory The physical address in SDRAM to be mapped The size of the block of memory to be mapped

void FlipBytes(unsigned char *address, int size); Flips the endianness of a group of bytes. This function is used internally by the BMP conversion process as Intel architectures require data to be stored in little-endian byte order. Parameters *address size Returns None Example
// Loop through image and reverse RGB to BGR for (a = start, a < end, a += 3) { FlipBytes(image_buff[a], 3); }

Pointer to the address of the data to reverse The number of bytes (eight bits) to reverse

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void msec_delay(int c); Waits for the specified number of milliseconds. This function requires the timer (tmr) peripheral. The delay parameter represents a number of 1/1024 second intervals. Parameters c Returns None Example
// Wait 5 seconds msec_delay(5000);

Delay time in units of 1/1024 seconds

usec_delay(int c); Waits for the specified number of microseconds. This function requires the timer (tmr) peripheral. The delay parameter represents a number of 1 / (0.96X106) second intervals. Syntax: Parameters c Returns None Example
// Wait 100 microseconds usec_delay(100);

Delay time in units of 1 / (0.96X106) seconds

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