CMOS Technology Scaling

Navakanta Bhat Associate Professor ECE Department, IISc

Navakanta Bhat

Constant Electric Field Scaling

Technology scaling Scaling factor K > 1 Primary scaling factors: Tox, L W Tox L, W, Xj (all linear dimensions) Na, Nd (doping concentration) Vdd (supply voltage) Derived scaling behavior of transistor: Electric field Ids Capacitance Derived scaling behavior of circuit: Delay (CV/I) Power (VI) Power-delay product Circuit d i ( Ci i density ( 1/A)

1/K K 1/K 1 1/K 1/K 1/K 1/K2 1/K3 K2

Navakanta Bhat

Constant Voltage Scaling

Technology scaling Scaling factor K > 1 Primary scaling factors: Tox, L W Tox L, W, Xj (all linear dimensions) Na, Nd (doping concentration) Vdd (supply voltage) Derived scaling behavior of transistor: Electric field Ids Capacitance Derived scaling behavior of circuit: Delay (CV/I) Power (VI) Power-delay product Circuit d i ( Ci i density ( 1/A)

1/K K2 1 K K 1/K 1/K2 K 1/K K2

Navakanta Bhat

Generalized Scaling
Technology scaling Scaling factor K > 1 1< < Primary scaling factors: Tox, L W Tox L, W, Xj (all linear dimensions) Na, Nd (doping concentration) Vdd (supply voltage) Derived scaling behavior of transistor: Electric field Ids Capacitance Derived scaling behavior of circuit: Delay (CV/I) Power (VI) Power-delay product Circuit d i ( Ci i density ( 1/A) 1/K K /K 2/K 1/K 1/K 3/K2 2/K3 K2
Navakanta Bhat

Non Scaling Factors

Bandgap of Silicon Eg=1.12eV g p g Thermal voltage kT/q Mobility degradation Increasing doping and electric field Velocity saturation y Parasitic s/d resistance Process tolerance

Navakanta Bhat

Velocity saturation
107cm/sec at T=300oK

Ids (Vgs-Vt) Id (V Vt)2 Ids (Vgs-Vt) ( g )

Ids

v
v=
E E valid only at low electric fields (E)
~104 V/cm

Vds Ids will be less than expected due to velocity saturation

For velocity saturated transistor, the saturation drive current is y Ids = [(W)/Tox](Vgs-Vt)vsat For L=0.1m transistor operating at Vd=1V: E=105 V/cm => transistor is velocity saturated
Navakanta Bhat

Short Channel Effect (SCE)

Vg n+
depletion d l i

Vt n+
depletion

~1m

p-substrate L (m) Fraction of the depletion charge (Qd in Vt equation) is supported by the b th source and drain junctions and hence Vg need not support this d d i j ti dh V d t t thi When L is very small (~ 1m) this charge becomes significant fraction of the total depletion charge and can not be neglected

=> Vt decreases with decreasing L

Impacts matching of transistors in analog applications and speed variation in digital applications
Navakanta Bhat

Sub-micron Transistor structure

Na

spacer n+ source p well p-well X

gate
oxide

Pocket halo Y drain

Na

n+

L Y

Super steep retrograde channel 0 X

Short channel effects are controlled by shallow extension region, pocket halo implant and super steep retrograde channel implant k h l i l d d h li l
Navakanta Bhat

Reverse Short Channel Effect

Vt With SCE control

dV t = ve dL

dV t = + ve dL

Without SCE control

Invariably exists in almost all the sub-micron technologies y g The techniques used to suppress SCE are responsible for RSCE Vt becomes very sensitive function of L, at the nominal length

Navakanta Bhat

Drain Induced Barrier Lowering (DIBL)

Vg Vs n+ Vd n+ Vds=Vdd Vds=0.1V Vds=Vdd Potential barrier Vt is also a function of drain voltage in sub-micron transistors DIBL effect is negligible in the long channel regime
Navakanta Bhat

Vt

Vds=0.1V

The Issue of Static Power

S. Thompson et.al. Intel technology Journal Q398, p.15

Navakanta Bhat

Sub threshold conduction

Log Ids

The inverse slope of this line is sub threshold slope, S sub slope Vt

Vgs For Vg < Vt, current is non zero and is exponential function of Vg S = 2.3kT/q (1 + Csi/Cox) mV/decade
Csi=depletion capacitance in Si, Cox=oxide capacitance,kT/q=thermal voltage

MOSFET should be designed to have minimum possible S S can be decreased by decreasing Na, decreasing Tox y g , g
Navakanta Bhat

Transistor design methodology for Digital Technology

Circuit characteristics: Delay (Vt/Vdd) Active power (Vdd) Standby power (Vt)

Hot carrier reliability Vdd, L, N

System compatibility Vdd

Gate oxide reliability Vdd, Vdd Tox

Design parameters: L, Vdd, Tox, N, Xj S/D engineering Channel engineering g g

Navakanta Bhat

Vt-Vdd design plane

Normalized delay

Delay y Vt Pac Psb

0.4 Vt/Vdd

Vdd

Delay increases significantly for Vt/Vdd > 0.4 04 Pactive (Pac) = CVdd2f Pstandby (Psb) = WVddIoff Delay and Power are the only trade-off points for digital design
Navakanta Bhat

Twin well CMOS process

Trench isolation to define active regions N well definition for PMOS transistors P well definition for NMOS transistors Gate oxide formation and gate poly silicon patterning NMOS h l and shallow extension i l t halo d h ll t i implant PMOS halo and shallow extension implant Spacer formation N+ select for NMOS source/drain P+ select for PMOS source/drain S/D activation and Silicidation Contact definition M t l 1 layer patterning Metal l tt i Via 1 definition Metal 2 layer patterning (Repeat via & metal process until last metal is reached)
Navakanta Bhat

Active area mask P1

p-Si Grow pad oxide and deposit nitride Apply photo resist Photo using Active mask Develop the photo resist Etch the nitride, oxide and clear resist Etch trench in Si Fill t trench by depositing oxide hb d iti id

Active mask

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Shallow trench isolation

p-Si Polish excess oxide, nitride and oxide oxide Active areas isolated with shallow trench Trench depth ~ 3500A Much better isolation compared to junction isolation

Navakanta Bhat

N-well mask P2

n-well

p-Si Grow sacrificial oxide on wafer Apply photo resist Photo using n-well mask Develop the photo resist Implant Phosphorus, Antimony Clear photo resist

n-well mask

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P-well mask P3

p-well

n-well p-well mask

p-Si Apply photo resist Photo using p-well mask Develop the photo resist Implant Boron, Indium Boron Clear photo resist Diffuse both wells

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Poly-silicon gate mask P4

p-well

n-well Poly mask

p-Si Etch sacrificial oxide Grow gate oxide, deposit poly silicon Apply photo resist Photo using Poly mask Develop the photo resist Etch poly-Silicon Clear h h Cl the photo resist i

Navakanta Bhat

NMOS Halo and Extension-P5

halo h l

p-well

n-well n-well N+ select mask

p-Si Apply photo resist Photo using N+ select mask Develop the photo resist Implant Boron halo at a 45o tilt angle Implant Arsenic shallow extension Clear the photo resist

Navakanta Bhat

PMOS Halo and Extension-P6

halo

p-well

n-well P+ select mask

p-Si Apply photo resist Photo using P+ select mask Develop the photo resist Implant Phosphorus halo at a 45o tilt angle Implant Boron shallow extension Clear the photo resist

Navakanta Bhat

Spacer formation

p-well

n-well

p-Si Deposit oxide Deposit blanket nitride Etch nitride anisotropically

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N + select mask P7

p-well

n-well n-well N+ select mask

p-Si Apply photo resist Photo using N+ select mask Develop the photo resist Implant Arsenic Clear the photo resist

Navakanta Bhat

P + select mask P8

p-well

n-well P+ select mask

p-Si Apply photo resist Photo using P+ select mask Develop the photo resist Implant Boron Clear the photo resist Anneal source/drain Silicide f Sili id formation i

Note: Not to scale. For 0.18 m technology: scale 0 18 Typical wafer thickness ~ 500m Typical well depth ~ 1m Typical source/drain depth ~ 0.1m 01 Typical gate oxide thickness ~ 25 Typical poly-Si gate thickness ~ 2000

Navakanta Bhat

Contact mask P9

p-well

n-well Contact mask

p-Si Deposit oxide Apply photo resist Photo using contact mask Etch contact hole Clear the photo resist Deposit contact plug

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Metal-1 mask P10

p-well

n-well Metal mask

p-Si Deposit metal Apply photo resist Photo using metal mask Etch metal Clear the photo resist

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Non Classical CMOS

Non Classical CMOS
High-K Gate dielectric Metal Gate electrode Silicon On Insulator Strained Silicon Channel Double gate / FinFET

Navakanta Bhat