INTERFACE CIRCUITS IN SOI-CMOS FOR HIGH-TEMPERATURE WIRELESS MICRO-SENSORS

by LEMI TOYGUR

Submitted in partial fulfillment of the requirements For the degree of Doctor of Philosophy

Thesis Adviser: Dr. Steven L. Garverick

Department of Electrical Engineering and Computer Science CASE WESTERN RESERVE UNIVERSITY

Jan, 2004

Table of Contents 1. Introduction ................................................................................................................ 1 1.1 1.2 Motivation ............................................................................................................. 1 Background............................................................................................................ 3 High Temperature Telemetry Using Discrete Components.......................... 3 Si Technologies for High-temperature Integrated Circuits............................. 4 High-Temperature Behavior of Si .................................................................. 5

1.2.1 1.2.2 1.2.3

1.2.3.1 Intrinsic Carrier Density and Carrier concentration .................................... 5 1.2.3.2 p/n Junction Leakage Current...................................................................... 6 1.2.3.3 Carrier Mobilities ........................................................................................ 8 1.2.4 1.2.5 Temperature Dependence of Bulk Silicon MOSFET ..................................... 9 SOI Technology ............................................................................................ 10

1.2.5.1 SOI Device Parameters.............................................................................. 11 1.2.5.2 Partially and Fully Depleted-SOI .............................................................. 12 1.2.5.3 The UTSi Process ...................................................................................... 13 1.3 Spice Simulation at High Temperature ............................................................... 16 SPICE model and simulation tool................................................................. 16

1.3.1 1.4 1.5

Alternative Technologies..................................................................................... 18 MEMS resonator.................................................................................................. 20 Thermal noise................................................................................................ 22

1.5.1 1.6

Analog to Digital Converters............................................................................... 23 Over-sampled analog-to-digital converters................................................... 23

1.6.1

1.6.1.1 Sigma-delta modulators............................................................................. 25 1.7 1.8 Modulo-N Decimator Filter................................................................................. 28 Binary VCO for FSK Transmitter ....................................................................... 29

2. Analysis of MEMS-based oscillators ...................................................................... 31 2.1 2.2 Introduction ......................................................................................................... 31 Background.......................................................................................................... 32 Oscillation Criteria........................................................................................ 32

2.2.1 2.3

Topology Selection.............................................................................................. 34 Negative-Resistance Topology ..................................................................... 35 Pierce Topology ............................................................................................ 36 Transresistance Topology ............................................................................. 38

2.3.1 2.3.2 2.3.3 2.4

Conclusion ........................................................................................................... 39

3. Transresistance amplifier design for high-temperature transducers with very large series resistance ..................................................................................................... 41 3.1 Transimpedance amplifier using discrete high-temperature BJTs ...................... 41 Biasing .......................................................................................................... 41 Transimpedance Gain ................................................................................... 42 Bandwidth ..................................................................................................... 44 Selection of the circuit variables................................................................... 44

3.1.1 3.1.2 3.1.3 3.1.4 3.2

CMOS SOI Design .............................................................................................. 45 Band-gap reference circuit............................................................................ 46 Transresistance amplifier .............................................................................. 53

3.2.1 3.2.2

3.2.3

Oscillator....................................................................................................... 58

4. Circuit Design of the Sigma-delta Modulator........................................................ 60 4.1 General Performance Issues ................................................................................ 60 Correlation of Quantization Noise with the Input Amplitude ...................... 60 Nonlinear Effects .......................................................................................... 60 1/f Noise and Offset Reduction with Chopping............................................ 62 Switch and Opamp Noise.............................................................................. 63 Settling-time.................................................................................................. 64

4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.2 4.3 4.4 4.5

Differences between the design of the silicon and the SOI circuits .................... 66 SOI version of the sigma-delta modulator........................................................... 67 Chopping, Dither, and Dynamic Element Matching ........................................... 71 Circuit Details...................................................................................................... 72

5. Testing of the SOI transresistance amplifier and sigma-delta ADC ................... 79 5.1 5.2 Testing of the transresistance amplifier............................................................... 79 Testing of the Sigma-Delta Converter................................................................. 87 DC Tests........................................................................................................ 87 AC Tests........................................................................................................ 88 High-Temperature Testing............................................................................ 97 Correcting the high-temperature simulation ................................................. 99 Extraction of the high-temperature parameters from the measurement...... 100 Sigma-Delta simulation from 27 C to 300 C ........................................... 106

5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6

6. Conclusion............................................................................................................... 113

6.1 6.2

Achievements .................................................................................................... 113 Future Work....................................................................................................... 114

List of Tables Table 1-1 Transistor types in UTSi (from [20])................................................................ 15 Table 1-2 Resistor type in UTSi [21]................................................................................ 16 Table 1-3 Properties of silicon and wide-bandgap semiconductors (from [26]). ............. 19 Table 4-1 Expected increase and decrease of the voltage at the output of the integrator with (VR+- VR-)=1.8 V and VIN=1 V. ......................................................................... 77 Table 5-1 Measured threshold variation with temperature. ............................................ 103 Table 5-2 Measured mobility variation with temperature. ............................................. 103 Table 5-3 Measured values of the SN type resistor with varying temperature............... 104

List of Figures Figure 1-1 Block diagram of the high-temperature, wireless sensor .................................. 1 Figure 1-2 Electron density in silicon as a function of reciprocal temperature with a donor impurity concentration of 1015 cm-3 (after [12])........................................................... 5 Figure 1-3 Measured leakage current density for Si/SiC p/n junctions, versus temperature (after [14, 15]). ............................................................................................................. 8 Figure 1-4 Temperature dependence of measured electron mobility in 6H-SiC (after [18]).............................................................................................................................. 9 Figure 1-5 Measured gm/Id curves of SOI p-MOSFETs as a function of temperature. W/L = 20/20 (solid lines) and W/L = 3/3 (dashed lines). (from [6]).................................. 12 Figure 1-6 The comparison between regular CMOS process and SOS process (from [19]). .................................................................................................................................... 14 Figure 1-7 Clamped-clamped beam resonator (from [29])............................................... 22 Figure 1-8 Illustration of in-band noise ............................................................................ 24 Figure 1-9 Principle of sigma-delta modulator................................................................. 25 Figure 1-10 Quantization noise model for first order sigma-delta modulator (after [34). 26 Figure 1-11 Basic circuit diagram of the VCO (after [37]) .............................................. 30 Figure 2-1 Basic positive feedback network..................................................................... 32 Figure 2-2 Negative-resistance Topology......................................................................... 35 Figure 2-3 Pierce Topology .............................................................................................. 37 Figure 2-4 Transresistance Topology ............................................................................... 38 Figure 3-1 Circuit schematic for the two stage discrete version of the transresistance

amplifier . ................................................................................................................... 42 Figure 3-2 Block diagram of the CMOS SOI version of the transresistance amplifier.... 46 Figure 3-3 The principle of the band-gap reference circuit (after [44]). .......................... 47 Figure 3-4 Schematic of the bulk Si design of the band-gap reference circuit (from [45]). .................................................................................................................................... 48 Figure 3-5 Schematic of the band-gap reference circuit in SOI [46]. Device dimensions are in units of =0.25 m........................................................................................... 49 Figure 3-6 Current schematic of the band-gap reference circuit in SOI. Device dimensions are in units of =0.40 m........................................................................ 50 Figure 3-7 Simulated variations in the reference voltages and the slope of the differential reference voltage due to the supply voltage variations. ............................................. 51 Figure 3-8 Schematic of the transresistance amplifier circuit in SOI. Device dimensions are in units of =0.40 m........................................................................................... 54 Figure 3-9 Magnitude response of the feedback-biasing loop for CC = 0.01 F.............. 55 Figure 3-10 Phase response of the feedback-biasing loop................................................ 56 Figure 3-11 Magnitude versus frequency response of the transresistance amplifier with 7 Meg source resistance and CC=0.1 F. ................................................................... 57 Figure 3-12 Phase response of the transresistance amplifier for 1, 2, and 3 pF loads. Source resistance is 7 Meg and CC=0.1 F............................................................. 57 Figure 3-13 Circuit schematic of the oscillator................................................................. 58 Figure 3-14 Simulation result of the 700 kHz oscillator. The amplitude variation in the

simulation is caused by the numerical error due to the simulator.............................. 59 Figure 4-1 Basic Integrator. .............................................................................................. 61 Figure 4-2 Integrator with bottom-plate sampling............................................................ 61 Figure 4-3 (a) Concept of chopper stabilization. (b) Equivalent input noise for the circuit in (a). (from [51]). ...................................................................................................... 62 Figure 4-4 Illustration of dynamic element matching and opamp chopping to minimize opamp offset and 1/f noise: (a) concept; (b) implementation. ................................... 63 Figure 4-5 Simplified schematic of the sigma-delta modulator [after 46]........................ 69 Figure 4-6 Clock phases for the switched-capacitor sigma-delta modulator [from 46]. .. 70 Figure 4-7 Dynamic D flip-flop........................................................................................ 71 Figure 4-8 Schematic of the SOI version of the FDOA [46]............................................ 74 Figure 4-9 Schematic of the SOI comparator [46]............................................................ 75 Figure 4-10 Integrator output from the SOI sigma-delta modulator................................. 77 Figure 5-1 Block diagram of the test setup for the Rm amplifier. ..................................... 79 Figure 5-2 Measured output voltage of the Rm amplifier with input floating................... 80 Figure 5-3 Measured output voltage of the Rm amplifier with input touched. ................. 80 Figure 5-4 Measured output voltage of the Rm amplifier with 0.1F capacitor connected between input and output. .......................................................................................... 81 Figure 5-5 High-temperature test setup ............................................................................ 82 Figure 5-6 Measurement of the Rm output in DIP package with minimum parasitics. .... 83 Figure 5-7 Block diagram of the transimpedance amplifier with parasitic feedback capacitance. ................................................................................................................ 84

Figure 5-8 AC simulation of the magnitude and phase response of the closed-loop system......................................................................................................................... 85 Figure 5-9 Transient simulation of the Rm amplifier with 50 fF feedback. ..................... 86 Figure 5-10 Measured DC transfer characteristic of the sigma-delta modulator at room temperature................................................................................................................. 88 Figure 5-11 FFT of the sigma-delta modulator output bit stream for a sinusoidal input of 3 kHz. The 16 kHz dither is apparent......................................................................... 91 Figure 5-12 Measurement of SNR versus input amplitude. ............................................. 93 Figure 5-13 Measured reference voltage versus power supply. ....................................... 94 Figure 5-14 Measured FFT offset voltage versus power supply. ..................................... 95 Figure 5-15 Measured SNR versus power supply voltage................................................ 96 Figure 5-16 Measured signal amplitude versus power supply voltage............................. 96 Figure 5-17 Measured SNR versus common-mode input voltage under nominal conditions. .................................................................................................................. 97 Figure 5-18 Measured SNR versus temperature............................................................... 98 Figure 5-19 Circuit Schematic of the transistors, capacitors and resistor used for device characterization. ....................................................................................................... 100 Figure 5-20 ID versus VDS at 300 C for intrinsic NMOS transistor with VGS varying between 0 V and 3 V and 0.5 V increments............................................................. 101 Figure 5-21 Measured Id versus Vgs at 200 C. ............................................................. 102 Figure 5-22 Sqrt(Id) versus Vgs using data of Fig 5-17, including linear fit for VGS between 0.1 V and 0.6 V. ......................................................................................... 102

Figure 5-23 Comparison of measured (solid line) and simulated (dash line) bias voltages at various temperatures:Vpbias (o), Vr+ (*), and Vr- (+). ....................................... 105 Figure 5-24 Total measured (solid line) and simulated (dash line) analog supply current. .................................................................................................................................. 106 Figure 5-25 Simulated OPAMP and comparator I/O at 27 C. ...................................... 108 Figure 5-26 Simulated OPAMP and comparator I/O at 150 C. .................................... 109 Figure 5-27 Simulated OPAMP and comparator I/O at 200 C. .................................... 110 Figure 5-28 Simulated OPAMP and comparator I/O at 250 C. .................................... 111 Figure 5-29 Simulated OPAMP and comparator I/O at 300 C. .................................... 112

Acknowledgements

I cannot thank Professor Steven Garverick too much for his guidance, encouragement, and patience thorough out this five year long work. Without his support I cannot imagine that I would have achieved my Ph.D. degree. Also, I would like to thank my committee members for their valuable suggestions and insights on my thesis. Furthermore, I am grateful to all of my former and present labmates of the CWRU Mixed-Dignal IC Design Group for making such an enjoyable working environment. They are Xinyu Yu, Shuyu lei, Hongwen Lu, Jun Guo, Michael Inerfield, etc. I have to thank my wife for her support and help. This work was supported by Glennan Research Center.

Interface Circuits in SOI-CMOS for High-Temperature Wireless Micro-Sensors Abstract by LEMI TOYGUR

This thesis explores the use of commercially available SOI-CMOS technology for use in high-temperature sensor interface circuits for operation at temperatures up to 300 C. A fully depleted technology was chosen for its inherently low leakage current and critical sensor interface circuits were developed, specifically, a transimpedance amplifier and analog-to-digital converter. Since the ultimate goal is a high-temperature wireless microsensor, low power consumption and stable oscillator frequency were key issues in this work. Oscillator topologies for MEMS resonators having very high series resistance were examined in regards power consumption and in-circuit quality factor. The transresistance topology was determined to be the best candidate for operation with MEMS resonators, but bandwidth and transimpedance gain must be very high to achieve a loop gain greater than one, as required for oscillation. An SOI transresistance was designed to meet the requirements of a particular SiC resonator. This IC was fabricated, packaged in a DIP, and tested. The amplifier, itself, oscillated due to parasitic coupling capacitance between input and output in the packaging, as proved by a variety of

measurements and simulations. In future work, an unpackaged SOI-IC will be used to eliminate the parasitic coupling. Ideally, the MEMS resonator should be integrated with the IC. To convert the analog signal to digital with 8-bit of accuracy reliably, a robust, 1st-order sigma-delta converter was designed. The sigma-delta converter is fully differential with discrete-time integrator and comparator, and also uses chopper stabilization, dynamic element matching and dithering to achieve high performance with relatively poor components. State-of-the-art performance has been achieved. With a power supply voltage of 3.3 V, SNR reached the theoretical maximum of 50 dB at room temperature, and was above 40 dB and 30 dB, respectively, up to 250 C and 275 C. Design weaknesses were identified in the course of testing, so it is believed that this performance can be improved.

1. Introduction 1.1 Motivation High-temperature (>150C) electronic circuits are limited by fundamental problems in the devices. With good design techniques, bulk CMOS can operate as high as 200C [1,2]. SiC has good electronic properties at temperatures as high as 600C [1,2], but IC fabrication processes are not yet mature. Silicon-on-Insulator (SOI) technology provides an intermediate option for temperatures up to 300C [3]. In this work, sensor interface circuits for high-temperature, wireless micro sensors have been designed and tested using SOI technology. The interface circuits are to be operated in a harsh environment, so miniaturization, low power and stable clockfrequency at high temperature are all key factors in this design. A block diagram of the overall concept, including the focus of this work, is given in Fig.1-1. Resonator This Work Rm Rm Sensor Amp. ADC Decimator VCO Transmitter Antenna Receiver SOI IC

Figure 1-1 Block diagram of the high-temperature, wireless sensor A high-temperature sensor is interfaced to a sigma-delta analog-to-digital converter through a transresistance amplifier. The sensor is stimulated using a relatively low-frequency signal, so the sigma-delta converter, which uses an over-sampling technique in a feedback configuration to reduce the quantization noise, can be clocked at just 1 MHz.

The proposed clock circuit for the oscillator employs the same transresistance amplifier used in the sensor interface, and a SiC resonator to set the oscillation frequency. Detailed analysis of the oscillator performed in the course of this work, however, shows that even though the quality factor of the SiC resonator is extremely high, it is only a good candidate for the oscillator if monolithically integrated with the Rm amplifier. This is technically possible, but has not been implemented. Instead, an external oscillator has been used to operate the sigma-delta converter. A decimation filter is required to remove quantization noise and to down sample to the Nyquist rate, which is the twice the maximum frequency of the input sensor signal. The detailed design of the filter has been performed by a colleague, and the necessary background is given in this document. The output of the decimation filter is digital. This data will be wirelessly transmitted using frequency shift keying (FSK). A simple voltage-controlled oscillator (VCO) has been designed for this purpose, again by a colleague, and a summary of this work is provided. This work includes MEMS-based oscillator analysis considering a variety of topologies, the design of an SOI transresistance amplifier to be used in the oscillator and sensor interface, and the design of the sigma-delta converter. This work is presented in Chapters II, III, and IV, respectively. Test results are presented in Chapter V, and concluding thoughts are given in Chapter VI. This chapter continues with background information related to all aspects of the work.

1.2 Background 1.2.1 High Temperature Telemetry Using Discrete Components

When the required sensor operating temperature is too high, electronics systems may be employed in a cooler place with long wires or cooling may be performed in the hightemperature environment. Unfortunately, both approaches bring undesirable overhead, complexity, and performance degradation. High-temperature integrated circuits are needed in many military and industrial applications. For the last three decades, many approaches have been studied. A radio frequency wireless telemetry system for sensor data acquisition at high temperature (200 C) was investigated in [4]. The objective was to transmit data from a sensor in a hightemperature environment to a remote receiver using load shift keying. In this research, the receiver supplied the energy required by the transmitter, to avoid the use of batteries at such high temperatures. Also, research in [4] focused on discrete circuit design, not on device level issues and the potential of IC technology. It was shown that even basic components used in the PCB design such as solder, capacitors, and resistors, are not readily available in elevated temperatures. They are, in fact, an active research topic. The system worked for distances up to 7 inches, but the discrete passive and active components were not very reliable at the highest temperatures. In another approach [5], a low-power silicon-tunnel-diode-based LC-tuned oscillator transmitter is proposed for high-temperature MEMS sensing and wireless data transmission applications. The prototype sensing and transmitting module employs a MEMS silicon capacitive pressure sensor performing pressure to frequency conversion

and a miniature on-board coil loop serving as the inductor for the LC tank and transmitting antenna. The system has achieved telemetry performance up to 290 C over a distance of 2.5 meters with a total power consumption of 110 W. But it has been reported that a significant performance degradation has occurred due to the failure of onboard discrete components at high temperature, so in addition to selecting better heat resistant discrete components, a sensor interface and an analog-to-digital converter is proposed to achieve higher resolution. 1.2.2 Si Technologies for High-temperature Integrated Circuits

Bulk Si devices, which rely on electrical isolation through reverse biased p/n junctions, fail above 200 C, primarily due to high leakage currents. Several attempts have been successful at 200 C [6], but beyond that temperature it seems unlikely to design a reliable circuit. Silicon IC chips fabricated using silicon-on-insulator (SOI) technology can operate at temperatures up to 300 oC [7-11]. Because this fabrication technology uses dielectric materials to isolate devices rather than reverse-biased junctions, leakage currents at high temperatures can be reduced by two to four orders of magnitude. However, at temperatures above 300 oC, threshold voltage shifts and mobility reduction limit performance. Wide-band gap semiconductors are needed for higher temperatures. In the following section basic high-temperature performance degradation factors in Si will be explored. In later sections bulk MOSFET, SOI MOSFET technology and wideband gap semiconductor solutions will be considered.

1.2.3

High-Temperature Behavior of Si

1.2.3.1 Intrinsic Carrier Density and Carrier concentration When a semiconductor is doped, the number of majority carriers per unit volume is mainly dependent on the ionized doping concentration, over a wide temperature range. Fig. 1-2 shows a typical electron carrier concentration versus temperature for Si doped with 1015 donors/cm3. At very low temperatures, the donor electrons are bound to the atoms. Intrinsic electron-hole pairs are negligible. As the temperature rises, an increased number of electrons are elevated to the conduction band, and the corresponding temperature range is called the ionization region. When temperature is high enough to activate all donor electrons, the semiconductor is in the desired extrinsic region. At a higher temperature, the semiconductor enters its intrinsic region. At room temperature, most of doped impurities are ionized for silicon so the majority carrier concentration is equal to the carrier concentration is equal to the accepter/donor concentration.
18 17 16 Intrinsic 500 K Extrinsic ni Ionization

Log (ne)

15 14 13 12 11
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014

1/T (K-1) Figure 1-2 Electron density in silicon as a function of reciprocal temperature with a donor impurity concentration of 1015 cm-3 (after [12]).

The intrinsic number of carriers per unit volume ni of a semiconductor depends on temperature and the band gap of the semiconductor, as given by [13]
ni = N C N V e
E g / 2 kT

Equation 1-1

where k is the Boltzmann constant, NC and NV are the effective electron and hole density of states for the semiconductor, and Eg is the bandgap energy. NC, NV and Eg are also temperature dependent but the exponential temperature dependence dominates ni(T) in equation (1). As evident from this equation, when the ambient temperature is increased, there can be as many or more intrinsic carriers than dopant carriers, i.e. the semiconductor functions in the intrinsic region.
1.2.3.2 p/n Junction Leakage Current

In bulk semiconductor technologies, reverse-biased p/n junctions are used to isolate the devices, and the leakage current of these parasitic diodes is most likely the limiting factor for high-temperature operation. Bulk silicon integrated circuits generally cannot function properly at temperatures beyond 200 oC, due to this problem. At moderate temperatures, the reverse saturation current of the parasitic diodes is quite small. However, this leakage current increases rapidly at high temperatures, and is comparable to channel currents. Leakage currents can cause an operating point shift in analog circuits, and cause loss of data stored in dynamic digital circuits. The current also contributes to self-heating of the device, and the power dissipation can be very large at elevated temperatures. The leakage current of a p/n junction mainly consists two components: diffusion

current and space-charge generation current. The total leakage current, IL, is expressed as [13].
IL = IL, diff + IL, gen qAni

ni ND

DP

(e

qV A / kT

1 +

W qVA / kT 1 e 2

Equation 1-2

where A is the area of the p-n junction, VA is the voltage applied to the diode, ND is the n-type doping density, W is the width of the junction depletion region at applied voltage VA, DP is the hole diffusion constant, and is the effective minority carrier lifetime. For negative VA (reverse bias) greater than a few tenths of a volt at temperatures below 1000 C, the exponential term are insignificant compared to 1, so that (2) simplifies to n I qAni i ND DP + W . 2

Equation 1-3

The diffusion current is generated in neutral regions where there is no significant electric field. The carriers move by diffusion from areas of higher carrier concentration to areas of lower carrier concentration. When these carriers reach the edge of the depletion region, they are swept across the junction by the electric field. On the other hand,

generation current is due to thermal generation of electron-hole pairs inside the depletion region. These carriers are separated and swept across the region by the electric field. It is clear that both leakage currents are proportional to junction area, which should be minimized. At low temperatures, the generation leakage current dominates, and at high temperatures, leakage current is mainly due to diffusion current. From equation (3), it is clear that diffusion current is proportional to intrinsic concentration ni. For silicon, ni is

significantly increased at high temperatures, so leakage current is not negligible.

1.00E+02 102 1.00E+00 100 1.00E-02 10-2 1.00E-04 10-4 1.00E-06 10-6 1.00E-08 10-8 1.00E-10 10-10

Leakage Current Density (A cm-2)

Si SiC

3
-1

1000/T (K ) Figure 1-3 Measured leakage current density for Si/SiC p/n junctions, versus temperature (after [14, 15]).
1.2.3.3 Carrier Mobilities

Electron and hole mobility are determined by two basic types of scattering mechanisms: lattice scattering and impurity scattering. In lattice scattering, a carrier moving through the crystal is scattered by vibration of the lattice, which is related to the temperature. The lattice scattering increases with temperature, causing a decrease in carrier mobility. On the other hand, a carrier can be scattered by crystal defects, i.e. impurity scattering. This will be dominant at low temperatures, since the thermal motion of the carriers is slower at low temperature, and the carrier is more likely to be scattered by crystal defects. A quantitative approach reveals that mobility has a T-3/2 dependence due to lattice scattering, and a T3/2 dependence due to impurity scattering for silicon [12]. It has been reported that carrier mobility in SiC increases for T up to 100 ~ 200 K,

after which it begins to decrease, dropping off as T 2 [16, 17, 18]. Since researchers are primarily interested in high-temperature properties, only mobility data above 100 K were provided.
4 1.00E+04

Electron Mobility(cm2/V-1s-1)

10

1.00E+03

103

2 1.00E+02

10

1.00E+01 1

10

100

102

1000

Temperature (K)

103

Figure 1-4 Temperature dependence of measured electron mobility in 6H-SiC (after [18]).
1.2.4 Temperature Dependence of Bulk Silicon MOSFET

A Si CMOS transistor in the saturation region has higher transconductance gm at room temperature than at high temperature since carrier mobility decreases when temperature is increased. The threshold voltage decreases slightly with temperature [13], about 2mV / C. The threshold of nchannel MOSFETs becomes more negative, pchannel more positive When gate voltage is decreased below threshold voltage, current flow due to majority carriers stops and the device is off. However, a parasitic flow of electrons carries a subthreshold channel leakage current via carrier emission over the potential barrier

10

between the source and drain created by the applied gate bias, analogous to a bipolar junction transistor. Additional reduction in the gate voltage increases the potential barrier for the electrons, resulting in an exponential relationship between gate voltage and subthreshold current

(I

DS

eV

GS / nV Th

) . When temperature is increased, a larger gate

voltage is required to decrease the subthreshold leakage. The subthreshold leakage is worse in short-channel devices since the applied drain voltage effectively lowers the height of the channel potential barrier all the way to the source side of the channel. The subthreshold leakage current is added to the reverse-biased drain-to-substrate junction leakage current. Thus, off-current is ultimately limited by the reverse-bias junction leakage current, which depends on the intrinsic carrier concentration, a strong function of temperature. As a result, operating current decreases while leakage current increases with increasing temperature, which presents significant challenges for the circuit design.
1.2.5 SOI Technology

The main advantage of Silicon-on-Insulator (SOI) technology is the reduction of the area of the drain/source junction, which significantly decreases leakage current. In a fully depleted process, the junction is effectively eliminated. Subthreshold channel current is also decreased, due to the underlying insulator [9]. These two facts enable the SOI MOSFET-based circuits to successfully operate in the 200 C - 300 C temperature range.

11

1.2.5.1 SOI Device Parameters

The threshold voltage of fully depleted SOI transistors is about three times less sensitive to temperature than for bulk devices [6]. The threshold voltage shift for both NMOS and PMOS is about 0.35 V (1 mV/C) between room temperature and 300 C. The mobility varies with temperature in SOI as in bulk devices. The junction leakage current is smaller by orders of magnitude in thin-film SOI as compared to bulk transistors due to the absence of diffusion leakage to the substrate. Since the dominant leakage current is the generation term in the fully depleted volume under the channel, the leakage current decreases with reduction of the device length. However, beyond a minimum limit corresponding to an optimum length, the junction leakage current increases rapidly with the reduction of the device length as a result of short-channel effects including sub-threshold leakage. The gm/IDS ratio is an important metric of device performance and higher is better, since opamp performance characteristics including voltage gain and bandwidth, increase with gm/IDS. The gm/IDS ratio is maximized in weak inversion. As mentioned in section 1.2.4, the junction leakage current adds to the subthreshold channel current in a bulk MOSFET. Junction leakage can be eliminated in SOI MOSFETs. Since subthreshold channel current is limited by the generation current, leakage current can be scaled down to an optimum value by length reduction, which improves the maximum gm/IDS, as shown in Fig. 1-5. The output conductance of fully depleted SOI MOSFETS is relatively insensitive to temperature, a tremendous advantage compared to bulk MOSFETs in which output

12

conductance is known to increase very rapidly above 150 C, since the drain junction leakage current becomes a significant component of the overall drain current.

Figure 1-5 Measured gm/Id curves of SOI p-MOSFETs as a function of temperature. W/L = 20/20 (solid lines) and W/L = 3/3 (dashed lines). (from [6])
1.2.5.2 Partially and Fully Depleted-SOI

The depletion region of partially depleted (PD) SOI does not reach through the entire silicon channel/body region. PD-SOI is easier to manufacture than fully depleted (FD) SOI due to its relatively thicker substrate. PD material usually has a silicon thickness greater than 0.15 m. PD-SOI devices exhibit the kink effect, a circuit behavior not present in bulk technology, which is reduced when the SOI film is thinned, and is mostly eliminated in

13

FD-SOI. The kink effect is caused by the floating body. The floating body also gives rise to hysteresis, causing different switching delays on subsequent switching edges in digital circuits. For FD devices, the SOI film is thinner than the pn junction depletion width. Thus, the MOS device has no body region. With no floating body, the FD transistor does not exhibit significant kink or hysteresis effects, and is much better for analog circuit design. However, threshold voltage control is relatively poor and matching difficulties may occur due to fringing fields. Devices in FD-SOI display a steep sub-threshold slope and low parasitic capacitances, making them appropriate for low-voltage, low-power applications. A significant advantage of FD circuits is that for the same bandwidth they typically consume only half the power of their bulk counterparts. Alternatively, bandwidth may be improved for a given power dissipation.
1.2.5.3 The UTSi Process

The Ultra Thin Silicon (UTSi) process [19], a mature SOI process invented by Peregrine Semiconductor, was chosen for this work. The UTSi is the worlds first commercially qualified silicon-on-sapphire (SOS) CMOS process and is optimized for high-performance, low-power commercial CMOS applications. Because of the small feature size (0.4 m) and low parasitic capacitance of this technology, UTSi is ideal for radio-frequency (RF) IC design and high-performance digital circuit design. The floating bulk leads to hysteresis and low output impedance, however, which can seriously impact analog peformance.

14

The comparison between a standard CMOS process and an SOS process is presented in Figure 1-6. In a bulk CMOS process, wells are needed to isolate MOSFETs from the substrate. At high temperature, a large reverse-biased current will flow through parasitic PN, PNP and NPN structures to cause circuit malfunction. On the other hand, SOI technology provides devices on insulator. Inherently, there are no parasitic bulk diodes or BJTs. Therefore, the IC can be operated at higher temperature.

Figure 1-6 The comparison between regular CMOS process and SOS process (from [19]). The UTSi technology has similar electron and hole mobility to a bulk silicon process. The gate oxide is 10 nm, consistent with the small feature size. The maximum supply voltage specified by Peregrine is 3.6 V. VDD is 3.3 V in this work. Six transistor types are available in the UTSi technology, three n-channel devices and three p-channel devices, as summarized in Table 1-1.

15

Table 1-1 Transistor types in UTSi (from [20]) Transistor Type IN NL RN IP PL RP Description Intrinsic N Channel Low Vt N channel Regular Vt N channel Intrinsic P channel Low Vt p channel Regular Vt p channel VT Implant None NL RN None PL RP Vt 0.0 0.2 0.7 0.0 -0.2 -0.7

The different choices of threshold voltage facilitate both analog and digital circuit design. Because of the low supply voltage, intrinsic devices should be used in most analog circuits. For example, in an amplifier design, especially a folded-cascode amplifier, the use of the intrinsic devices improves linearity for large signal swing. On the other hand, for digital circuits, devices with largest threshold voltage should be used to obtain a larger noise margin and lower off-state current. In this work, intrinsic devices were generally used in analog circuits and regular threshold devices were used in digital circuits. The UTSi process also has four types of resistors, shown in Table 1-2. SN is a high-value implanted resistor, and is used for biasing in this work.

16

Table 1-2 Resistor type in UTSi [21]. Resistor type Polycide N+ source / drain P+ source / drain SN Nominal sheet resistance Ohms/Square 12 145 225 1900

1.3 Spice Simulation at High Temperature

Accurate simulation of analog integrated circuits is necessary for successful development. For a variety of reasons, SPICE inadequately models MOS circuits at temperatures greater than 150 C [22,23]. A SPICE preprocessor for high temperature simulation, called PreSPICE, was developed in [22]. This program was enhanced in [23]. Since the SOI process is different than the bulk process studied in this earlier work, this automated preprocessor could not be used in this work. Instead, the major performance parameters, specifically threshold voltage and mobility, are extracted at selected high temperatures and used to create a new SPICE model for each selected temperature.
1.3.1 SPICE model and simulation tool

Peregrine provides the BSIM3v3 model for all six types of MOS devices. The intended simulator is SmartSpice from Silvaco, which is one of the most popular circuit simulators presently available. It is a C-language implementation of SPICE that is fully

17

compatible with Berkeley SPICE and other commercial SPICE simulators. BSIM3 [24] was developed by the BSIM research group in the department of Electrical Engineering and Computer Science (EECS) at University of California, Berkeley. It is a physics-based, accurate, scalable, robust, and predictive MOSFET SPICE model for circuit simulation and CMOS technology development. The third iteration of BSIM3, BSIM3 version 3, (commonly abbreviated as BSIM3v3), was established by SEMATECH as the first industry-wide standard of its kind in December of 1996. BSIM3v3 has since been widely used by most semiconductor and IC companies worldwide for device modeling and CMOS IC simulation. SmartSpice is not available for this work. Instead, MicroSim PSPICE has been used. MicroSim supports BSIM3v3 model for bulk MOSFETs via level 7. Thus, it is possible to simulate the SOI circuits in this work as bulk MOSFET circuits using BSIM3v3 (PSPICE level 7) with special consideration for the bulk contact. Details are discussed later in this document. Incidentally, the device group at UC Berkeley also developed BSIM3SOI, which is a deep submicron, Silicon-on-Insulator MOSFET device model for SPICE engines. The most recent version number of BSIM3SOI is 1.3. BSIM3v3 is used for bulk MOSFETs via level 8 in Berkeley SPICE, while BSIM3SOI is used for SOI MOSFETs via level 9 in Berkeley SPICE. There are some differences between the BSIM SOI model in SmartSpice and that used in the official release from Berkeley. The most important difference is that the level number for the SOI model in SmartSpice is 8 instead of 9. The SOI model is not supported by PSPICE.

18

1.4 Alternative Technologies

Wide-bandgap materials are needed for even higher temperature operation. Gallium arsenide (GaAs), aluminum nitride (AlN), gallium nitride (GaN), silicon carbide (SiC), and diamond are the best candidates for this purpose. Considering performance and cost, SiC appears to be the best choice at this time. SiC devices can be operated at temperatures over 500 0C [25]. Table 1-3 lists some important properties of these semiconductor materials. In addition to the type of semiconductor, the device types are also limited by high-temperature operation. Metal-oxide-semiconductor field-effect transistors (MOSFETs) are not commonly used for high-temperature applications because of threshold voltage drift and mobility reduction. Junction field-effect transistors (JFETs) are better suited for high temperature because pinch-off voltage is relatively stable across a large temperature range. SiC and III-nitride devices are the most developed wide-band gap semiconductors, suitable for operating temperatures as high as 600 oC [9]. SiC is more advanced in some important technology areas than III-N, such as better control of crystal impurities needed to realize electronic devices. During the 1990s, success in forming relatively large boules and high quality epitaxial layers enabled the fabrication of SiC junction field-effect transistors (JFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), metal-semiconductor field-effect transistors (MESFETs), heterojunction bipolar transistors (HBTs), p/n junction diodes, light emitting diodes (LEDs), and ultra-violet (UV) photo detectors [10, 11].

19

Table 1-3 Properties of silicon and wide-bandgap semiconductors (from [26]). Semiconductor Band transition Bandgap, Eg (eV) Carrier mobility at 300K n (cm2 V-1 s-1) p (cm2 V-1 s-1) Saturation carrier drift Velocity, Vsat (cm s-1) Breakdown field, Eb (V cm-1) Thermal conductivity at 300K 1.56 (W cm-1 K-1) Dielectric constant 11.9 12.9 10.4 8.5 9.7 5.7 0.44 1.30 0.30 3.9 10 3105 4105 20105 70105 100105 1450 500 9500 450 600 10 80 14 400 60 2200 2100 Si GaAs GaN Direct 3.45 AlN 6H-SiC Diamond

Indirect Direct 1.12 1.42

Diret Indirect Indirect 6.28 2.90 5.50

1.0107 2.0107 2.5107 -

2.0107 2.7107

SiC has a very wide bandgap, so ni will not increase dramatically, even at temperatures above 500 oC. Thus, it is obvious that SiC is a much better semiconductor than silicon to operate at high temperatures. At high temperatures, leakage current from a SiC p/n junction is several orders of magnitude less than Si junction. Fig. 1-6 shows two sets of extrapolated experimental data of leakage current density versus temperature for both SiC and Si p/n junctions [14, 15].

20

Despite the potential of wide-bandgap semoconductors such as SiC, we consider only SOI technology in this work for the high-temperature sensor interface IC, since SiC process technology is not ready for sophisticated circuits such as analog-to-digital converters.
1.5 MEMS resonator

In this work, a parallel-plate micromechanical resonator, as illustrated in Fig 1-7, is considered for use in a high-temperature oscillators. AC and DC voltages are applied between the drive electrode and the beam. DC voltage serves two purposes [27]. First, if VP is 0 then the microstructure will move at twice the frequency of the applied drive voltage due to the square-law nature of electrostatic force. Since the DC bias on the beam is greater than the ac amplitude on the drive electrode, frequency doubling is avoided. The second function of VP bias is to amplify the device current due to microstructure motion. The current through the device, neglecting the second order terms, is given by:

Is

V P dC d C d ( avg ) dv i + dt dt

Equation 1-4

where the first term is the current due to the microstructure motion and the second term is the current due to the alternating voltage [27]. This equation shows that device current due to the microstructure motion can be increased by increasing the DC bias voltage. An excessive DC bias voltage may pull the resonator to the substrate and inhibit motion,

21

however. On the other hand, as shown in the following equations, DC voltage has a nonlinear effect on the current of the device.

Is

C d x V P dC d = V PD , x t dt

Equation 1-5

assuming the first term in equation (4) dominates. Also,

C d ( x) =

o Ao
d+x

= C os (1 +

x 1 ) d

Equation 1-6

where Ao and Cos are the overlap area and static capacitance between the beam and the drive electrode. Differentiating the above equation yields
C d C x = os (1 + ) 2 x d d
Equation 1-7

If the beam displacements are small, then the approximation x=0 holds in the above equation. The series resistance of the resonator consists of a motional resistance and an interconnect (parasitic) resistor which is between the moving beam and the wire bond. The interconnect resistor has a significant contribution to the total series resistance [28].

22

Figure 1-7 Clamped-clamped beam resonator (from [29])

1.5.1 Thermal noise

If the ambient temperature of the damped mechanical resonator is finite, and if the system is in thermal equilibrium, then the mechanical resonator must exhibit some degree of random (Brownian) motion. This random vibration constitutes thermal noise in the mechanical domain. The magnitude of the noise generator depends upon both temperature and the amount of damping in the system. The average noise displacement of the mass in a mass-spring-damper oscillator system having spring constant Kr, assuming a dominant mode in the x-direction, is given by

1 1 2 k r <= x n => kT 2 2

Equation 1-8

where xn is the displacement noise and <xn2> is equal to the integral of |xn|2 for frequencies less than resonance o [30]. The noise current at resonance is

23

in x 4kT 2 2 C = o VP ( ) 2 n = . Rx f x f

Equation 1-9

Note that above equation is exactly the expression for thermal noise in a resistor with value Rx. To minimize thermal voltage noise power in micro-resonators, this theory suggests that the series resistance Rx be minimized.
1.6 Analog to Digital Converters

A wide variety of analog-to-digital conversion schemes have been developed based on the requirements of sampling rate and resolution, including single and dual-slope, successive approximation, algorithmic (cyclic), flash, pipelined, and sigma-delta type converters. Among those types, flash, algorithmic, and sigma-delta are the most popular at present. Sigma-delta type converters are simple to implement, robust, and best suited for the low-frequency signals. They do not require ideal components and have been chosen for this work. Although the architecture is simple, analysis can be quite complicated.
1.6.1 Over-sampled analog-to-digital converters

Nyquist-rate ADCs require, sharp-cutoff analog low-pass filters to avoid aliasing. Such filters are difficult to implement, particularly in a high-temperature environment. In contrast, sigma-delta converters employ oversampling followed by a sharp-cutoff digital LPF [31]. RMS quantization noise generated with sampling can be calculated as
e
2 2

e 2 de =

2 , 12

Equation 1-10

where is the quantization spacing. The bandwidth of the quantization noise is the

24

sampling frequency fs. In-band noise can be calculated as illustrated in the following figure.

Noise Power

e2rms E(f)
2

fo fs/2 Frequency e2rms/OSR, OSR = fs/(2fo)

Figure 1-8 Illustration of in-band noise erms2/OSR is the noise power in the signal band. If fs is increased, quantization noise in the signal band decreases. This is a somewhat remarkable result. It implies that, in principle, quantization can be very crude in the initial sampling of the signal, and if the over-sampling ratio is high enough, an accurate representation of the original samples can be obtained by doing digital filtering of the noisy samples. Of course, large oversampling ratios are needed to make a significant reduction in e2. Also the model is based on the assumption of white quantization noise, which is only true for active signals. The above calculation assumes that the power density spectrum of the quantization noise is constant over the entire frequency band. The basic concept in noise shaping is to modify the A/D conversion procedure so that the power density spectrum of the quantization noise is no longer uniform, but rather, is shaped such that most of the noise power is outside the band. In that way, the subsequent filtering and down-sampling removes more of the quantization noise power.

25

1.6.1.1 Sigma-delta modulators

Sigma-Delta modulation [24,32,33,34] is a very robust technology for analog-digital conversion (ADC). The principle of a sigma-delta modulator is shown in Fig 1-9.

+VR Vin

-VR
Figure 1-9 Principle of sigma-delta modulator

Y out

In general, an ADC with Q quantization levels has a resolution of N bits where

N = log 2 (Q) .
Equation 1-11

The quantization noise power for an N-bit ADC is therefore

2 2V R = = 12 2 N 1
2 e

2V 12 NR 2

12 ,

Equation 1-12

where 2VR is the full-scale range of the ADC . If a signal has power of 2x, the signal-to-noise-ratio (SNR) is
2 SNR = 10 log x 2 e 2 = 10 log x V 2 + 4 .77 + 6 .02 N (dB)
Equation 1-13

In other words, a SNR improvement of 6 dB is equivalent to a resolution improvement by 1 bit. The quantization noise of a first-order sigma-delta modulator can be calculated

26

using the linearized model of Fig 1-10, in which the comparator is modeled as an additive source of quantization noise e[n].

Discrete Time Integrator x[n] z-1

e[n]

DAC
Figure 1-10 Quantization noise model for first order sigma-delta modulator (after [34). The ideal DAC is modeled as a unity-gain transfer function. The discrete-time integrator has transfer function of z 1 (1 z 1 ) . The modulator output is therefore given by Y(z) = X(z)z-1 + E(z)(1- z-1)
Equation 1-14

so that Hx(z) = z-1 and He(z) = (1 - z-1). The output is a delayed version of the input plus quantization noise that has been shaped by a first-order z-domain differentiator, i.e. highpass filter. The corresponding time-domain version of the modulator is y[n] = x[n-1]+(e[n]-e[n-1]), where the (e[n]-e[n-1]) term is the first-order difference of e[n]. Since H e ( z ) contains a zero at z = 1, quantization noise has zero response at dc. In general, H e ( z ) has large attenuation at low frequencies and amplification at higher frequencies such that total noise power is preserved. If the signal bandwidth f B is much smaller than the sampling frequency f s and a low-pass filter is used to process the
Equation 1-15

27

output, it is possible to obtain low quantization noise, i.e. high resolution. Since a 1-bit DAC is guaranteed linear (there is only one line between two points), it is common to use a 1-bit DAC and a corresponding 1-bit quantizer, which is simply a comparator. If the sampling frequency f s is high enough, the in-band noise power (i.e., the noise in the frequency range fB to fB at the output of a first-order sigmadelta modulator is [34]

ey = e
2 2

2 2 fB
3 fs

Equation 1-16

The SNR in dB is thus

2 fs SNR = 10 log( x2 ) 10 log( e2 ) 10 log + 30 log 2 f 3 B

( dB )

Equation 1-17

Defining R log2(fs/(2fB)),
2 2 SNR = 10 log( x ) 10 log( e2 ) 10 log 3 + 9.03R (dB ) .
Equation 1-18

For every doubling of the oversampling ratio, i.e. every increment in R, the SNR improves by 9 dB, or equivalently, the resolution improves by 1.5 bits. Thus, bandwidth can be traded for resolution. The sigma-delta modulator has a 1-bit digital output, and requires a decimation filter to recover the input signal. It applies a shaping function to the quantization noise, and a 1-b sample delay to the input signal. A sigma-delta modulator needs a highly accurate integrator since any error in the integrator will be coupled into the signal band.

28

Amplitude of the input signal is limited to VR.

1.7 Modulo-N Decimator Filter

The output of the modulator carries the input signal plus out-of-band components including quantization noise, circuit noise, and interference. Modulation noise and outof-band components of the input signal exist in the high and low frequency range, respectively. The out-of-band energy of the signal must be attenuated so that when it is resampled at the Nyquist rate it is not aliased into the signal band. An abrupt low-pass filter is necessary to achieve the theoretical performance in equations (17) and (18). These filters are expensive to build and decimation is generally performed in more than one stage. The first stage is designed to remove the highfrequency quantization noise. Low-frequency out-of-band components are removed with a high-order low-pass filter in the final stage of the decimator. Let us define fo, fd, and fs as the signal bandwidth, the intermediate decimation frequency, and the modulator sample frequency. When the noise at the output of the modulator is decimated to fd, the noise components in the vicinity of fd and harmonics of fd fold into the signal band. Thus, the zeros of the first-stage filter are best located at these points. There is no need for an abrupt cutoff at fo because noise in the range fo to fd-fo is not aliased into the signal band. A convenient filter for this decimation has frequency response sincK(f/fd), and K should be at least one order higher than the modulator to provide adequate attenuation of the high-frequency quantization noise. When the intermediate frequency fd is four times the Nyquist rate, the penalties of increased noise and droop in the frequency response of

29

the filter at the edge of the signal band fo, and the attenuation of the high-frequency components of the signal that alias into the signal band, are minimal [35]. Decimators with sincK response can have very simple implementations. An obvious approach for K = 1 is accumulate-and-dump, in which input words are added to the contents of a register and the sum is stored back into the register, except after each decimated sample, when the sum goes to the output and the register is cleared. An alternative method for designing decimators that gives simpler circuits for 2nd and higher-order filters is given in [36]. The input signal feeds to a cascade of K accumulators. The signal is then resampled at rate fd and feeds to a cascade of K differentiators. The nature of modulo arithmetic automatically corrects for overflow in the accumulators [36], providing that each accumulator and differentiator stage has at least Klog2(OSR)+1 bits. The circuit can be slightly simplified by replacing one accumulator and differentiating stage, together with the resampling switch, by an accumulate-and-dump stage. The decimation filter for the high-temperature wireless microsensor has been designed by a colleague using the modulo-N approach and K = 2.
1.8 Binary VCO for FSK Transmitter

VCOs are often used in the feedback path of the phase-lock-loop (PLL) circuits. Here, a simple VCO is used for implementation of a modulation scheme, which is known as frequency-shift-keying (FSK). The circuit schematic of the VCO developed for the high-temperature wireless microsensor is given in Fig 1-11 [37]. The serialized decimation filter is modulating a

30

MOS gate-capacitance which is modulates the resonant frequency (fo = 1/(LC)1/2) of the tank circuit. A tunnel diode is used to create a negative resistance, which cancels the resistance of the other passive components in the loop to permit oscillation. The tunnel diode operates with low bias voltage, 0.25 V, so consumes little power. L1 represents the inductance of the loop antenna and is one of the frequency determining passive components.

I TD (-R) Digital

L1 C2 C3

Decimation Filter Figure 1-11 Basic circuit diagram of the VCO (after [37]) The loop has high Q so presents a band-pass characteristic with narrow bandwidth and high amplitude at the resonant frequency. Based on the voltage versus capacitance characteristic of MOS gate-capacitance (C2), C2 is modulated by the binary input of the VCO. SPICE simulations have shown that the transition between the two frequencies happens in less than 3 cycles of oscillation.

2. Analysis of MEMS-based oscillators 2.1 Introduction

Much work has been done in solid-state oscillator design [38]. These oscillators can be divided into three groups in terms of their primary operating principle: 1) relaxation, 2) ring, and 3) resonator, including LC-tuned, crystal and most recently micromechanical [39]. This discussion will focus on the resonator group, especially micromechanical-based oscillators for high-temperature wireless sensor applications. In some cases, comparisons will be made with other types. There are a number of performance metrics for oscillators, including in-circuit Q, power dissipation, phase/amplitude noise, and short-term frequency stability, which are determined by specific topology selection. Depending on the application, one metric might be more important than the other. For example, minimum phase noise is crucial in communication systems, but it may not be particularly important for clocking an oversampled A/D converter. The latter application is the subject of this work. In the following section, oscillator theory is briefly reviewed. In Section 2.3, the reasoning behind the topology selection for micromechanical-based oscillators is explored and performance metrics, especially power consumption and in-circuit quality factor (Q) will be calculated. (In-circuit Q refers to the quality factor seen by the amplifier.) A micromechanical resonator by Haria et. al. having 7 Meg series resistance and 700 kHz oscillation frequency is examined as a candidate for an oscillator circuit.

32

2.2 Background 2.2.1 Oscillation Criteria

A(s)

(s) Figure 2-1 Basic positive feedback network An oscillation criterion can be developed using the feedback approach illustrated in Fig 2-1, a positive feedback circuit with no input. A(s) and (s) represent amplifier gain and feedback factor, respectively. The feedback network consists of frequencydependent passive elements, possibly a resonant device. At the frequency of zero phase shift, if the loop gain has magnitude >1, the circuit will oscillate with a growing amplitude. An automatic level control (ALC) mechanism [38] can be used to maintain a precise loop gain of 1 to obtain a pure sinusoidal output at a desired amplitude. In this analysis, an ALC scheme is not considered. Without ALC, nonlinearity will cause the amplifier gain to drop as amplitude increases, until loop gain is 1. The resonator will mostly remove this nonlinearity at the amplifier output and create a nearly pure sinusoid, depending on the value of Q, at the input of the amplifier. In crystal-based oscillators the amplifier circuit is the primary cause of nonlinearity, but the resonator dominates the amplitude limiting process [30] in micromechanical-based oscillators. An oscillation criterion can also be developed using the negative resistance

33

approach. The amplifier and other components of the active circuit are separated from the frequency-dependent device/circuit, and the admittance seen by each network is calculated. For stable oscillation, the real and imaginary parts of the two networks must cancel each other. In this analysis approach, root locus and Nyquist plots can be drawn to help visualize and determine the movement of the poles and the oscillation condition. Typically, this approach is used to analyze circuits based on a resonant device, where power loss in the resonator is compensated by the amplifier. In such oscillator designs, the phase shift of the amplifier circuit is desired to be near zero, but in general, there is some phase shift by the amplifier circuit. Thus, the resonator must operate slightly off resonance. If in-circuit Q is high enough, then frequency will not change much to compensate for the amplifier phase shift. It is important to note that not all oscillators are feedback circuits. For example, a negative resistance topology can be designed without a feedback loop using a physical device that creates a negative resistance. In this analysis, the negative-resistance approach and the negative-resistance topology refer to two different things. The negative-resistance approach can be used to analyze any type of oscillator, but a negativeresistance topology refers to an oscillator that was a negative-resistance device. Both analysis approaches can be applied to all oscillator topologies but a particular approach may be more convenient for some topologies. In this paper, the feedback approach is used because it is suitable for a wide range of topologies, and provides good insight. It is noted here that conventional methods of predicting oscillatory behavior are

34

not always valid and may provide misleading results. It was shown in [40] that, particularly for microwave resonators operating in the microwave region where the effects of parasitic elements are very significant, Eq 2-1 and 2-2 for the feedback approach
T ( z ) = 0 | T ( z ) |> 1
Equation 2-1 Equation 2-2

and, Eq 2-3 and 2-4 for the negative resistance approach

Ramp ( x ) + Rres ( x ) < 0
Equation 2-3 Equation 2-4

X amp ( x ) + X res ( x ) = 0

are not always valid for predicting circuit instability. The problem occurs since due to the parasitic elements there can be two frequencies satisfying the criterions given below. In this case, the Nyquist and root-locus analyses are useful techniques. In this paper, oscillation frequencies around 1 MHz are considered, and the conventional techniques are reliable.
2.3 Topology Selection

The Q factor of MEMS resonators is very high, making them a candidate for stable oscillators. The most challenging factor in the design of micromechanical-based oscillator circuits is the very high series resistance (many Meg). In the following sections, different topologies are examined in terms of power consumption and in-circuit Q.

35

2.3.1

Negative-Resistance Topology

This topology is popular in communication applications for having very good phase noise performance [41]. The typical implementation uses a negative-resistance circuit; as shown in Fig 2-2, but the feedback amplifier can be replaced by a negative-resistance device such as a tunnel diode. If the resonator is modeled as a parallel RLC and if Rp->, the LC-tank would oscillate indefinitely without the need for Gm.

Figure 2-2 Negative-resistance Topology Finite resistance is unavoidable, however, and some current flows through this resistor, resulting in power dissipation. At the oscillation frequency, the resistance seen by the resonator must be negative and have magnitude less than Rp to permit oscillation, in other words, the sum of the admittance must be negative. In the circuit of Fig 2-2, an active device having a transconductance Gm is connected in a positive feedback loop such that negative resistance is Gm, i.e. the oscillation criterion is
Gm 1 , Rp
Equation 2-5

36

where Rp = Q2Rx is the well-known series-parallel equivalence for high-Q devices [42]. In Fig. 2-2, Cp is the shunt parasitic capacitance. It is often dominated by packaging capacitance. Since the SiC resonant structure is off-chip in this work, Cp will be at least 3-pF. In an integrated process, this capacitor would be much smaller. From Eq 2-5, high Rp means low Gm, and low Gm means low power. Low-power is an important objective, but this topology is not useful for MEMS-based oscillator because Cx is extremely small and Lx is extremely large (23 aF and 2356 H [43]). Since Cx << Cp, even in an integrated process, the oscillator frequency would be

osc 1 / L x C p , a very low frequency that is very sensitive to Cp.

Thus, the Negative-Resistance topology is not a good choice because of a parasitic shunt-capacitance across the resonator. In fact, any topology that connects the resonator directly to ground suffers from this problem, even if the MEMS resonator and electronics are integrated.
2.3.2 Pierce Topology

The Pierce Topology is shown in Fig. 2-3. This topology is well known for its high in-circuit Q and simple design, and is sometimes called the three-point topology.

37

Figure 2-3 Pierce Topology To sustain oscillations, the phase-shift around the loop must be 360. The amplifier in Fig. 2-3 is an inverting type, so another 180 of phase shift is required in the loop. It is achieved using two capacitors Cin and Cout at the input and output nodes of the amplifier, respectively. These capacitors each introduce an additional phase shift of 90, providing
1 << R x o C in and 1 << Rout o C out
Equation 2-6

which is easily satisfied. In a MEMS resonator, however, the magnitude criterion is difficult to satisfy since T ( o ) Gm R x o C out C in
2

Equation 2-7

The capacitors increase the in-circuit Q, and improve frequency stabillity but also dictate an amplifier with a very high transconductance gain. Since Rx in quartz crystal is low, a one-stage amplifier is adequate. With a MEMS resonator, however, one stage is

38

not enough, and since an odd number of stages are required, a 3-stage approach is an option. Excess phase shift and power consumption is unattractive, however.
2.3.3 Transresistance Topology

The transresistance topology is more suitable than Pierce when Rx is large since it is based on the assumption Rin << R x and Rout << R x .
Equation 2-8

The basic circuit topology is shown in Fig 2-4. In this topology, there is no phase shift in voltage from input to output of the amplifier as shown in Fig. 2-4, i.e. a non-inverting amplifier is required. It can be easily shown that the in-circuit Q will be close to that of the resonator, i.e.
Q=

o Lx
R x + Rin + Rout

o Lx
Rx

Figure 2-4 Transresistance Topology At resonant frequency, the loop gain is

T ( o ) = Rm Gm Rin Rout , = Rx Rx

for Rout << Rx.

Equation 2-9

In this circuit, input and output capacitance is undesirable, but unavoidable. Their

39

effect on phase shift can be minimized if 1 >> Rin o C in and 1 >> Rout , o C out
Equation 2-10

which can be achieved by lowering the input and output resistances of the amplifier. If resistances are 10 times smaller than this limit then Eq 2-9 can be rewritten T ( o ) = 0.01Gm R x o C in C out
2

Equation 2-11

Therefore, it is desirable to minimize Cin and Cout such that Gm can be reduced while achieving adequate gain.
2.4 Conclusion

In both the Pierce and transimpedance topologies, the loop gain can be written

T ( o ) =

Gm Z in Z out Rx

Equation 2-12

In both cases, loop gain must be greater than one for oscillation. Input and output impedances Zin and Zout in Eq 2-12 vary in both topologies. In the Pierce topology, two capacitors are added to the input and output port to ground, and the input and output resistance of the amplifier is designed to be much higher than the magnitude of the impedance of the capacitor. On the contrary, input and output resistances are designed to be much less than the magnitude of the impedance of the parasitic capacitances in the transresistance topology. At the resonant frequency, capacitance will dominate the input impedance in the Pierce topology, and resistance will dominate the input impedance in the transresistance topology.

40

In comparing these two topologies, the ratio of the input/output impedance to the series resistance is critical, since this ratio determines the Gm requirement, and therefore power. In the Pierce topology, it is desirable to minimize Cin and Cout, but this results in the variation of the oscillation frequency with parasitic capacitance. As illustrated by Eq 2-10, it is also desirable to minimize capacitance in the transresistance topology, and in this case both frequency stability and power is improved. With the high series-resistance of the MEMS resonator, the Pierce topology requires at least three stages of amplification. It can be implemented in two stages by using a transresistance topology. The transresistance topology is also easier to bias. The transresistance amplifier has the further advantage that it could be used both in sensor interface circuitry and the oscillator.

3. Transresistance amplifier design for high-temperature transducers with very large series resistance

Discrete and CMOS SOI versions of a transresistance amplifier have been designed. The MEMS resonator of interest has a 7 Meg series resistance and 700 kHz oscillation frequency, and the amplifiers have been designed to meet the oscillator requirements, namely positive Rm gain > 7 Meg. Providing the amplifiers meet this requirement and has small phase shift at the resonant frequency, the oscillator circuit is formed by just connecting the resonator between the input and output of the amplifier. To obtain adequate gain, with near zero phase shift, an even number of common-source stages are required. Two stages are used in both designs. In addition to the two stages, both versions include source-follower stage at the output to decrease the output resistance.
3.1 Transimpedance amplifier using discrete high-temperature BJTs

The design using discrete BJTs is shown in Fig 3-1. Series RxLxCx models the MEMS resonator and component values were obtained from [43].
3.1.1 Biasing

Despite the use of Darlington pair BJTs, non-zero base current dictates the use of AC coupling between stages to isolate biasing. The base current of Q1 creates a voltage drop across Rf1, which raises the collector voltage of Q1 above 2VBE. Since the base of Q3 also operates at 2VBE, this voltage would appear as an offset to the 2nd stage, if dc coupling was used. The offset is directly dependent upon , and therefore sensitive to T. If Q1 is biased with 0.1 mA and =100, VRf1 is 0.1 V and the output stage is entirely saturated since the 2nd-stage gain is Rf2/Rs=-10. If Q1 is biased with 10 A and =100, VRf1 is 0.1 V, and

42

the output is 2VBE 1V, leaving about 0.4 V of downward swing (at room T). However, at this low level of bias current, Q1 has inadequate gm to meet the BW requirements.

Resonator model

1st stage

2nd stage

Output follower

Figure 3-1 Circuit schematic for the two stage discrete version of the transresistance amplifier . Therefore, AC coupling is required in this BJT design to decouple Q1 bias current from output offset-voltage.
3.1.2 Transimpedance Gain

To make the overall gain less dependent on the active device characteristics such as transconductance gm, which is directly related to the temperature, voltage gain is set by

43

resistor ratio. This selection also makes the biasing more reliable for the discrete circuit implementation. The ideal closed-loop Rm gain is Rm = R f 1R f 2 Rs
.

To achieve the ideal gain, most signal current must pass through Rf1 and Rf2. To decrease the signal lost to the input of the amplifiers, the resistance seen looking into feedback resistor Rf, Rf/|av1|, must be much smaller than the input resistance of the active device, Rin, as specified in the following equation. Rin << Rf a v1
Equation 3-1

To increase Rin, the Darlington configuration is used. Otherwise, the signal lost to the active device is overwhelming. The open loop voltage gain, av1, of a BJT amplifier is simply.
a v1 = g m RC = I C RC V = RC , Vth Vth
Equation 3-2

where VRC is the bias voltage on the collector resistor. In both CE stages, VRC2 V when Vcc=3.3 V, so open-loop gain is about 80 at room temperature. To obtain accurate closed-loop gain, let g m RC >> Rf RS
, Equation 3-3

where Rs is the source resistance. In the 1st stage Thus, the open-loop gain is adequate.

Rf Rs

= 7 , while the second stage is 10.

44

3.1.3

Bandwidth

There are unavoidable shunt capacitors (Csh1, Csh2) at the input of the amplifiers due to PCB fabrication, and they are added to the circuit schematic given in Fig 3-1. To decrease the signal lost to the shunt capacitor, and also for high bandwidth requirements, the following equation must be satisfied. Rf 1 << oC av
Equation 3-4

Q1 and Q3 act as a source follower. Q2 and Q4 provide voltage amplification. Due to the high open-loop gain that is required, the Miller capacitances C2 and C4 are the major bandwidth-limiting factor. To decrease the effect of these capacitors, a resistor, RE, is added to the emitters of Q1 and Q3 to increase their bias current and transconductance. Since the Miller capacitances see 1/gm, the associated 3 dB pole frequency shifted towards a much higher frequency. These pole frequencies must be shifted to frequencies >> 700 kHz to avoid excessive phase shift at the operating frequency. An oscilloscope probe with 13 pF will be connected to the output node for measurement. For this load capacitor not to be a bandwidth-limiting factor, the output resistance must be made adequately low, i.e.
R 1 1 + C 2 << . g m3 3 oC L
Equation 3-5

3.1.4

Selection of the circuit variables

Collector resistors RC must be low enough to drive the input capacitance of the following stage, but not so low to waste power. Their value does not directly affect open-

45

loop gain. Large Rf will provide high gain, but selection is limited by the shunt capacitor Csh. Similarly low RS helps gain, but will load the 1st stage. A high power supply voltage, VCC, is desired, since high open-loop gain has benefits illustrated in Eq 3-4 and 3-5. However, power increases Vcc(Vcc-2VBE) and minimum power is desired for the wireless microsensors. Also, simulation has revealed a problem with phase margin when Vcc was raised above 4.5 V.
3.2 CMOS SOI Design

The block diagram of the CMOS SOI amplifier is presented in Fig. 3-2. The design consists of biasing, an amplifier that produces Vout, and a digital buffer that produces y. (The same bias circuit is used by the sigma-delta modulator.) The amplifier circuit uses only one voltage (PBIAS) from the bias circuit for its current mirrors. Its second amplifier stage is biased with a common mode feedback circuit, and the rest is self-biased. The key differences between discrete and IC versions are as follows: 1. there is no need for the Darlington configuration in the amplifier, since the input resistance of the MOS transistor is infinity; 2. biasing is based on the replica technique, not feedback, and includes a band-gap reference; 3. parasitic capacitances are much lower in SOI CMOS devices, so, the bandwidth is larger, and phase shift in the amplifier is smaller. Details are discussed in the following sections.

46

Resonator Model

Figure 3-2 Block diagram of the CMOS SOI version of the transresistance amplifier.
3.2.1 Band-gap reference circuit

The reference voltage (VR+ - VR-) sets the scale factor of the ADC. Any fluctuation due to voltage, temperature, etc. directly corrupts the output of the ADC. Therefore, a reference circuit, which has low temperature coefficient (TC), is needed in this hightemperature application [44].

47

The reference circuit used in the previous bulk Si designs was a VBE-referenced circuit. The VBE of a BJT has a negative TC of about 2mV / C , depending on the process. In the well-known bandgap reference, a positive TC is used to compensate the negative TC of VBE. The idea of a band-gap voltage reference is illustrated in Fig. 3-3. The thermal voltage VT , i.e. kT / q , is used for this purpose. VT has a positive TC of about
+ 0.085mV / C . Using the two TCs mentioned above, zero TC can be achieved if K is

about 20.

VBE

VT Generator

Vout = VBE + KVT

Figure 3-3 The principle of the band-gap reference circuit (after [44]). The SOI implementation has these challenges: 1) a BJT is not available in the SOI process; 2) the 3.3-V power supply limits the value of the reference voltage. In regards to the first, a diode can be used instead of the BJT, and the SOI process does offer isolated PN diodes. In regards to the second, the reference scheme must be adjusted. In the bulk Si design, shown in Fig. 3-4, three levels of reference, VR-, CMREF

48

and VR+, were provided. The power supply is 5 V, and there is a 1.2 V difference between consecutive reference voltages.

Figure 3-4 Schematic of the bulk Si design of the band-gap reference circuit (from [45]). In the SOI band-gap reference circuit design, only two levels of reference voltage can be generated, as limited by the 3.3 V supply. The first version of the SOI design [46] is shown in Fig 3-5. The present version, given in Fig 3-6, is quite similar. The major differences are summarized here. 1. In the SOI technology, the drain-source resistances of the transistors are low. Thus, bias voltages are sensitive to supply voltage fluctuations. For this reason, in the current version, a triple cascode current mirror is used to increase the output resistance. Fig 3-7 shows simulation of the power supply rejection. The voltage supply is swept from 2.4 V to 4 V with 0.01 V increments, and reference voltages are plotted. Although not perfect, as shown in Fig 3-7 reference voltage levels are quite constant near Vdd=3.3 V. The differential reference voltage has a sensitivity

49

of 80 mV/V at low frequency.

Figure 3-5 Schematic of the band-gap reference circuit in SOI [46]. Device dimensions are in units of =0.25 m. 2. In the Peregrine SOI technology, the voltage drop across the diode is high since the emission coefficient N is high, around 1.4, where I D = I o eVD q / NkT 1 . As a result, the first version of the SOI design [46] could not be used. Instead, one of the resistor-diode pairs is replaced by a simple diode. Although the diode voltage will change with temperature, the voltage across the diode and the resistor (R2 and D3) will be constant, and the differential voltage (VR+ - VR-) will stay the same. The common-mode reference CMREF is sensitive to temperature, but this level has a minor effect on OPAMP performance.

))

50

Figure 3-6 Current schematic of the band-gap reference circuit in SOI. Device dimensions are in units of =0.40 m.

51

60 0m

40 0m

20 0m

(VR - VR ) VDD

SL> E> 0 dVX:r)VX:r) ((1V+-(1V-) 30 .V

20 .V

VR+ VR+- VR10 .V

VR0 V 24 .V 26 .V 28 .V ((1V+-(1V-) VX:r) VX:r) VX:r)VX:r) (1V- (1V+ 30 .V 32 .V VV _1 34 .V 36 .V 38 .V 40 .V

Figure 3-7 Simulated variations in the reference voltages and the slope of the differential reference voltage due to the supply voltage variations. The reference current generated by this bias circuit is calculated as follows. Twelve transistors, M1 M12, force the current through the two branches to be equal; and the voltage at the source of M11 and M12 are equal. Thus, the current through R1 can be easily determined to be [47]

52

I R1 = VT ln A R1 ,

Equation 3-6

where V T = kT q , and A is the size ratio between D2 and D1. In Fig. 3-6, A is 10, R1 is 20 k, N is 1.6 and at room temperature, VT is 26 mV, so, the current through R1 is about 5 A. The gate voltage of M1 is the current mirror gate voltage, PBIAS. The unit size of mirror transistors for 5 A is 10 / 4, so |VGS-VT|0.3 V. The band-gap reference works as follows. The current through R2 is ten times that of through R1. In other words,
I R 2 = 10 I R1 = 10 N VT ln( A) R1 .
Equation 3-7

The voltage across R2 is

VR 2 = R2 I R 2 = 10 NVT ln( A) R2 / R1 .
Since R1 and R2 are equal, then,

Equation 3-8

VR 2 = 10 N ln( A)VT .
Therefore, the differential reference voltage is

Equation 3-9

VR VR = VD 4 + VR 2 = VD 4 + 10 N ln( A)VT

Equation 3-10

where VD4 has a TC temperature dependence of about 3 mV/C, higher than a bulk silicon process due to the emission coefficient. SPICE simulation verifies that 10 ln(A)23 is the proper choice for low temperature coefficient. Compared with the bulk Si design [45] in Fig. 3-5, the new design has an obvious drawback. In the bulk-Si design, the reference voltages are driven from the emitters of the BJTs, so that the output impedance of the reference voltage is small. The low

53

impedance is beneficial for the switched-capacitor circuits. Unfortunately the BJT is not available in the SOI process, and the output impedance of VR+ has series R2. For this reason, R2 must be as small as possible. The sigma-delta requires a common-mode reference near the middle of the two reference voltages, VR+ and VR-. In this design, a push-pull source follower is used for this purpose. Two low-threshold transistors (|VT| is about 0.2 V). Since (VR+ - VR-)1.8 V, |VGS-VT| 0.7 V for these transistors. M10 M13 act as a start-up circuit. M13 is a PMOS with regular threshold voltage, to insure that there is no current through M13 in normal working condition. Besides M13 M15, all MOSFETs in the bias circuit are intrinsic devices.
3.2.2 Transresistance amplifier

The schematic of the overall amplifier is given in Fig. 3-8. The first stage, M1-M5,is a transresistance amplifier using a cascoded common source amp. M4 is used as a feedback resistance. It is biased in the saturation region using current source M5. The feedback resistance is 1/gm4. With a source resistance, Rx the voltage gain from input to the output of the first stage is Rx/gm4. In the current design, the resistance 1/gm4 is roughly 200 k. The first stage, M1-M3, is cascoded, to provide a higher open loop gain and more importantly wider-bandwidth, compared to a simple common source amplifier.

54

1st stage cascode

Level Shifter

Biasing 2nd stage Push-pull cascode amp.

CMFB amp. Biasing

Figure 3-8 Schematic of the transresistance amplifier circuit in SOI. Device dimensions are in units of =0.40 m. A source-follower stage, M6-M7, is added after the cascode stage to decrease the output resistance and lower the level of the output voltage to match the input level of the second amplifier stage, M10-M13. The second stage is fully cascoded to provide higher voltage gain and buffered using push-pull transistors M15-M16. The gain is high enough that a feedback bias circuit, M20-M24, is implemented to insure accurate biasing of the second-stage amplifier. This differential feedback

55

amplifier uses an off-chip compensation capacitor between nodes cap and Vdd to set its bandwidth and insure stability. The feedback amplifier forces the output voltage to be feedback bias voltage, about 1.7 V, for frequencies within its bandwidth. In other words, it imposes a high-pass characteristic on to the transimpedance amplifier. The simulated magnitude and phase response of the feedback bias loop, including differential amp, cascaded second stage, and push-pull buffer, is shown in Figs 3-9 and 310 with CC = 0.1 F, the feedback loop has a unity gain frequency of about 31 kHz. The phase margin is nearly 90.
60

40

20

-20

-40 10Hz DB(V(U3.R3:1))

100Hz

1.0KHz

10KHz Frequency

100KHz

1.0MHz

10MHz

Figure 3-9 Magnitude response of the feedback-biasing loop for CC = 0.01 F.

56

180d

138d

92d

46d

0d

-46d 10Hz P(V(U3.R3:1)) 100Hz 1.0KHz 10KHz Frequency 100KHz 1.0MHz 10MHz

Figure 3-10 Phase response of the feedback-biasing loop. The overall magnitude versus frequency response is given in Fig. 3-11. Gain for Rx = 7 Meg is greater than one between 7 kHz and 2 MHz. The phase shift at the resonant frequency, 700 kHz, depends on the capacitive load at the output of the push-pull buffer. As shown in Fig. 3-12, for 1 pF, phase shift is around 13 degrees, but for 3 pF it is about 23 degrees. In either case, since the amplitude is larger than one, phase shift will be compensated by the resonator with a small frequency shift providing the in-circuit Q is large. Note that, since the resonator will be connected between input and output, the parasitic capacitor is unavoidable.

57

Figure 3-11 Magnitude versus frequency response of the transresistance amplifier with 7 Meg source resistance and CC=0.1 F.

Figure 3-12 Phase response of the transresistance amplifier for 1, 2, and 3 pF loads. Source resistance is 7 Meg and CC=0.1 F.

58

3.2.3

Oscillator

The proposed MEMS-based oscillator is shown in Fig 3-13. A piece-wise linear voltage source V7 is used to start the oscillation, but in reality noise is adequate. The oscillator output from simulation is given in Fig. 3-14. The output is seen to oscillate at 700 kHz.

start pulse Figure 3-13 Circuit schematic of the oscillator

59

2.647V

2.400V

2.000V

1.600V

1.200V

0.841V 146.44us 148.00us V(vo)

150.00us

152.00us

154.00us

156.00us

158.00us Time

160.00us

162.00us

164.00us

166.00us

168.00us

170.00us

Figure 3-14 Simulation result of the 700 kHz oscillator. The amplitude variation in the simulation is caused by the numerical error due to the simulator.

4. Circuit Design of the Sigma-delta Modulator 4.1 General Performance Issues

This work presumes a sensor with a low bandwidth, << 8-kHz and a resolution requirement of 8- bit. Thus, a 1st-order architecture is adequate. Although this work requires neither a high-resolution nor a high-speed sigma-delta ADC analysis of such is presented in this section.
4.1.1 Correlation of Quantization Noise with the Input Amplitude

The quantization noise from a basic 1st-order sigma-delta converter such as presented in Chapter I is highly correlated, thus, the oversampling ratio needed to achieve a resolution greater than 12- bit is prohibitively large [48]. More specifically, if the sampling rate is much higher than the input signal band, such that the input approximates dc, the modulator generates pulses in recurrent patterns that depend on the input level, and when the repetition lies in base-band, resolution decreases [49]. The addition of a dither signal disrupts these limit cycles and improves resolution. A convenient dither is a square wave with an amplitude approximately 1/16th of the peak signal-level [50]. The drawback of the dither signal is that it reduces the maximum input by the amplitude of the dither. The 1/16th dither provides approximately maximum dynamic range.
4.1.2 Nonlinear Effects

High resolution corresponds to high signal-to-noise ratio. In addition, distortion occurs due to nonlinearity in the circuit. As implemented in this design, a differential topology minimizes even-order harmonics, so the 3rd harmonic is expected to be dominant.

61

Nonlinearity can occur during sampling. Referring to the integrator Fig. 4-1, when S1 is opened, input dependent charge injection introduces nonlinearity in the charge stored on C1. Also, the capacitance of the source/drain junctions of the switches S1 and S2 is nonlinear, but this problem can be corrected by using bottom-plate sampling as shown Fig 4-2.

C2 Vin S1 P S2 C1 + Vout

Figure 4-1 Basic Integrator. A fully differential version of the bottom-plate scheme is implemented in this design. S3 is opened first, and this creates some offset on C1, which is cancelled by the differential operation.

C2 Vin S1 S2 C1 S3 S4 + Vout

Figure 4-2 Integrator with bottom-plate sampling.

62

4.1.3

1/f Noise and Offset Reduction with Chopping

Noise can be attributed to quantization, switches, and the opamp. Quantization noise can be reduced with higher sampling-rates and using a higher order of sigma-delta converter, which better shapes the noise in the base band. Chopping is an effective technique to remove the opamp offset and 1/f noise. The basic idea is shown in Fig 4-3. The noise spectrum of the opamp is not affected by the first multiplier, but after the second multiplier the spectrum moves to the odd harmonics of the square wave. Thus at the input of the second amplifier, the noise power in baseband is lowered.

Figure 4-3 (a) Concept of chopper stabilization. (b) Equivalent input noise for the circuit in (a). (from [51]).

63

Vin+ Vin-

-+ +-

Vout+ Vout-

(a)

Vout+

Vin+ Vin-

-+ +Vout(b)

Figure 4-4 Illustration of dynamic element matching and opamp chopping to minimize opamp offset and 1/f noise: (a) concept; (b) implementation.
4.1.4 Switch and Opamp Noise

When the quantization noise level is reduced sufficiently, switch and opamp noise sources limit resolution. During sampling, the on-resistance of the switch has thermal noise. This noise power is independent of the resistance, since in the product of the

64

bandwidth and the magnitude, the resistance cancels. The total noise power sampled onto a capacitor C is simply v 2 = kT / C . The noise spectrum is white. A 1 pF capacitor at room temperature has samples rms noise of 64 V, much less than the desired resolution in this application. The input-referred thermal-noise-power of the fully-differential operational amplifier (FDOA) given in Figure 4.8 is given by
2

en

2 2 g = 2 en1 + en 4 m 4 g m1

g + en8 2 m8 g m1

Equation 4-1

where en1, en4, en8 are the mean-square gate-voltage noise of the respective transistors. Design parameters are gm1 = .632 mho, gm4 = .16 mho, and gm8 = 3.05 mho, and thermal noise spectral density is 8 kT . The unity-gain frequency of the FDOA is gm1/CC and CC 3 gm

is the effective single-ended load capacitance, 4 pF. Thus, the total noise-power inherent to the FDOA is en
2

g m1 1 2 = (1.7 V ) . This noise is amplified by C C 2

2

Vcl = Vol

(C s + C p + C f ) (C44244f ) 22 44C2444 2 f s + Cp + C 1 31 31 4 3 filter Cf

leakage noise gain

so effective FDOA noise ignoring Cp is 2.8 mV rms.

4.1.5 Settling-time

There are two settling phases, the charging of the capacitor (sampling), and the opamp response (integration). Each phase has to be completed in one-half clock cycle.

65

The charging time is determined by the RC time constant of the switch, and the opamp response is by its unity-gain bandwidth, feedback factor, and slew rate. Settling problems due to the RC time constant of the MOS switch and the switched capacitor can usually be solved by simply increasing the width of the switch, the limitation being that as the switch becomes larger in comparison to the switched capacitor, the errors due to channel charge-injection and the parasitic junctioncapacitances also increase. A folded-cascode amplifier with internal compensation and source-follower buffers is used in the integrator. The slew rate of the folded-cascode amplifier is determined by the ratio of the 1st-stage current to the compensation capacitance, so it can be increased as required at the expense of increased power. If the opamp is assumed to have a single pole and is not slewing, then the response of the integrator to a new input sample will be exponential with a time constant given by

(1 +

Ci ) , where o is the unity-gain bandwidth, Ci is the total capacitance on the Cf

summing node, and Cf is the feedback capacitance. In general, the integrator gain should be made as small as possible to obtain the fastest settling. On the other hand, integrator gain should be adequate to provide a strong signal to the comparator. As is common practice, a gain of was used in this design such that the integrator output range is equal to the reference voltage. The settling can be signal independent (linear) or signal dependent (nonlinear). If the integrator does not settle fully but settling is linear, then just a gain error occurs and it has

66

been shown that this has no effect on sigma-delta performance. On the other hand, if settling is nonlinear, distortion occurs. Therefore, it is critical to provide high slew rate. The nonlinearities due to the voltage-dependent capacitors and signal-dependent charge-injection from switches can limit linearity. These effects are difficult to model analytically, and unreliable to simulate, but are generally less than 0.1%. Likewise, nonlinearity due to inadequate opamp swing is difficult to model, even simulate, but the integrator gain of suppresses output swing to VR.
4.2 Differences between the design of the silicon and the SOI circuits

The sigma-delta modulator was originally designed using a bulk silicon CMOS process, as described in [46]. To convert the designs from bulk silicon to SOI, some general changes were made. 1. Since the feature size is smaller in the SOI process, was changed from 0.6 in the bulk process to 0.40 in the SOI process. 2. There is no bulk contact in SOI technology, so these were eliminated from the layout. 3. The power supply for SOI circuits is 3.3 V. For the bulk silicon, analog power supplies are 3.5 V, and the digital power supply is 5 V. Since a single supply is used in the SOI circuits, no level shifting circuits are needed, but a common-mode reference level (CMREF) replaces analog ground. 4. In bulk silicon circuits, there is only one type of PMOS transistor and one type of NMOS. In the SOI circuits, intrinsic devices with zero threshold voltage are

67

used in most of the analog circuits, while regular threshold-voltage transistors are used in the digital circuits. 5. Since the feature size is smaller in the SOI process, the small-signal output impedance of transistors is smaller. To achieve adequate opamp gain, a relatively large length was used for the transistors at the output stage.
4.3 SOI version of the sigma-delta modulator

A first-order sigma-delta modulator has a one-bit output, which represents the signal. Thus, the quantization noise is large. However, the frequency distribution of the quantization noise is shaped by the loop, while the input signal is passed unshaped. The overall quantization noise at the output can therefore be reduced using a low-pass decimation filter, where the bandwidth of the filter is set according to the bandwidth of the input signal. Thus, the input signal can be accurately recovered from the output bit stream. The decimation filter is separate from the modulator and is not considered here. There are three major blocks inside the sigma-delta modulator chip: the clock generator / control unit, the bias generator and the sigma-delta modulator itself. The first generates multi-phase non-overlapping clocks for the sigma-delta modulator, required since switched-capacitor circuitry is used. It is also responsible for control signals required by chopper and dither circuits to improve the performance of the sigma-delta modulator. The bias generator provides bias currents for the analog portion of the circuits, and also provides the reference voltage for the sigma-delta modulator. Because the chip needs to work at high temperature, a band-gap reference-circuit [52] was used to

68

obtain a relatively constant reference voltage at high-temperature. A switched-capacitor topology was used to realize the sigma-delta modulator. The simplified schematic is shown in Fig 4-5. There are two key components inside the sigma-delta modulator: a switchedcapacitor integrator and a switched-capacitor comparator. Both integrator and comparator exploit fully-differential topology. Although a fully-differential circuit consumes slightly more power, it has much better PSRR and CMRR, key in mixed-signal applications. Also in high-temperature applications, a fully-differential topology has lower TC because of its symmetry. The modulator has differential inputs, Vi+ and Vi-. Differential reference voltage, Vr+ and Vr-, are provided by the band-gap bias circuit. There are two digital outputs, DS+ and DS-, from the comparator. The sigma-delta modulator uses chopping and dither for improved stability and resolution. Ignoring these additional controls, the clock scheme for the switchedcapacitor sigma-delta is shown in Fig 4-6. Non-overlapping clocks, Phase1 and Phase 2, are used in the switched-capacitor sigma-delta modulator. The master clock is 1 MHz. Control signal ResetB is a complementary version of Phase 2 used to reset the comparator. The Regen signal triggers regeneration inside the comparator to obtain valid digital outputs.

69

P1: Phase1 P2: Phase 2 DSFB Vr+ VrP2 Chop P1 Vi+ ViP1 P2 P2 C3 C1 P1 CMREF C2 C4 P2 DSFB DS+
Q D

Chop P2 P1 C5

Switched-capacitor Integrator
Vout+

P1

C6 Vout-

P2 P1 C7 C9 CMREF

Chop DS-

P2 P1
Q D

ResetB (Phase2B)

C10 Regen C8

Phase1

Switched-capacitor Comparator

Phase2

Figure 4-5 Simplified schematic of the sigma-delta modulator [after 46].

70

MCLK Phase 1 Phase 2 ResetB Regen

0.5sec

1sec

Figure 4-6 Clock phases for the switched-capacitor sigma-delta modulator [from 46]. Inside the switched-capacitor integrator, C1 and C2 are input capacitors and C5 and C6 are feedback capacitors. The ratios C1 / C2 and C5 / C6 are 0.5. Thus, the integrator has a gain of 0.5, which limits the output of the integrator to VR. In Phase 1, C1 and C2 are charged with Vi+ or Vi- depending on the polarity of Chop. Also in Phase 1, C7 and C8 connect to the differential outputs from the integrator, the comparator determines the polarity, and following Regen at the end of the Phase 1, an output is produced and latched. Two dynamic D flip-flops (Fig 4-7) latch the outputs from the comparator, and generate the feedback control signal DSFB. PhIn is Phase 1 and Phout is Phase 2. The output node of the clocked inverter is the dynamic storage node. When Phase 1 is high, the t-gate turns on and captures the data produced by the comparator. When Phase 2 is on, the dynamic node is charged and the new output is driven. Thus, data is captured on

71

the falling edge of phase 1 and driven on the rising edge of Phase 2. During Phase 2, DSFB is used to control the polarity of the sigma-delta feedback applied via C1 and C2.

Figure 4-7 Dynamic D flip-flop. Although the inputs of the switched-capacitor in Fig 4-5 comparator look complicated, it performs one simple function: the polarity of the integrator output. Capacitors C9 and C10 perform no function in this application.
4.4 Chopping, Dither, and Dynamic Element Matching

Chopping and dynamic element matching were discussed with the help of Fig 4-4. The full schematic of Fig 4-5 implements these techniques and additionally incorporates dither and the sigma-delta feedback. A square wave dither is added to the input signal using a second set of input caps C3 and C4 that are switched between VR+, VR- and CMREF. When Chop = 1, dither is + C3/C5. When chop = 0, dither is - C3/C5. The ratio C3/C5 is set to obtain an amplitude of (1/16)VR, as suggested in [50]. Sigma-delta feedback is applied via C1 and C2, the only complication being the

72

necessity to XOR the output with Chop in order to provide the correct polarity in both phases of the Chop cycle. Timing of the chop signal is critical. It must not change after Phase 1 in order to be consistent with the sampling in Phase 1. Instead, it should change at the beginning of the Phase 1. In this design, chop changes after Phase 2 goes low and before Phase 1 goes high. Since C1,2 = 0.5 pF, C3,4 = 0.06 pF, and C5,6 = 1.0 pF, the increment at the output of each cycle the integrator is

1 + + + Vout = Vc 5 Vc 6 = [(Vi Vi ) (V R V R )] 0.06(VR VR ) 2

Equation 4-2

The polarity of the second term depends on the comparator output and the 3rd term is controlled by the square wave chop signal. The 3rd term averages to zero while the second term averages to equal the input. In summary, the Chop control signal does not change the signal transfer-function of the circuit. It is used to cancel any mismatch between C1 and C2, and therefore improve CMRR as well as offset and flicker noise of the switched-capacitor integrator. The chop signal is also used to control the dither. Artifacts created by chop have frequency components at integral multiples of the chop frequency and are conveniently eliminated by a sincK(fT) decimation filter. In this design, Chop has a frequency 64 times lower than the master clock, and is fixed within the clock generator circuit.
4.5 Circuit Details

The integrator amplifier is key to obtaining high performance. In this application,

73

noise performance of the amplifier is relatively unimportant, but slew rate and settling time must meet the 8-bit resolution goal using minimum power and with high CMRR and PSRR since the high-temperature power supply is uncertain. The amplifier uses the wellknown, fully-differential cascode configuration with common-mode feedback biasing provided by a continuous-time amplifier. The power supply for the circuit is 3.3 V. All transistors in the FDOA are intrinsic devices. The intrinsic devices improve voltage swing at the output. The schematic of this FDOA is given in Fig 4-8. M1 M11 form a folded- cascode amplifier. M1 and M2 are PMOS input transistors with relative large shape factor for large tranconductance. PBIAS is a current-mirror voltage from the bias circuit which creates a tail current for M1 and M2 of about 20 A. M4 M11 form the cascode output stage. The cascode stage has a large output impedance, so the amplifier has large voltage gain. M24 M29 provide cascode bias voltages for NMOS and PMOS transistors. The cascode voltage is made just large enough to make sure every transistor (M4 M11) is in the saturation region, but otherwise minimized to achieve the best possible output swing. The lengths of transistors M6 / M7 and M10 / M11 are relatively large to achieve large small-signal output resistance from these devices. Transistors in the SOI process have relatively poor output resistance, so L (in ) must be quite large.

74

Figure 4-8 Schematic of the SOI version of the FDOA [46]. C1 C4 are compensation capacitors that set the bandwidth of the differential and CMFB loops. M12 M13 are source-follower output buffers that provide a low output impedance that helps to minimize charge injection from the chopper switches. Transistors M16 M23 and transistors M8 M9 form a two-stage amplifier that provide common-mode feedback. The common-mode level for vo2+ and vo2- is forced equal to CMREF, which is produced by the band-gap reference bias circuit. Low-frequency gain of the folded-cascode amplifier is about 58 dB. The unitygain frequency is about 21 MHz, and the phase margin at the unity-gain frequency is greater than 81. The low-frequency gain of the CMFB amplifier is about 70 dB. The unity-gain frequency is about 1 MHz. Phase margin at the unity-gain frequency is about 87. Large bandwidth is not required from this amplifier since the common-mode error is usually a

75

low-frequency signal, primarily DC. The low bandwidth insures stability. The schematic of the comparator amplifier is given in Fig 4-9. The comparator pre-amplifier uses transistors with regular threshold voltage because 1) comparison is a nonlinear function, so nonlinearity caused by poor output swing is not an issue; and 2) the transistors following the pre-amplifier are used in a switching mode in which static digital behavior is required.

Figure 4-9 Schematic of the SOI comparator [46]. This circuit is self-biased using a simple circuit that is relatively sensitive to the power supply. M13 M16 generate a 5 A current, and the gates of M13 and M16 are used to bias other devices. M1 and M2 are NMOS input transistors. M6 and M7 are current sources that serve as high-impedance load. The length of M6 / M7 is large for adequate voltage gain. When ResetB is high, the difference between Vin+ and Vin- is amplified at the drain of M6 / M7. In regeneration, M10 is turned on. Positive feedback

76

between M8 and M9 force the drain voltages of M6 / M7 to rail-to-rail very quickly. The DC gain of the pre-amplifier is about 42 dB. Unity gain frequency is about 12-MHz and phase margin at unity gain frequency is about 87 for a load capacitor equal to the input capacitance of the comparator. The stability in the reset phase is key since the circuit is open loop in the evaluation phase. SPICE simulations of the sigma-delta were run with a common-mode reference voltage of 1.7 V, and 1 V differential dc input voltage. In these simulations the effect of the chop signal was exaggerated using a period of just 4 clock cycles = 4 sec. The results of the simulation are shown in Fig 4-10. This figure shows the output of the switched-capacitor integrator in agreement with Eq 4-2, and Table 4-1 summarizes the expected increase and decrease at the output of the integrator each clock cycle for all combination of feedback (F) and Chop signal (C).

77

4.0V

Chopper Glitch
3.0V

Chop

2.0V

1.0V

-0.0V

Integrator Glitch
-1.0V

-2.0V 0s

2us 4us 6us V(X1.X3.X3:Vout+)-V(X1.X3.X3:Vout-)

8us V(X1.chop)

10us

12us Time

14us

16us

18us

20us

22us

24us

26us

Figure 4-10 Integrator output from the SOI sigma-delta modulator.

Table 4-1 Expected increase and decrease of the voltage at the output of the integrator with (VR+- VR-)=1.8 V and VIN=1 V.

F=1 C=0

F=1 C=1

F=0 C=0

F=0 C=0

-0.485 V -0.283 V 1.283 V 1.485 V

In summary, the following modifications have been made to the SOI sigma-delta design initiated in [46]:

78

1) the timing of the chop signal was corrected; 2) the bias circuit was modified to achieve 3.3 V operation; and 3) the Sigma-delta modulator has now been fabricated and tested.

5. Testing of the SOI transresistance amplifier and sigma-delta ADC 5.1 Testing of the transresistance amplifier

A block diagram of the test setup for the Rm amplifier is shown in Fig 5-1. In order to prevent coupling between circuit components inside the IC and the oscillator circuit, unused pins were tied to appropriate voltage levels, and a scope probe was connected to the output of the amplifier.
Gnd DVss 100 F 0.1 F DVdd Unused Digital I/O connected to DVdd/Gnd . . 100 F AVss 0.1 F

DIP package

AVdd 0.1 F Cap Oscin Oscout Scope probe

Figure 5-1 Block diagram of the test setup for the Rm amplifier. First, the input of the Rm amplifier was left floating and the bias levels produced by the bias generator were measured. Measurements agreed with simulation. Without applying any input, a strange signal was observed at the output periodic pulses with duration of 20 s as shown in Fig 5-2. The output is not a pure oscillation since the period is varying, and it consists of many frequency components, mostly less than 100 kHz.

80

Figure 5-2 Measured output voltage of the Rm amplifier with input floating. If the input pin is touched, which presumably adds capacitance, the output signal becomes a pure oscillation with a frequency of 28 kHz, as shown in Fig 5-3.

Figure 5-3 Measured output voltage of the Rm amplifier with input touched. To remove possible feedback loops which might exist in the PCB, the IC was removed from the PCB and placed on a non-conducting surface. All necessary bypass capacitors and instrument connections were clipped to package pins. This change did not

81

stop the oscillation. When Vdd was decreased, in addition to reduced amplitude at the output, the duty factor increased, i.e. the pulses became wider while the frequency stayed about the same. Several tests were performed using a 0.1 F ceramic high-frequency capacitor. This capacitor has a low impedance at the frequencies observed so can be used to break a feedback loop. First, the capacitor was connected from the output port to ground, Vss, and this stopped the output oscillation, as expected. Next it was connected from input to output. A periodic, binary oscillation at 2.9 kHz appeared at the output with pulse duration of 200 s as shown in Fig 5-4, indicating the effect of capacitive feedback.

Figure 5-4 Measured output voltage of the Rm amplifier with 0.1F capacitor connected between input and output. The capacitor was also connected from input to the ground in an attempt to attenuate feedback from output to input, and this time the output signal was aperodic with a peakto-peak value of VDD.

82

The feedback-bias loop inside the transresistance amplifier, which is used to bias the second stage, has a high voltage gain and can potentially oscillate. It uses a 0.1 F compensation capacitor connected off-chip to Vdd. In simulation, this loop was stable. To test this loop, feedback bias voltage was varied and the output bias level was observed to track feedback bias voltage, as it should. This suggested that the feedback bias loop was stable and working properly. During the preceding tests, the high-temperature setup shown in Fig 5-5, with heatresistant Teflon-coated wires connecting the instruments to the DIP pins, was used. To remove the possible coupling between these wires, they were removed and instruments were directly connected to the DIP pins. This created a significant change in the oscillation behavior. Instead of rectangular behavior, it became sinusoidal with a frequency of about 1 MHz that is shown in Fig 5-6. Apparently, the rectangular response of the Rm amplifier in the previous measurements was due to the coupling between the heat-resistant Teflon-coated wires.

Instruments Connector Tube

Hot Plate .. . . Thermal grease

Thermocouple

DIP

Figure 5-5 High-temperature test setup Since it was not possible to debug the circuit further with the existing I/O pins,

83

simulation was used to further examine the behavior. Several theories such as feedback through the power supply or ground, inductive follower behavior, etc, were studied to explain the oscillation, but a parasitic coupling capacitor through the packaging between input and output was identified as the most likely cause, as presented in the remaining of this section.

Figure 5-6 Measurement of the Rm output in DIP package with minimum parasitics. The block diagram of the Rm amplifier is shown in Fig 5-7. A parasitic capacitor was connected between input and output of the Rm amplifier. Cin and Cout are parasitic capacitances at the input and output of the Rm amplifier with the estimated values of 15 pF and 20 pF respectively. Cout is higher than Cin since a scope probe was connected to the output. Since Rin of the Rm amplifier is smaller than

1 at the observed oscillation Cin

84

frequency, most of the AC current through the coupling capacitor,

Vout , would flow 1 /(C c )

into the Rm amplifier. The loop gain can be estimated from Fig 5-7 by breaking the loop at the output and applying a sinusoidal voltage to Cc, and calculating the voltage return at the output. The loop gain is simply
Rm , and if greater than one, oscillation starts. The C c

tolerable value of Cc at 1 MHz is just 15 fF, since Rm is about 10 Meg in this design. This reasoning was verified by simulation. First, loop gain was simulated breaking the loop between the amplifiers as shown in Fig 5-7. Simulation was performed for 15 fF, 30 fF and 50 fF of capacitances, and as can be seen from Fig 5-8, all loop gains are above 0 dB at 0 of phase shift, and increasing with the increasing capacitance values. Simulation predicts that the frequency of 0 phase is about 400 kHz.

200 k Rin 2 k In
40 dB 40 dB

Out

Vac Cc Cin 15 pF Coupling Cap

Cout 20 pF

Figure 5-7 Block diagram of the transimpedance amplifier with parasitic feedback cap.

85

10 8d

0 d

SL> E> -0d 20 PVU.41/(1C12) ((1R:)VU.1:) 10 0

-0 10

-0 20 10z .H

1H 0z D((1R:)VU.1:) BVU.41/(1C12)

10z 0H

10H .Kz Feuny rqec

1Kz 0H

10H 0Kz

10H .Mz

1Mz 0H

Figure 5-8 AC simulation of the magnitude and phase response of the closed-loop system. As a final confirmation, a transient simulation test was performed and the resulting oscillation is shown in Fig 5-9. A 50 fF coupling capacitor was found to be the smallest

86

capacitor that started the oscillation in the transient simulation. The frequency of the oscillation is about 550 kHz, which is slightly lower than the actual measured oscillation frequency of about 1 MHz. The waveform shape and amplitude is quite similar to the measured result.
2.77V

2.40V

2.00V

1.60V

1.20V

0.88V 1.232ms 1.234ms V(U1:Vout) 1.236ms 1.238ms 1.240ms 1.242ms Time 1.244ms 1.246ms 1.248ms 1.250ms 1.252ms

Figure 5-9 Transient simulation of the Rm amplifier with 50 fF feedback. Having determined the cause of the oscillation, the next step was to search for the source of the coupling between input and output. To determine whether it is inside the IC itself, the bonding wire of the input node of the Rm amplifier was physically removed. The oscillation stopped indicating that the capacitance is outside the IC. The bias levels and the bias currents were measured and they all agreed with the expected levels. Thus,

87

it is concluded that the reason of the oscillation is the parasitic coupling due to packaging, and packaging will be improved in future work.
5.2 Testing of the Sigma-Delta Converter

Two types of tests, DC and AC, have been performed on the sigma-delta converter. Ground connections of the instruments were floated to remove possible loops through ground, and only one ground connection remained. Capacitors were added whenever necessary to filter out interference. More specifically, to remove 60-Hz and high frequency interference, 100 F and 0.1 F capacitors were connected from digital and analog Vdd to ground, respectively. There are also 0.1 F capacitors connected from the bias voltages to ground. The following instruments were used during these tests:

Agilent E3631A Power Supplies, SRS DS345 and Agilent 33250A Function Generators, Agilent 1673G Logic Analyzer, and HP 54615B Oscilloscope.

Since the output of the ADC is digital, a logic analyzer was used to collect the data. The output of the ADC is stable when the clock goes low, so the logic analyzer was set to state mode with trigger on the falling edge of the input master clock. In AC tests, 16384 binary data samples were collected for each measurement condition.
5.2.1 DC Tests

The differential reference voltage (VR+-VR-) generated in the bias circuit is about 1.8

88

V. The differential DC input voltage was swept from 1.8 V to +1.8 V. The differential sweep was performed with two power supplies set to tracking mode and the commonmode level was biased at 1.7 V using a third supply. In DC tests, 1000 samples were taken using the logic analyzer for each 0.2 V increment, and the number of ones were counted using Excel. As shown in Fig 5-10, linearity for DC inputs between -1.8 V to +1.8 V was very good except it is slightly off from the linear line at 1.8 V and 1.8 V since sigma-delta converter started to overload, and is quantified in the AC tests. The sampling frequency of 1 MHz was used during this test.
DC Trans fer Charac teris tic 1200 Data Linear fit 1000

800

600

400

200

-200

-1.8

-1.4

-1

-0.6 -0.2 0.2 0.6 Differential Input A m plitude (P )

1.4

1.8

Figure 5-10 Measured DC transfer characteristic of the sigma-delta modulator at room temperature.
5.2.2 AC Tests

A balanced differential AC input was used to test the sigma-delta converter. In order to create the balanced AC differential input, an audio transformer with center-tapped

89

secondary was used. A DC bias voltage equal to CMREF was applied to the center tap of the transformer in order to match the dc levels of the input signal and common-mode level of the sigma-delta converter. Nominal input amplitude is 3 Vp-p and nominal common-mode voltage is 1.7 V. A Fast-Fourier Transform was used to analyze the sampled data. Input frequency was selected so sampling times for one cycle did not correspond to the same points in any other cycle. In order to achieve this, the number of cycles, N, must not be divisible by the number of samples, 2m, where
NTsig = 2 m Tsamp .
Equation 5-1

Tsig and Tsamp are the periods of the input signal and the sampling respectively. In all AC tests, 2m is 16384, and fsamp is 1 MHz. The frequency of the input signal was approximately 3 kHz, the maximum frequency for which a 16 ksps sinc2() decimation filter is flat, but N was rounded to an odd integer, 47, so fsig was 2868.652344 Hz. The Agilent 33250A signal generator was used to generate the input, which accepts 10 digits, and the SRS DS345 signal generator was used to generate the clock. Since the signal generators are not ideal, the periods of the input signal and the sampling clock can vary slightly from ideal and can cause significant errors in the FFT. A Hanning windowing algorithm could be used to accurately calculate the signalto-noise ratio (SNR) when data does not represent an integral number of cycles. This algorithm slightly alters signal amplitude, but does a good job of isolating the primary signal peak. The windowing is done by multiplying the data by a raised cosine to

90

emphasize features near the center of the data set and minimize the effect of those located at the data set extremes. Hanning windowing is often useful in the analysis of real world signals where it is difficult to constrain the analysis to an integral number of cycles. In this work, however, a phase-locked loop (PLL) was used to solve the mismatch problem between the signal generators. The output of the SRS DS345 signal generator was connected to the input reference of the, Agilent 33250A, which has an internal PLL. The PLL locked to the input reference clock from the DS345, so the 33250A was able to provide a precise sinusoidal input. The output of the sigma-delta modulator was captured with the logic analyzer and this data was transferred to the PC through a LAN connection using FTP protocol. The FFT of the data was calculated using MATLAB and the single-sided magnitude response for nominal operating conditions and a full-scale input is given in Fig 5-11. Circles represent the noise components for the 8 kHz bandwidth corresponding to an OSR = 64 and the peak reaching up to 70 dB is the input signal at 3 kHz. The built-in dither corresponds to a square wave with frequency components at 16, 48, 80, . kHz. Harmonic distortion of the signal input is below the noise floor, so SDR is better than 70 dB. The interaction of chopping and dynamic element matching with the input signal does create artifacts at frequencies greater than the chopping frequencies, but these would be removed by the decimation low-pass filter.

91

80 70 60 50 Amplitude (dB) 40 30 20 10 0 -10 -20 2 4 6 8 Frequency (Hz) 10 12 14 x 10

4

Input Amplitude = 3 V Number of points = 16384

Figure 5-11 FFT of the sigma-delta modulator output bit stream for a sinusoidal input of 3 kHz. The 16 kHz dither is apparent. In the figures 5-12 to 5-17, except 5-13 which did not vary much under repeated tests, three measurements are performed sequentially at each x-axis setting. A bar is drawn between minimum and maximum levels and the average value is marked with a short horizontal bar. In the SNR plots, there is about 2.5 dB of uncertainty in the SNR calculated from the FFT of the bitstream. It is observed that the signal amplitude calculated by the FFT was very close to the applied input peak-to-peak value and did not very much during the three consecutive measurements, so noise is varying from measurement to measurement. Sigma-delta quantization noise is not white in reality and this could be the major contribution to the uncertainty. Also, data acquisition might have

92

an effect since every measurement starts from a different point on and there may be some inaccuracy in the period of the sine wave due to the decimal point limitation of the signal generator. One last possibility is the input signal not being pure. The measured SNR in Fig 5-12 is about 3 dB higher than predicted by theory. This might be partly due to the calibration error in the scope that is used to measure the amplitude of the input signal, but is mainly attributable to the approximations in sigmadelta theory. The performance of the modulator was tested at four separate clock frequencies: 250 kHz, 500 kHz, 1 MHz and 2 MHz, where 1 MHz is the nominal value. The input frequency and FFT bandwidth were scaled in each test to maintain an OSR of 64, so SNR is expected to be unchanged. As expected, the SNR increased in every doubling of the clock frequency, and the corresponding SNRs for four frequencies from low to high respectively are 53.2 dB, 54.6 dB, 52.46 dB, and 45.94 dB. The SNR at 2 MHz is 45.94 dB, much lower than the other SNRs which are very close to each other. We believe the reason is the unnecessary long non-overlapping clock delay.

93

60

55

50

SNR (dB) Average Value:(*)

45

40

35

30

25

20

15 -40

-35

-30

-25

-20 -15 Input Voltage (dBFS)

-10

-5

Figure 5-12 Measurement of SNR versus input amplitude. The IC will be powered from a battery, so there will be a certain drop in the battery voltage overtime. Therefore the performance of the modulator has also been tested against power supply variation. During these tests the DC level of the input signal was adjusted according to the change in CMREF generated in the bias circuit. As shown in Fig 5-13 and 5-14, the variation of reference voltage and FFT offset are acceptable over a wide range of supply voltage. In particular, the reference voltage increases with power supply voltage and then flattens. This is due to the cascoded transistors above the diode-resistor pair in bias circuit given in Fig 3-6. These transistors are on the edge of being in triode region, so an

94

increase in power supply voltage puts them in saturation region where the reference voltage becomes constant. So, the A/D converter performs better when the power supply voltage increases, as is evident from Fig 5-13. The variation in offset voltage shows a supply dependence below 3 V, but no clear trend above 3 V.
1 .7 1.6 8 1.6 6 1.6 4 Vref (V) 1.6 2 1 .6 1.5 8 1.5 6 1.5 4 2 .6

2 .8

3 .2 V dd (V )

3 .4

3. 6

3.8

Figure 5-13 Measured reference voltage versus power supply.

95

9.5

x 10

-3

8.5 Average Value:(*) Offset (V)

7.5

6.5

5.5

2.7

2.85

3.15 V dd (V )

3.3

3.45

3.6

3.75

Figure 5-14 Measured FFT offset voltage versus power supply. Variations of the SNR and signal amplitude with power supply voltage are shown in Figs 5-15 and 5-16. The measured amplitude derived by FFT is scaled to the applied input peak-to-peak value, and it is in close agreement with measurement. In the SNR measurements in Figs 5-15 and 5-17, the SNR uncertainty is high, as previously mentioned, but the average values show little variation.

96

58

57

Average Value:(*) SNR (dB)

56

55

54

53

52

2.7

2.85

3.15 V dd (V )

3.3

3.45

3.6

3.75

Figure 5-15 Measured SNR versus power supply voltage.

2.845

2.84 Average Value: (*) Signal Amplitude (V)

2.835

2.83

2.825

2.82

2.815

2.7

2.85

3.15 V dd (V )

3.3

3.45

3.6

3.75

Figure 5-16 Measured signal amplitude versus power supply voltage.

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58

57

Average Value:(*) SNR (dB)

56

55

54

53

52

51 1.2

1.3

1.4

1.5

1.6 1.7 Com m on Input V oltage (V )

1.8

1.9

2.1

Figure 5-17 Measured SNR versus common-mode input voltage under nominal conditions.
5.2.3 High-Temperature Testing

In the high-temperature test setup, heat-resistant teflon-coated wires are used to make connection to the IC. The IC is placed on a hot plate upside down, the dead-bug position, and secured with thermal grease. The connections from the wires to the IC pins are established through small tube-like connectors with both ends open. One end of the wires were inserted into the tube, and crimped, and the IC pins were inserted into the other end of the tube but not crimped to avoid possible damage to the pins. A K-type thermocouple was used to record the temperature. The thermocouple was affixed to the back of the ceramic DIP using thermal grease, and the voltage was measured with a handheld multimeter. The first step was to insure the reliability of the DIP package at high temperature.

98

Since the DIP package is ceramic it can withstand high temperatures, but the pad connections are potentially vulnerable. In order to test the quality of the pad connections at high temperature, and during temperature sweeps, Vdd and Vss were grounded, a 1V supply was connected to the IC pins through a 5 k resistance, and the voltage drop across the resistance was recorded. Since there is an Electrostatic Discharge (ESD) protection circuit for each pad inside the IC, and this circuit includes diodes between each pad and Vdd and Vss, the pad voltage is normally clamped to one diode drop. The temperature was swept up and down several cycles with no failure by the ESD diode, then sigma-delta tests were begun. Data was captured using the logic analyzer at seven temperatures (27 C 50 C, 100
C, 150 C, 200 C, 250 C and 300 C), and the SNR versus temperature plot is

presented in Fig 5-18. The SNR begins to drop at 50 C, stays close to 40 dB up to 250
C, decreases to 30 dB at 275 C and then drops drastically.
60

50

40

SNR (dB)

30

20

Input Frequency = 1 MHz Input Amplitude = 3 V

10

-1 0

50

100

150 Te m p e ra t u re ( C )

200

250

300

Figure 5-18 Measured SNR versus temperature.

99

5.2.4

Correcting the high-temperature simulation

SPICE simulation was used to analyze the SNR drop in the sigma-delta modulator at elevated temperatures. Since SPICE models are generally not accurate above 150 C, the mobility and threshold voltage were manually adjusted as described here. The test devices (Fig 5-19), including all six types of transistors, a resistor, and a diode, were tested using the semiconductor parameter analyzer (HP 4555B) at temperatures up to 300 C, and leakage, mobility and threshold voltage of the devices were extracted from the measurement as described in following section. These parameters were substituted into the SPICE model file to override values that would otherwise be calculated using the generic model. Testing of the NMOS transistors was straight forward since the ESD diodes do not turn on during the measurement, but testing the PMOS transistors was more complicated due to the ESD protection circuit. For PMOS transistors, 0 V was applied to Vdd and the source was also grounded. Vss was set to 3 V, and the drain voltage was swept from 0 V to 3 V to get VDS versus ID curves at different values of VGS between 0 V and 3 V. VGS versus ID curves were also plotted by sweeping VGS and keeping the drain potential at 3 V.

100

Figure 5-19 Circuit Schematic of the transistors, capacitors and resistor used for device characterization.
5.2.5 Extraction of the high-temperature parameters from the measurement

ID versus VGS and ID versus VDS curves from room temperature up to 300 C were measured. Leakage currents were analyzed from ID versus VDS curves, for VGS,SG = 0 V and VDS,SD = 3 V. The measured leakage current is fairly low at high temperature. As shown in Fig 5-20, the current is 5 A for the intrinsic NMOS transistor at 300 C for VGS=0, but this is strictly the leakage current since the threshold voltage of the NMOS transistor is negative at high temperature. However, a small kink effect was noticed in all devices at elevated temperature and an example Fig 5-20 is given.

101

2.5

x 10

-4

1.5

Id

0.5

-0.5

0.5

1.5 Vds

2.5

Figure 5-20 ID versus VDS at 300 C for intrinsic NMOS transistor with VGS varying between 0 V and 3 V and 0.5 V increments. VGS versus
I D curves were derived, and a linear fit was made with Matlab to the

linear portion of the curves over a range of 0.5 V near threshold voltage. From the intersection point of the VGS axis, the threshold voltage, and from the slope of the curve, the mobility were calculated using Eq 5-2. An example of this process is shown in Figs 5-21 and 5-22 for an NMOS intrinsic transistor at 200 C. To extract mobility, ( ) = 1 and Cox = 3.28 fF/(m)2 were used. L
Id = W C ox (VGS VT ) L 2
Equation 5-2

102

9 8 7 6 5 Id 4 3 2 1 0

x 10

-5

Intrinsic NMOS transistor VDS = 3-V

Parabolic region

0.2

0.4

0.6

0.8 Vgs

1.2

1.4

1.6

Figure 5-21 Measured Id versus Vgs at 200 C.

5 x 10
-3

4.5 data linear fit 4 sqrt(Id)

3.5

2.5

2 0.1

0.15

0.2

0.25

0.3

0.35 Vgs

0.4

0.45

0.5

0.55

0.6

Figure 5-22 Sqrt(Id) versus Vgs using data of Fig 5-17, including linear fit for VGS between 0.1 V and 0.6 V. Table 5-1 shows the results.

103

Table 5-1 Measured threshold variation with temperature.

Threshold Voltage 27C -0.161 0.158 0.448 -0.011 -0.264 -0.565 50C -0.200 0.120 0.442 -0.006 -0.239 -0.575 100C -0.250 0.090 0.426 0.028 -0.224 -0.556 150C -0.298 0.065 0.405 0.074 -0.186 -0.500 (V) 200C -0.340 0.023 0.351 0.153 -0.115 -0.393 250C -0.432 -0.043 0.239 0.235 -0.011 -0.273 300C -0.564 -0.161 0.041 0.407 0.173 -0.008 Device Type IN NL RN IP PL RP

Table 5-2 Measured mobility variation with temperature.

Mobility (cm2/v-sec) 27C 460.52 351.43 204.68 211.79 170.91 128.74 50C 342.24 265.03 164.52 140.18 128.74 97.35 100C 249.21 211.79 134.4 112.5 102.28 78.85 150C 197.68 177.42 107.33 92.54 83.29 62.3 200C 152.11 134.4 83.29 70.33 66.26 47.7 250C 117.79 107.33 66.26 58.47 51.17 41.13 300C 92.54 87.86 51.17 44.35 41.13 29.45

Device Type IN NL RN IP PL RP

104

After substituting the extracted threshold and mobility values given in Tables 5-1 and 5-2 into the model file, and replacing the 20-k resistor in the bias circuit with the measured values given in Table 5-3, a bias-point simulation was performed. The original diode model for the device used in the bias circuit was not accurate, so saturation currents of the diodes were decreased by one order of magnitude relative to the value provided by Peregrine, so the voltage drop across the diode in the simulation and the measurement were matched. As shown in Fig 5-23, with this change, all bias levels were very close.

Table 5-3 Measured values of the SN type resistor with varying temperature.
R (k) 27C 19.2 50C 19.2 100C 19.6 150C 20.8 200C 22.7 250C 24.4 300C 26.3

In order to insure the accuracy of the simulation, analog supply current was measured and compared against the modified simulator result. As a result, as can be seen from Fig 5-24, the supply current is in close agreement except at 300 C. At 300 C, the measured analog supply current is much higher than simulation. It was also observed at 300 C that while the temperature was help constant the current kept increasing, indicating a positive feedback effect. As done in all other high temperature tests, this test was performed three consecutive times, and no change in the measured current was

105

observed. Furthermore the performance of the chip at lower temperatures was unchanged. This suggested that there was no damage to the semiconductor. It could be that at this temperature, as suggested by the theory shown in Fig 1-2, the semiconductor is operating in the intrinsic region. Aside from this drastic increase in supply current near 300 C, the modified SPICE model correctly simulates the circuit behavior at elevated temperatures.
3.5

2.5

2 Volt

1.5

VDD = 3.3-V

0.5

27

50

100

150 200 Temperature C

250

300

Figure 5-23 Comparison of measured (solid line) and simulated (dash line) bias voltages at various temperatures:Vpbias (o), Vr+ (*), and Vr- (+).

106

1.8

1.6

1.4

IDD (A)

1.2

0.8

0.6

0.4

50

100

150 Temperature C

200

250

300

Figure 5-24 Total measured (solid line) and simulated (dash line) analog supply current.
5.2.6 Sigma-Delta simulation from 27 C to 300 C

The input and output of the OPAMP, as well as the output of the comparator inside the sigma-delta modulator are simulated at 27 C, 150 C, 200 C, 250 C and 300
C, and results at these five temperatures are shown in Figs 5-(25-29), respectively. The

input voltage is 1 V differential and the chop signal is set to a high frequency to better see its effects. The differential input-voltage of the OPAMP is expected to be close to zero. As shown in Fig. 5-21 the differential input-voltage, the voltage levels at the output of the integrator, and the comparator response are all in good agreement with expectation. But, as evident from Figs 5-(22-25) the performance of the OPAMP starts to degrade at 150
C. More specifically, the differential input-voltage increases with temperature

indicating reduced gain and/or settling speed in the OPAMP. In addition to the performance degradation in the OPAMP, the comparator output does not agree with the

107

OPAMP output at 300 C, i.e., the comparator is producing an opposite polarity output compared to the output of the integrator as shown in Fig 5-25, which results in the ADC failure. Also, notice there is substantial error in the differential output following a Chop transition for temperatures of 150 C and above. This is caused by slower clock edges and a design oversight. Also the Chop switches around the integration capacitors do not have non-overlapping clocks. It is well known that sigma-delta ADCs are very robust. Although the OPAMP gain dropped remarkably, the SNR decreased by just 10 dB. The SNR remained above 40 dB up to 250 C and remained above 30 dB up to 275 C, but after that, it degraded drastically. Further analysis showed that the self-biasing circuits inside the OPAMP and the comparator were failing at elevated temperatures, and this caused some transistors to go into the triode mode, which results in gain loss, and performance degradation. Another cause of the performance degradation and failure was due to the current mirrors. The current mirror concept works providing two transistors share the same VGS,SG, and if they are both in the saturation regime, ignoring channel length modulation. Saturation regime is normally guaranteed by the diode connection, but at elevated temperatures the threshold voltage drops and the transistor becomes depletion-mode. In this design, intrinsic devices with 0 V threshold were used to achieve high voltage swing, and their threshold voltages, as given in Table 5-1 were very much negative. Thus, since VD is greater than VT due to the negative VT, the diode connection does not

108

guarantee saturation-mode operation at elevated temperatures, and low-threshold transistors should not be used as current mirrors in high-temperature designs.

C o m p . O u t

40 .V

0 V

SL> E> -.V 40 VX.3X:ot,1X.2Vu(1X.2Vu+X.3X:ot) O p a m p I n 40 .V

Vin+
0 V

Vin-

differential input
-.V 40 VX.3X.2Vn)VX.3X.2vn) VX.3X.2Vn) VX.3X.2vn) (1X.3X:i+-(1X.3X:i- (1X.3X:i+ (1X.3X:iO p a m p O u t 40 .V

Vout-

Vout+

0 V

chop differential output

-.V 40 0 s 1s u 2s u 3s u 4s u 5s u 6s u VX.3X:ot) VX.3X:ot) VX.hp VX.3X:ot)VX.3X:ot) (1X.3Vu- (1X.3Vu+ (1co) (1X.3Vu+-(1X.3VuTm ie

7s u

8s u

9s u

1u 0s

Figure 5-25 Simulated OPAMP and comparator I/O at 27 C.

109

C o m p . O u t

40 .V

0 V

SL> E> -.V 40 VX.3X:ot,1X.2Vu(1X.2Vu+X.3X:ot) O p a m p I n 20 .V

Vin+
0 V

Vin-

differential input
-.V 20 VX.3X.2Vn)VX.3X.2vn) VX.3X.2Vn) VX.3X.2vn) (1X.3X:i+-(1X.3X:i- (1X.3X:i+ (1X.3X:iO p a m p O u t 40 .V

Vout-

Vout+

0 V

chop differential output

-.V 40 0 s 1s u 2s u 3s u 4s u 5s u 6s u VX.3X:ot) VX.3X:ot) VX.hp VX.3X:ot)VX.3X:ot) (1X.3Vu- (1X.3Vu+ (1co) (1X.3Vu+-(1X.3VuTm ie

7s u

8s u

9s u

1u 0s

Figure 5-26 Simulated OPAMP and comparator I/O at 150 C.

110

C o m p . O u t

40 .V

0 V

SL> E> -.V 40 VX.3X:ot,1X.2Vu(1X.2Vu+X.3X:ot) O p a m p I n 20 .V

Vin+
0 V

Vin-

-.V 20 O p a m p O u t 40 .V

differential input
VX.3X.2Vn)VX.3X.2vn) VX.3X.2Vn) VX.3X.2vn) (1X.3X:i+-(1X.3X:i- (1X.3X:i+ (1X.3X:i-

Vout-

Vout+

0 V

chop differential output

-.V 40 0 s 1s u 2s u 3s u 4s u 5s u 6s u VX.3X:ot) VX.3X:ot) VX.hp VX.3X:ot)VX.3X:ot) (1X.3Vu- (1X.3Vu+ (1co) (1X.3Vu+-(1X.3VuTm ie

7s u

8s u

9s u

1u 0s

Figure 5-27 Simulated OPAMP and comparator I/O at 200 C.

111

C o m p . O u t

40 .V

0 V

SL> E> -.V 40 VX.3X:ot,1X.2Vu(1X.2Vu+X.3X:ot) O p a m p I n 20 .V

Vin+
0 V

Vin-

differential input
-.V 20 VX.3X.2Vn)VX.3X.2vn) VX.3X.2Vn) VX.3X.2vn) (1X.3X:i+-(1X.3X:i- (1X.3X:i+ (1X.3X:iO p a m p O u t 40 .V

Vout-

Vout+

0 V

chop differential output

-.V 40 0 s 1s u 2s u 3s u 4s u 5s u 6s u VX.3X:ot) VX.3X:ot) VX.hp VX.3X:ot)VX.3X:ot) (1X.3Vu- (1X.3Vu+ (1co) (1X.3Vu+-(1X.3VuTm ie

7s u

8s u

9s u

1u 0s

Figure 5-28 Simulated OPAMP and comparator I/O at 250 C.

112

C o m p . O u t

40 .V

0 V

SL> E> -.V 40 VX.3X:ot,1X.2Vu(1X.2Vu+X.3X:ot) O p a m p I n 40 .V

0 V

Vin-

Vin+ differential input

-.V 40 VX.3X.2Vn)VX.3X.2vn) VX.3X.2Vn) VX.3X.2vn) (1X.3X:i+-(1X.3X:i- (1X.3X:i+ (1X.3X:iO p a m p O u t 40 .V

Voutchop differential output

Vout+

0 V

-.V 40 0 s 1s u 2s u 3s u 4s u 5s u 6s u VX.3X:ot) VX.3X:ot) VX.hp VX.3X:ot)VX.3X:ot) (1X.3Vu- (1X.3Vu+ (1co) (1X.3Vu+-(1X.3VuTm ie

7s u

8s u

9s u

1u 0s

Figure 5-29 Simulated OPAMP and comparator I/O at 300 C.

6. Conclusion 6.1 Achievements

In this work, oscillator topologies for MEMS-based resonators with very high series resistance have been analyzed and the transresistance topology is identified as the best candidate. Discrete and IC versions of a transresistance amplifier having potential for sensor interfacing, for characterization of MEMS resonators, and as the basis of an oscillator, have been designed for high-temperature operation. Due to the difficulty in finding reliable discrete parts at temperatures > 200 C, and possible high parasitic capacitance, a discrete version of the design has not been implemented. Instead, an IC version has been fabricated using SOI technology. Although the transresistance amplifier and the oscillator functioned in simulation, the actual amplifier did not work, but oscillated due to the packaging parasitic coupling between input and output of the Rm amplifier. Although the transresistance amplifier test was not successful, MEMS-based oscillator topologies and the importance of packaging parasitics is now much better understood. An SOI 1st- order, fully-differential, switched-capacitor sigma-delta analog-to-digital converter with dither, chopping, and dynamic element matching has been developed, evaluated, and exhibits state-of-the-art performance. The A/D converter achieved the theoretical maximum 50 dB SNR at room temperature, which dropped to 40 dB at 250 C and 30 dB at 275 C. Easily correctable design oversights, including excessive nonoverlap time in the clock generator, depletion-mode transistors in current mirrors, and non-overlapping chop signals, have been identified.

114

6.2 Future Work

Most of the goals have been reached, but there is inspiration for future work. As concluded in Chapter 2 (2.4), the integration of the resonator is required to achieve lowpower oscillation. The integration can also help to stop the oscillation in the Rm amplifier. In future test of the Rm amplifier above, an unpackaged IC will be used to reduce the possible coupling between input and output. A number of small, but important, design flaws were discovered in the sigma-delta design, and these problems and the solutions are summarized here. Despite these flaws, the sigma-delta achieved the goal of 8-bit resolution, but resolution at higher OSR and operating temperature were limited. The non-overlapping clock delay between Phase1 and Phase2 was unnecessarily long,
100 nsec, which limits the maximum speed of the ADC clock. This can be easily

corrected and should be set to 5 nsec. The chop signal should have been non-overlapping, not simply complementary. Also, limiting of the integration Chop should be cycle later than sampling Chop to avoid unnecessary glitches at the output of the integrator. Without non-overlapping Chop, charge losses are observed in the feedback capacitors at elevated temperatures. Due to the decrease in threshold voltages that drive the devices to depletion mode, diode-connected transistors used in the current-mirror biasing is not reliable, so regularthreshold devices should be used. Also, a ZTC biasing scheme should be used to maintain saturated operation across a wide temperature range.

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