Ds 095

0
XC2C384 CoolRunner-II CPLD

0 0
DS095 (v1.1) August 20, 2002
Advance Product Specification
Features
Optimized for 1.8V systems - As fast as 6.0 ns pin-to-pin delays - As low as 27 A quiescent current Industrys best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis - Multi-voltage I/O operation 1.5V to 3.3V Available in multiple package options - 144-pin TQFP with 118 user I/O - 208-pin PQFP with 173 user I/O - 256-ball FT (1.0mm) BGA with 212 user I/O - 324-ball FG (1.2mm) BGA with 240 user I/O Advanced system features - Fastest in system programming 1.8V ISP using IEEE 1532 (JTAG) interface - IEEE1149.1 JTAG Boundary Scan Test - Optional Schmitt-trigger input (per pin) - Unsurpassed low power management - Four seperate output banks - Fast Zero Power (FZP) 100% CMOS product term generation - DataGATE enable (DGE) signal control - Flexible clocking modes Optional DualEDGE triggered registers Clock divider (divide by 2,4,6,8,10,12,14,16) CoolCLOCK - Global signal options with macrocell control Multiple global clocks with phase selection per macrocell Multiple global output enables Global set/reset - Advanced design security - Open-drain output option for Wired-OR and LED drive - Optional bus-hold, 3-state or weak pullup on selected I/O pins - Optional configurable grounds on unused I/Os - Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility - Hot pluggable
Description
The CoolRunner-II 384-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved This device consists of twenty four Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as direct input registers to store signals directly from input pins. Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchonous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis. A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the device. Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections. This yields divide by even and odd clock frequencies. The use of the clock divide (division by 2) and DualEDGE flip-flop gives the resultant CoolCLOCK feature. DataGATE is a method to selectively disable inputs of the CPLD that are not of interest during certain points in time.
Refer to the CoolRunner-II family data sheet for architecture description.
2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS095 (v1.1) August 20, 2002 Advance Product Specification
www.xilinx.com 1-800-255-7778
XC2C384 CoolRunner-II CPLD By mapping a signal to the DataGATE function, lower power can be achieved due to reduction in signal switching. Another feature that eases voltage translation is output banking. Four output banks are available on the CoolRunner-II 384 macrocell device that permits easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V devices. The CoolRunner-II 384 macrocell CPLD is I/O compatible with various I/O standards (see Table 1). This device is also 1.5V I/O compatible with the use of Schmitt-trigger inputs.
Supported I/O Standards

The CoolRunner-II 384 macrocell features LVCMOS, LVTTL, SSTL and HSTL I/O implementations. See Table 1 for I/O standard voltages. The LVTTL I/O standard is a general purpose EIA/JEDEC standard for 3.3V applications that use an LVTTL input buffer and Push-Pull output buffer. The LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications. Both HSTL and SSTL I/O standards make use of a VREF pin for JEDEC compliance. CoolRunner-II CPLDs are also 1.5V I/O compatible with the use of Schmitt-trigger inputs. Table 1: I/O Standards for XC2C384 Output VCCIO 3.3 3.3 2.5 1.8 1.5 1.5 2.5 3.3 Input VCCIO 3.3 3.3 2.5 1.8 1.5 1.5 2.5 3.3 Board Input Termination VREF Voltage VTT N/A N/A N/A N/A N/A 0.75 1.25 1.5 N/A N/A N/A N/A N/A 0.75 1.25 1.5
Fast Zero Power Design Technology

Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron process technology which is derived from leading edge FPGA product development. CoolRunner-II CPLDs employ Fast Zero Power (FZP), a design technique that makes use of CMOS technology in both the fabrication and design methodology. FZP design technology employs a cascade of CMOS gates to implement sum of products instead of traditional sense amplifier methodology. Due to this technology, Xilinx CoolRunner-II CPLDs achieve both high-performance and low power operation.
I/O Types LVTTL LVCMOS33 LVCMOS25 LVCMOS18 1.5V I/O HSTL-1 SSTL2-1 SSTL3-1
20
15
ICC (mA)
10
0 0 25 50 75 100 125 150 175 200 225

DS095_01_053102
Frequency (MHz)
Figure 1: ICC vs Frequency Table 2: ICC vs Frequency (LVCMOS 1.8V TA = 25C)(1) Frequency (MHz) 0 Typical -7, -10 ICC (mA) Typical -6 ICC (mA)
Notes: 1. 16-bit up/down, resettable binary counter (one counter per function block).
25
50
75
100
125
150
175
200
225
Absolute Maximum Ratings

Symbol VCC VCCIO VJTAG VAUX VIN VTS TSTG TSOL TJ Description Supply voltage relative to ground Supply voltage for output drivers JTAG input voltage limits JTAG input supply voltage Input voltage relative to ground(1) Voltage applied to 3-state output(1) Value 0.5 to 2.0 0.5 to 4.0 -0.5 to 4.0 -0.5 to 4.0 0.5 to 4.0 0.5 to 4.0 65 to +150 + 260 + 150 Units V V V V V V C C C
Storage Temperature (ambient) Maximum Soldering temperature (10s @ 1/16in. = 1.5mm) Junction Temperature
Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions, the device pins may undershoot to 2.0v or overshoot to +4.5V, provided this over or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA.
Recommended Operating Conditions

Symbol VCC VCCIO Parameter Supply voltage for internal logic and input buffers Commercial TA = 0C to +70C Industrial TA = 40C to +85C Min 1.7 1.7 3.0 2.3 1.7 1.4 1.7 Max 1.9 1.9 3.6 2.7 1.9 1.6 3.6 Units V V V V V V V
Supply voltage for output drivers @ 3.3V operation Supply voltage for output drivers @ 2.5V operation Supply voltage for output drivers @ 1.8V operation Supply voltage for output drivers @ 1.5V operation
VAUX
JTAG programming
DC Electrical Characteristics (Over Recommended Operating Conditions)

Symbol ICCSB ICCSB ICC (1) ICC (1) CJTAG CCLK CIO
Notes: 16-bit up/down, resettable binary counter (one counter per function block).
Parameter Standby current (-7, -10) Standby current (-6) Dynamic current (-7, -10) Dynamic current (-6) JTAG input capacitance Global clock input capacitance I/O capacitance
Test Conditions VCC = 1.9V, VCCIO = 3.6V VCC = 1.9V, VCCIO = 3.6V f = 1 MHz f = 50 MHz f = 1 MHz f = 50 MHz f = 1 MHz f = 1 MHz f = 1 MHz
Min. -
Max. 100
Units A mA mA mA mA mA
10 12 10
pF pF pF
LVCMOS and LVTTL 3.3V DC Voltage Specifications

Symbol VCCIO VIH VIL VOH VOL IIL IIH Parameter Input source voltage High level input voltage Low level input voltage High level output voltage IOH = 8 mA, VCCIO = 3V IOH = 0.1 mA, VCCIO = 3V Low level output voltage IOL = 8 mA, VCCIO = 3V IOL = 0.1 mA, VCCIO = 3V Input leakage current I/O High-Z leakage VIN = 0V or VCCIO to 3.9V VIN = 0V or VCCIO to 3.9V Test Conditions Min. 3.0 2 0.3 VCCIO 0.4V VCCIO 0.2V 10 10 Max. 3.6 3.9 0.8 0.4 0.2 10 10 Units V V V V V V V A A
LVCMOS 2.5V DC Voltage Specifications

Symbol VCCIO VIH VIL VOH VOL IIL IIH Parameter Input source voltage High level input voltage Low level input voltage High level output voltage IOH = 8 mA, VCCIO = 2.3V IOH = 0.1 mA, VCCIO = 2.3V Low level output voltage IOL = 8 mA, VCCIO = 2.3V IOL = 0.1mA, VCCIO = 2.3V Input leakage current I/O High-Z leakage VIN = 0V or VCCIO to 3.9V VIN = 0V or VCCIO to 3.9V Test Conditions Min. 2.3 1.7 0.3 VCCIO 0.4V VCCIO 0.2V 10 10 Max. 2.7 3.9 0.7 0.4 0.2 10 10 Units V V V V V V V A A
LVCMOS 1.8V DC Voltage Specifications

Symbol VCCIO VIH VIL VOH VOL IIL IIH Parameter Input source voltage High level input voltage Low level input voltage High level output voltage IOH = 8 mA, VCCIO = 1.7V IOH = 0.1 mA, VCCIO = 1.7V Low level output voltage IOL = 8 mA, VCCIO = 1.7V IOL = 0.1 mA, VCCIO = 1.7V Input leakage current I/O High-Z leakage VIN = 0 or VCCIO to 3.9V VIN = 0 or VCCIO to 3.9V Test Conditions Min. 1.7 0.65 x VCCIO 0.3 VCCIO -0.45 VCCIO -0.2 10 10 Max. 1.9 3.9 0.35 x VCCIO 0.45 0.2 10 10 Units V V V V V V V A A
1.5V DC Voltage Specifications(1)

Symbol VCCIO VT+ VTVOH VOL IIL IIH High level output voltage IOH = 8 mA, VCCIO = 1.4V IOH = 0.1 mA, VCCIO = 1.4V Low level output voltage IOL = 8 mA, VCCIO = 1.4V IOL = 0.1 mA, VCCIO = 1.4V Input leakage current I/O High-Z leakage VIN = 0 or VCCIO to 3.9V VIN = 0 or VCCIO to 3.9V Parameter Input source voltage Input hysteresis threshold voltage Test Conditions Min. 1.4 0.5 x VCCIO 0.2 x VCCIO VCCIO 0.45 VCCIO 0.2 10 10 Max. 1.6 0.8 x VCCIO 0.5 x VCCIO 0.4 0.2 10 10 Units V V V V V V V A A
Notes: 1. Hysteresis used on 1.5V inputs.
SSTL2-1 DC Voltage Specifications

Symbol VCCIO VREF(1) VTT(2) VIH VIL VOH VOL IIL IIH Parameter Input source voltage Input reference voltage Termination voltage High level input voltage Low level input voltage High level output voltage Low level output voltage Input leakage current I/O High-Z leakage IOH = 8 mA, VCCIO = 2.3V IOL = 8 mA, VCCIO = 2.3V VIN = 0V or VCCIO to 3.9V VIN = 0V or VCCIO to 3.9V Test Conditions Min. 2.3 1.15 VREF -0.04 VREF +0.18 0.3 VCCIO -0.62 10 10 Typ 2.5 1.25 1.25 Max. 2.7 1.35 VREF +0.04 3.9 VREF -0.18 0.54 10 10 Units V V V V V V V A A
Notes: 1. VREF should track the variations in VCCIO, also peak to peak ac noise win VREF may not exceed +/- 2% VREF 2. VTT of transmitting device must track VREF of receiving devices
SSTL3-1 DC Voltage Specifications

Symbol VCCIO VREF(1) VTT(2) VIH VIL VOH VOL IIL IIH Parameter Input source voltage Input reference voltage Termination voltage High level input voltage Low level input voltage High level output voltage Low level output voltage Input leakage current I/O High-Z leakage IOH = 8 mA, VCCIO = 3V IOL = 8 mA, VCCIO = 3V VIN = 0V or VCCIO to 3.9V VIN = 0V or VCCIO to 3.9V Test Conditions Min. 3.0 1.3 VREF -0.05 VREF +0.2 0.3 VCCIO -1.1 10 10 Typ 3.3 1.5 1.5 Max. 3.6 1.7 VREF +0.05 VCCIO + 0.3 VREF -0.2 0.7 10 10 Units V V V V V V V A A
HSTL1 DC Voltage Specifications

Symbol VCCIO VREF(1) VTT(2) VIH VIL VOH Parameter Input source voltage Input reference voltage Termination voltage High level input voltage Low level input voltage High level output voltage IOH = 8 mA, VCCIO = 1.7V Test Conditions Min. 1.4 0.68 VREF +0.1 0.3 VCCIO -0.4 Typ 1.5 0.75 VCCIO*0.5 Max. 1.6 0.90 1.9 VREF -0.1 Units V V V V V V
Symbol VOL IIL IIH
Parameter Low level output voltage Input leakage current I/O High-Z leakage
Test Conditions IOL = 8 mA, VCCIO = 1.7V VIN = 0 or VCCIO to 3.9V VIN = 0 or VCCIO to 3.9V
Min. 10 10
Typ -
Max. 0.4 10 10
Units V A A
AC Electrical Characteristics Over Recommended Operating Conditions

-6 Symbol TPD1 TPD2 TSUF TSU1 TSU2 THF TH TCO FTOGGLE FSYSTEM1 FSYSTEM2 FEXT1 FEXT2 TPSUF TPSU1 TPSU2 TPHF TPH TPCO TOE/TOD TPOE/TPOD TMOE/TMOD TPAO TAO TSUEC THEC TCW TPCW TDGSU TDGHO TDGR TDGW TCDRSU Parameter Propagation delay single p-term Propagation delay OR array Fast input register set-up time Setup time fast (single p-term) Setup time (OR array) Fast input register hold time Hold time (OR array or p-term) Clock to output Internal toggle rate(1) frequency(2) Maximum system Min. 2.2 2.3 2.6 0 0 1.0 1.1 1.4 0.5 0.4 2.4 0 1.2 6.0 7.0 7.0 7.0 2.5 1.2 3.0 1.7 Max. 5.7 6.0 4.4 416 217 204 149 143 5.6 5.5 6.5 7.1 7.4 7.2 Min. 2.4 2.6 3.0 0 0 1.1 1.3 1.7 0.9 0.7 2.7 0 2.0 7.5 9.0 9.0 9.0 5.0 2.5 -7 Max. 7.1 7.5 5.8 250 179 167 119 114 7.1 7.0 8.0 9.1 8.9 9.0 Min. 2.7 3.1 3.9 0 0 1.3 1.7 2.5 1.3 0.9 3.2 0 3.0 10.0 10.0 10.0 11.0 -10 Max. 9.2 10.0 7.9 166 128 116 91 85 9.3 9.2 10.2 12.5 11.6 11.5 Units ns ns ns ns ns ns ns ns MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Maximum system frequency(2) Maximum external frequency(3) Maximum external frequency(3) Fast input register p-term clock setup time P-term clock setup time (single p-term) P-term clock setup time (OR array) Fast input register p-term clock hold time P-term clock hold P-term clock to output Global OE to output enable/disable P-term OE to output enable/disable Macrocell driven OE to output enable/disable P-term set/reset to output valid Global set/reset to output valid Register clock enable setup time Register clock enable hold time Global clock pulse width High or Low P-term pulse width High or Low Set-up before DataGATE latch assertion Hold to DataGATE latch assertion DataGATE recovery to new data DataGATE high pulse width CDRST setup time before falling edge GCLK2
-6 Symbol TCDRHO TCONFIG Parameter Hold time CDRST after falling edge GCLK2 Configuration time Min. 0.0 Max. Min. 0.0
-7 Max. Min. 0.0
-10 Max. Units ns us
Notes: 1. FTOGGLE (1/2*TCW) is the maximum frequency of a T flip-flop with output enabled 2. FSYSTEM1 (1/TCYCLE) is the internal operating frequency for a device with 16-bit resettable binary counter through one p-term per macrocell while FSYSTEM2 is through the OR array (one counter per function block) 3. FEXT1(1/TSU1+TCO) is the maximum external frequency using one p-term while FEXT2 is through the OR array
Internal Timing Parameters

-6 Symbol
Buffer Delays
-7 Max. 2.5 2.8 1.8 2.8 2.0 2.4 3.5 0.5 0.4 0.3 0.4 0.2 2.0 0 2.8 1.6 2.0 0.5 2.0 0 2.0 0 2.0 Min. 1.4 0 1.4 0 Max. 3.1 3.4 2.4 3.8 2.7 3.0 4.3 0.6 0.5 0.4 0.5 0.4 2.2 0 3.3 2.0 3.0 0.8 3.0 0 3.0 0 3.0 Min. 1.8 0 1.8 0 -
-10 Max. 3.8 4.2 3.3 4.6 3.7 3.9 5.5 0.9 0.8 0.8 0.7 0.7 3.0 0 4.5 3.0 4.0 1.0 4.0 0 4.0 0 4.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Parameter(1) Input buffer delay Fast data register input delay Global Clock buffer delay Global set/reset buffer delay Global 3-state buffer delay Output buffer delay Output buffer enable/disable delay Control term delay Single P-term delay adder Multiple P-term delay adder Input to output valid Setup before clock Hold after clock Enable clock setup time Enable clock hold time Clock to output valid Set/reset to output valid Clock doubler delay Feedback delay Macrocell to global OE delay Hysteresis input adder Output adder Output slew rate adder Standard input adder Hysteresis input adder Output adder Output slew rate adder
Min. 1.2 0 1.2 0 -
TIN TFIN TGCK TGSR TGTS TOUT TEN

P-term Delays
TCT TLOGI1 TLOGI2 TPDI TSUI THI TECSU TECHO TCOI TAOI TCDBL TF TOEM THYS15 TOUT15 TSLEW15 TIN18 THYS18 TOUT18 TSLEW
Macrocell Delay
Feedback Delays
I/O Standard Time Adder Delays 1.5V CMOS
10
Internal Timing Parameters (Continued)

-6 Symbol TIN25 THYS25 TOUT25 TSLEW25 TIN33 THYS33 TOUT33 TSLEW33 SSTL2-1 Parameter(1) Standard input adder Hysteresis input adder Output adder Output slew rate adder Standard input adder Hysteresis input adder Output adder Output slew rate adder Input adder to TIN, TFIN, TGCK, TGSR,TGTS Output adder to TOUT SSTL3-1 Input adder to TIN, TFIN, TGCK, TGSR,TGTS Output adder to TOUT HSTL-1 Input adder to TIN, TFIN, TGCK, TGSR,TGTS Output adder to TOUT
Notes: 1. 1.5 ns input pin signal rise/fall.
-7 Max. 0.5 1.5 1.5 2.0 0.7 1.0 1.0 2.0 1.5 0 1.5 0 1.5 0 Min. -
-10 Max. 0.8 2.5 2.5 3.0 1.0 2.0 2.0 3.0 1.8 0 1.8 0 1.8 0 Min. -
Min. -
Max. 1.0 3.0 3.0 4.0 2.0 3.0 3.0 4.0 2.5 0 2.5 0 2.5 0
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns
I/O Standard Time Adder Delays 3.3V CMOS/TTL
I/O Standard Time Adder Delays HSTL, SSTL
Switching Characteristics
VCC = 1.8V, 25oC
6.0
Switching Test Conditions
5.8
TPD_PAL (ns)
5.6
4.4
4.2
4.0 1 2 4 8 12 16
Number of Outputs Switching

DS095_09_053102
11

11
Pin Descriptions
Function Block Macrocell TQ144 PQ208 FT256 FG324 I/O Bank
Pin Descriptions (Continued)

1 1 1(GSR) 1 1 1 1 1 1 1 1 1 1 1 1 1 2(GTS2) 2 2(GTS3) 2 2(GTS0) 2 2 2 2 2 2 2 2 2 2(GTS1) 2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
143 142 140 139 2 3 4 5 6 7
2 208 206 205 203 202 201 200 199 3 4 5 6 7 8 9 10
B3 B4 C4 A2 C5 A3 E7 D3 C3 E3 B2 D4 A1 D2 C2 E5 B1
C3 A1 A2 B3 C4 B4 C5 B5 A3 A4 D3 B2 B1 C2 C1 D2 F4 E2 E1 F2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
138 137 136 135 134 9 10 11 12 -
198 197 196 195 194 193 192 191 12 14 15 16 17 18 19 20 21
A4 C6 B5 D6 A5 E8 B6 C7 A6 E4 C1 E2 F2 E6 F3 D1 G4 E1 G3
D6 A5 C6 B6 A6 D7 C7 B7 A7 D8 G4 G3 G2 G1 H4 H3 H2 H1 J3 J2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
12


5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
133 132 131 130 129 13 14 15 16 17 18
189 188 187 186 185 184 183 22 23 25
D7 B7 E9 A7 D8 B8 C8 A8 E11 E10 G2 F5 F1 K1 H2 H4 G1 H3 H1 H5
C8 B8 A8 D9 C9 B9 A9 D10 C10 B10 J1 K3 K2 K1 L1 L3 L2 M1 M2 M3
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
7(CDRST) 7 7 7 7 7 7 7 7 7 7 7(GCK1) 7 7 7(GCK0) 7 8 8(GCK2) 8 8 8(DGE) 8 8 8 8 8 8 8 8 8 8 8
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
35 34 33 32 31 30 38 39 40 41 42 43
51 50 49 48 47 46 45 44 43 54 55 56 57 58 60 61 -
P2 N3 R1 N4 N2 M3 P1 M4 M2 L3 P4 P5 R2 T1 T2 N5 R4 M5
AB2 AA2 AA1 W4 Y2 Y1 W2 W1 V3 U4 Y4 AB3 AA4 Y5 AA5 AB4 W6 AB5 Y6 AA6
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
13


9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
28 -26 25 44 45 46 48 49 50
41 40 39 38 37 36 35 34 32 62 63 64 65 66 67 69 70 71
N1 L4 M1 L5 K4 L2 K3 L1 R5 R6 N6 R3 M6 T3 P6
V2 V1 U3 U2 U1 T4 T3 T2 T1 R4 AB6 W7 Y7 AA7 AB7 W8 Y8 AA8 AB8 Y9
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
24 23 22 21 20 19 51 52 53 54 -
31 30 29 28 27 72 73 74 75 76 77 78
K5 K2 J4 K1 J3 J2 J5 J1 T4 P7 T5 N7 R7 M7 T6
R3 R2 R1 P4 P3 P2 P1 N3 N2 N1 AA9 AB9 W10 Y10 AA10 AB10 AB11 W11 AA11 Y11
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
14


13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
112 113 114 115 111 110 107 106 105 104 -
160 161 162 163 164 159 158 155 154 153 152 151 150
B16 G11 C14 B15 A16 B13 B14 C13 A15 C12 D14 C15 G12 D15 E14 C16 F14 D16 F13 E15
C21 C20 B22 B21 A22 A21 B20 C19 B19 C18 D19 D20 C22 D21 D22 E20 F19 E21 E22 F20
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
116 117 118 119 120 103 102 101 100
165 166 167 168 169 170 171 149 148 147 146 145 144 143
B12 D13 A14 E13 A13 C11 A12 B11 D11 A11 G13 F15 G14 E16 H12 F16 H16 -
B18 A19 D17 A18 C17 B17 D16 C16 B16 D15 F21 F22 G19 G20 G21 G22 H19 H21 H22 J19
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
15


17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
121 124 125 126 128 98 97 96 95 94 -
173 174 175 178 179 180 182 142 140 139 138 137 136 135 134 -
D10 B10 E12 F12 B9 C9 C10 A9 D9 G15 H13 G16 H14 H15 J12 K12 J16
C15 B15 D14 B14 C13 A13 D12 C12 B11 A10 J20 J21 J22 K19 K20 K21 K22 L19 L20 L21
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
74 75 76 77 78 79 71 70 69 68 66 64 -
103 106 107 108 109 110 111 112 113 102 101 100 99 97 95 -
P13 P14 P15 R15 T16 N14 R16 N15 M15 M13 R13 N13 R14 T15 R12 T14 N11 P11 M11 T13
AA22 Y20 Y21 W20 W21 Y22 W22 V20 V21 U19 AB22 AA21 AB21 W19 AA20 Y18 AA19 Y17 AA18 AB18
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
16


21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
80 81 82 83 61 60 59 -
114 115 116 117 118 119 120 121 122 123 91 90 89 88 87 86 85 -
P16 N16 L14 M14 L15 L13 M12 M16 K14 N10 T12 P10 T11 R10 M10 T10 M9 R9 P9
V22 U20 U21 U22 T19 T20 T21 T22 R21 R22 AA17 AB17 Y16 AA16 AB16 W15 Y15 AA15 AB15 W14
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
85 86 87 88 91 92 58 57 56 -
125 126 127 128 131 84 83 82 80 -
L16 K15 L12 K16 J14 J15 J13 N9 T9 M8 T8 P8 R8 T7 N8
P20 P21 N19 N21 N22 M22 M19 M20 M21 L22 Y14 AA14 AB14 Y13 AA13 AB13 W12 Y12 AA12 AB12
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
Notes: 1. GTS = global output enable, GSR = global reset/set, GCK = global clock, CDRST = clock divide reset, DGE = DataGATE enable.
17
XC2C384 JTAG, Power/Ground, No Connect Pins and Total User I/O

Pin Type TCK TDI TDO TMS VAUX (JTAG supply voltage) Power internal (VCC) Power Bank 1 I/O (VCCIO1) Power Bank 2 I/O (VCCIO2) Power Bank 3 I/O (VCCIO3) Power Bank 4 I/O (VCCIO4) Ground TQ144 67 63 122 65 8 1, 37, 84 27, 55, 73, 93 109, 127, 141 73, 93 109, 127 29, 36, 47, 62, 72, 89, 90, 99, 108, 123, 144 PQ208 98 94 176 96 11 1, 53, 124 33, 59, 79 26, 204 92, 105, 132 133, 157, 172, 181 13, 24, 42, 52, 68, 81, 93, 104, 129, 130, 141, 156, 177, 190, 207 FT256 P12 R11 A10 N12 F4 P3, K13, D12, D5 J6, K6, L7, L8 F7, F8, G6, H6 J11, K11, L10, L9 F10, F9, H11 F11, F6, G10, G7, G8, G9, H10, H7, H8, H9, J10, J7, J8, J9, K10, K7, K8, K9, L11, L6 FG324 Y19 AB19 C14 AB20 F1 AA3, N20, A20, D4, E3 M9, N9, P10, P11 J10, J11, K9, L9 M14, N14, P12, P13 J12, J13, K14, L14 D5, D18, E4, E19, J9, J14, K10, K11, K12, K13, L10, L11, L12, L13, M10, M11, M12, M13, N10, N11, N12, N13, P9, P14, V4, V19, W5, W18 A11, A12, A14, A15, A16, A17, B12, B13, C11, D1, D11, D13, F3, H20, J4, K4, L4, M4, N4, P19, P22, R19, R20, W3, W9, W13, W16, W17, Y3, AB1 212 240
No connects
Total user I/O (includes dual function pins)
118
173
18
Ordering Information
JC Pin/Ball JA Spacing (C/Watt) (C/Watt) 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 1.0mm 1.0mm 1.0mm 1.0mm 1.0mm 1.0mm 0.5mm 0.5mm 1.0mm 1.0mm 34.1 34.1 34.1 36.1 36.1 36.1 33.5 33.5 33.5 39.3 39.3 39.3 34.1 36.1 33.5 39.3 6.5 6.5 6.5 8.4 8.4 8.4 5.5 5.5 5.5 5.3 5.3 5.3 6.5 8.4 5.5 5.3 Package Dimensions 20mm x 20mm 20mm x 20mm 20mm x 20mm 28mm x 28mm 28mm x 28mm 28mm x 28mm 17mm x 17mm 17mm x 17mm 17mm x 17mm 23mm x 23mm 23mm x 23mm 23mm x 23mm 28mm x 28mm 28mm x 28mm 17mm x 17mm 23mm x 23mm Commercial (C) I/O 118 118 118 173 173 173 212 212 212 240 240 240 118 173 212 240 Industrial (I) C C C C C C C C C C C C I I I I
Part Number XC2C384-6TQ144C XC2C384-7TQ144C XC2C384-10TQ144C XC2C384-6PQ208C XC2C384-7PQ208C XC2C384-10PQ208C XC2C384-6FT256C XC2C384-7FT256C XC2C384-10FT256C XC2C384-6FG324C XC2C384-7FG324C XC2C384-10FG324C XC2C384-10TQ144I XC2C384-10PQ208I XC2C384-10FT256I XC2C384-10FG324I
Package Type Thin Quad Flat Pack Thin Quad Flat Pack Thin Quad Flat Pack Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Quad Flat Pack Fine Pitch Thin BGA Fine Pitch Thin BGA Fine Pitch Thin BGA Fine Pitch BGA Fine Pitch BGA Fine Pitch BGA Plastic Quad Flat Pack Plastic Quad Flat Pack Fine Pitch Thin BGA Fine Pitch BGA
Note: C = Commercial (T A = 0 C to +70 C); I = Industrial (T A = 40 C to +85 C).
19
VCC I/O(1) I/O(1) I/O I/O(1) I/O(1) I/O VAUX I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
VCCIO1 I/O GND I/O(2) I/O I/O(2) I/O I/O I/O(4) GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
GND I/O(3) I/O VCCIO2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO4 I/O I/O I/O GND TDO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO4
TQ144 Top View
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCCIO3 I/O I/O GND GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO1
Figure 2: TQ144 Thin Quad Flat Pack
20
VCCIO1 I/O I/O I/O I/O I/O I/O GND TDI I/O TMS I/O TCK I/O I/O I/O I/O GND
VCC I/O(2) I/O(5) I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
(1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset (4) - Clock Divide Reset (5) - DataGATE Enable
VCC I/O I/O(1) I/O I/O(1) I/O I/O(1) I/O I/O(1) I/O VAUX I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCCIO2 I/O I/O I/O I/O I/O I/O VCCIO1 I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O(2) I/O I/O(2) I/O I/O I/O I/O I/O(4) GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
I/O GND I/O(3) I/O VCCIO2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O VCCIO4 I/O I/O I/O GND TDO I/O I/O I/O VCCIO4 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO4
PQ208 Top View
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
VCC I/O I/O(2) I/O I/O I/O(5) VCCIO1 I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO1 I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO3 GND TDI I/O TMS I/O TCK I/O I/O I/O I/O I/O GND
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VCCIO4 VCCIO3 I/O GND GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO3
Figure 3: PQ208 Plastic Quad Flat Package
21
16
15
14
13
12
11
10
2
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O(2) I/O I/O(4) I/O I/O(5)
A B C D E F G H J K L M N P R T
I/O
I/O
I/O
I/O
I/O
I/O
TDO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O(3)
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O(1)
I/O(1)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O(1)
I/O
I/O(1)
I/O
I/O
I/O
I/O
I/O
I/O
GND VCCIO4 VCCIO4 VCCIO2 VCCIO2
GND
I/O
VAUX
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
GND
GND VCCIO2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO4
GND
GND
GND
GND VCCIO2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO3
GND
GND
GND
GND VCCIO1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
VCCIO3
GND
GND
GND
GND VCCIO1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCCIO3 VCCIO3 VCCIO1 VCCIO1
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O(2)
I/O
I/O
I/O
I/O
I/O
TMS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O(2)
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
TDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
FT256 Bottom View
Figure 4: FT256 Fine Pitch Thin BGA
22
22
21
20
19
18
17
16
15
14
13
12
11
10
2
I/O(3) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O(4)
A B C D E F G H J K L M N P R T U V W Y AA AB
I/O
I/O
VCC
I/O
I/O
N/C
N/C
N/C
N/C
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O(1) I/O(1)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDO
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O(1)
NC
I/O
I/O
I/O
GND
GND
VCC
I/O(1)
I/O
I/O
I/O
I/O
I/O
NC
VAUX
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N/C
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND VCCIO4 VCCIO4 VCCIO2 VCCIO2 GND GND GND GND
GND
N/C N/C
I/O I/O
I/O I/O
I/O
I/O
I/O
I/O
VCCIO4
VCCIO2 VCCIO2
I/O
I/O
I/O
I/O
VCCIO4
GND
GND
GND
GND
N/C
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO3
GND
GND
GND
GND VCCIO1
N/C N/C
I/O I/O
I/O I/O
I/O
I/O
VCC
I/O
VCCIO3
GND
GND
GND
GND VCCIO1
N/C
I/O
I/O
NC
GND VCCIO3 VCCIO3 VCCIO1 VCCIO1
GND
I/O
I/O
I/O
I/O
I/O
N/C
N/C
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND N/C I/O I/O
GND
I/O(2)
I/O
I/O
I/O
I/O
I/O
GND
N/C
I/O
I/O
N/C
I/O
I/O
N/C
I/O
I/O
GND
I/O
NC
I/O
I/O
I/O
I/O
TCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O(2)
I/O I/O
I/O I/O
I/O TMS
I/O TDI
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O(5) I/O
I/O I/O
VCC I/O(2)
I/O NC
FG324 Bottom View
Figure 5: FG324 Fine Pitch BGA Figure 6:
23
Revision History
The following table shows the revision history for this document. Date 05/31/02 08/20/02 Version 1.0 1.1 Initial Xilinx release. Minor Changes Revision
24

Ds 095

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Ds 095

Uploaded by

Copyright:

Available Formats

0

XC2C384 CoolRunner-II CPLD

DS095 (v1.1) August 20, 2002

Advance Product Specification

Refer to the CoolRunner-II family data sheet for architecture description.

DS095 (v1.1) August 20, 2002 Advance Product Specification

Supported I/O Standards

Fast Zero Power Design Technology

0 0 25 50 75 100 125 150 175 200 225

DS095 (v1.1) August 20, 2002 Advance Product Specification

XC2C384 CoolRunner-II CPLD

Absolute Maximum Ratings

Recommended Operating Conditions

DC Electrical Characteristics (Over Recommended Operating Conditions)

DS095 (v1.1) August 20, 2002 Advance Product Specification

XC2C384 CoolRunner-II CPLD

LVCMOS and LVTTL 3.3V DC Voltage Specifications

LVCMOS 2.5V DC Voltage Specifications

DS095 (v1.1) August 20, 2002 Advance Product Specification

XC2C384 CoolRunner-II CPLD

LVCMOS 1.8V DC Voltage Specifications

1.5V DC Voltage Specifications(1)

Notes: 1. Hysteresis used on 1.5V inputs.

DS095 (v1.1) August 20, 2002 Advance Product Specification

XC2C384 CoolRunner-II CPLD

SSTL2-1 DC Voltage Specifications

SSTL3-1 DC Voltage Specifications

HSTL1 DC Voltage Specifications

DS095 (v1.1) August 20, 2002 Advance Product Specification

XC2C384 CoolRunner-II CPLD

Symbol VOL IIL IIH

DS095 (v1.1) August 20, 2002 Advance Product Specification

XC2C384 CoolRunner-II CPLD

AC Electrical Characteristics Over Recommended Operating Conditions

DS095 (v1.1) August 20, 2002 Advance Product Specification

XC2C384 CoolRunner-II CPLD

-7 Max. Min. 0.0

-10 Max. Units ns us

DS095 (v1.1) August 20, 2002 Advance Product Specification

XC2C384 CoolRunner-II CPLD

Internal Timing Parameters

Min. 1.2 0 1.2 0 -

TIN TFIN TGCK TGSR TGTS TOUT TEN

I/O Standard Time Adder Delays 1.5V CMOS

I/O Standard Time Adder Delays 1.8V CMOS

DS095 (v1.1) August 20, 2002 Advance Product Specification

XC2C384 CoolRunner-II CPLD

Internal Timing Parameters (Continued)

I/O Standard Time Adder Delays 2.5V CMOS

I/O Standard Time Adder Delays 3.3V CMOS/TTL

I/O Standard Time Adder Delays HSTL, SSTL

Switching Test Conditions

Number of Outputs Switching

DS095 (v1.1) August 20, 2002 Advance Product Specification

XC2C384 CoolRunner-II CPLD

Pin Descriptions (Continued)

1 1 1(GSR) 1 1 1 1 1 1 1 1 1 1 1 1 1 2(GTS2) 2 2(GTS3) 2 2(GTS0) 2 2 2 2 2 2 2 2 2 2(GTS1) 2

143 142 140 139 2 3 4 5 6 7

2 208 206 205 203 202 201 200 199 3 4 5 6 7 8 9 10

138 137 136 135 134 9 10 11 12 -

198 197 196 195 194 193 192 191 12 14 15 16 17 18 19 20 21

DS095 (v1.1) August 20, 2002 Advance Product Specification