ACKNOWLEDGMENT

We are grateful to Department of Electronics and Communication Engineering, University college of Engineering, Hyderabad, Which gives us the opportunity to have profound technical knowledge. Theyre by enabling us to complete the project.

We express our sincere and heartful thanks to Dr.CH.Vijay Kumar (PRINCIPAL university college of engineering hyderabad) for his kind permission to undertake this project work.

We are extremely grateful to M.Sumalatha (HOD of ECE, university college of Engineering ,Hyderabad) for her valuable suggestions and timely help in the endeavor and which paved the way for the successful completion of this project.

We specially surrender humble thanks and record our deep sense of gratitude to our guide, who helped us a lot, guided us in excellent way by keeping us always in positive mood and our wills alive. He is none other than M.Rambabu

Last but not least, we express our heartfelt thanks to all this staff members and friends for all help and co-operation extended in bringing out this project successfully in time.

D.DIVYA D.KRISHNA ADITHYA B.NAGA THRINADH REDDY E.ANIL KUMAR

(08C51A0426) (08C51A0423) (08C51A0408) (08C51A0432)

CONTENTS
Acknowledgment Abstract Contents List of Figures List of Tables CHAPTER 1 Introduction
1.1 Introduction 1.1.1 What is cryptography 1.1.2 How does cryptography work 1.1.3 The purpose of cryptography 1.2 Methods of encryption 1.2.1 Symmetric cryptography 1.2.2 Asymmetric cryptography 1.3 Types of cryptographic algorithms 1.4 Introduction to aes 1.4.1 Block cipher 1.5 Applications

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01 01 02 03 04 04 07 10 11 12 13

CHAPTER 2

Advanced encryption standard algorithm

2.1 Introduction 2.2 Terminologies 2.3 Algorithm parameters 2.4 Aes algorithm 2.4.1 Specification 2.4.2 Description 2.5 Encryption 2.5.1 Aes cipher functions 2.5.1.1 Subbytes transformation 2.5.1.2 Shiftrows transformation .5.1.3 Mixcolumns transformation 2.5.1.4 Addroundkey transformation 2.5.2 Key expansion
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14
14 14 15 16 16 17 18 19 20 21 22 24 25

2.6 Summary

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CHAPTER 3

Aes algorithm implementation

3.1 Introduction 3.2 Implementation requirements 3.3 Notation and conventions 3.4 Mathematical preliminaries 3.5 General implementation flow 3.6 Implementation 3.7 Summary

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29 29 30 32 33 34 36

CHAPTER 4

Results and discussion

4.1 Introduction 4.2 Simulation results 4.3 Introduction to fpga 4.3.1 Fpga flow 4.4 Synthesis result 4.5 Summary

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37 37 43 44 45 47

CHAPTER 5

Software requirements
5.1 Introduction 5.2 Usage of Xilinx ISE for VHDL Based Design 5.2.1. Create new project 5.2.2. Start with you VHDL code 5.3 Advantages and Disadvantages 5.3.1 Advantages: 5.3.2 Disadvantages

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48 48 48 48 49 49 49

CHAPTER 6

Conclusion and Future scope

6.1 conclusion 6.2 future scope

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50 50

APPENDIX

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LIST OF FIGURES Figure No.

1.1 1.2 1.3 1.4 1.5 1.6 2.1 2.2 2.3 2.4 2.5 2.6 3.1 3.2 4.1 4.2 4.3

Title
Encryption and decryption symmetric algorithm for encryption function. Asymmetric cryptosystem Type of security service that will be provided Three types of cryptographic algorithms Overall Representation of Encryption Top Level Block Diagram of AES Algorithm Block Diagram for AES Round and AES Last Round SubBytes Operation of the State ShiftRows Operation of the State MixColumns operates on the State column-by-column AddRoundKey Operation State Array Input and Output General Implementation Flow Diagram Simulation Result of AES Encryption for Set-1 Inputs Simulation Result of AES Encryption for Set-2 Inputs

Page No.
01 05 07 09 11 11 17 20 21 22 24 25 31 33 38 39 40

Simulation Result of Encryption with Internal Operation for Set-1 Inputs Simulation Result of Encryption with Internal Operation for Set-2 Inputs Simulation Result of Encryption for Set-1 Inputs Simulation Result of Encryption for Set-2 Inputs Logic Block RTL Schematic

4.4

41

4.5 4.6 4.7 4.8

42 43 44 45

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List of Tables

Table No.
2.1 2.2 2.3 2.4 2.5

Title
Terminologies and their Definitions Parameters, Symbols and their Definitions AES encryption cipher using a 16 byte key Key Expansion Rcon Table

Page No.
15 16 19 26 27

Abstract
In todays world most of the communication is done using electronic media. Data Security plays a vital role in such communication. Hence, there is a need to protect data from malicious attacks. Cryptography is the science of secret codes, enabling the confidentiality of communication through an insecure channel. It protects against unauthorized parties by preventing unauthorized alteration of use. Generally speaking, it uses a cryptographic system to transform a plaintext into a cipher text, using most of the time a key. Advanced Encryption Standard (AES), also known as Rijndael, is an encryption standard used for securing information. AES was published by NIST (National Institute of Standards and Technology). AES is a block cipher algorithm that has been analyzed extensively and is now used widely. AES is a symmetric block cipher that is intended to replace DES as the approved standard for a wide range of applications. The block cipher Rijnddael was designed by Dr. Joan Daemen and Dr. Vincent Rijmen and the name of the algorithm is a combination of the names of its two creators. Rijndael is very secure and has no known weakness. Rijndael is conventional (symmetric key) system and is relatively simple cipher in many respects. It takes an input block of a certain size, usually 128, and produces a corresponding output block of the same size. The transformation requires a second input, which is the secret key. It is important to know that the secret key. In this work, both encryption and decryption will be carried out with the key length of 128 bits, that is, both AES encrypter and the AES decrypter were integrated. Hence the input block and secret key will be provided for encryption and the cipher block and same secret key will be provided to the decryption to get the proper block as output. All the transformations of both Encryption and Decryption will be developed using VHDL language and will be verified with the help of its simulation result. The AES Encryption and Decryption is synthesized on FPGA family of Virtex-2 using Xilinx ISE tool and hence the design operates at a maximum clock frequency of 18.970 MHz with a minimum period of 52.716ns.

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