Embedded system

UNIT-I Introduction to Embedded Systems

VVCET

Part A (2 MARKS) 1. Define a System. 2. What is an embedded system? 3. What are the main components of an embedded system? 4. Define embedded microcontroller. 5. What are the various classifications of embedded systems? 6. What are the two essential units of a processor on a embedded system? 7. What does the execution unit of a processor in a embedded system do? 8. Give examples for general purpose processor. 9. Define microprocessor. 10. When is Application Specific System processors (ASSPs) used in an embedded system? 11. What is the need for LCD and LED displays? 12. Define ROM image. 13. Define device driver. 14. Name some of the softwares used for the detailed designing of an embedded system. 15. What are the various models used in the design of a embedded system? 16. Give some examples for small scale embedded systems. 17. Give some examples for medium scale embedded systems 18. Give some examples for sophisticated embedded systems Part B (16 MARKS) 1. List the hardware units that must be present in the embedded systems. (16) 2. i) Explain the Exemplary applications of each type of embedded system. (8) (ii) Explain the different program layers in the embedded software and also the process of converting a C program into the file for ROM image with suitable block diagrams. (8) 3. Explain the Embedded System on Chip (SoC) & in VLSI circuit.(16) 4. i) Explain the various form of memories present in a system (8) ii) Explain the software tools in designing of an embedded system. (8) UNIT-II PROCESSOR AND MEMORY MANAGEMENT Part A (2 MARKS) 1. What are the common structures units in most processors? 2. What are the special structural units in processors for digital camera systems, real-time video processing systems, speech compression systems, voice compression systems, voice compression systems and video games? 3. How do separate caches for instruction, data and branch transfer help? 4. What is the advantage of having multi way cache units so that only that part of cache unit is activated necessary data to execute a subset of instructions? List four exemplary processor with multi-way caches 5. When you need MAC unit at a processor in the system? 6. Explain three stage pipeline and superscalar processing and branch and data dependency penalties 7. What are the advantages in Harvard architecture? What is the ease of accessing stack and data table at a program memory less in Harvard memory architecture compared to Princeton memory architecture? 8. Explain the three performance metrics of processor: MIPS, MFLOPS, and DHRYSTONE PER SECOND 9. Why Should Program Divided in to data types and data structures and each placed in different memory blocks or segments? 10. Explain how the following data structures store at the memory: stack, vector, array, circular queue, list and look up table DEPARTMENT OF EEE Page 1

Embedded system

VVCET

11. What do you mean by device register and device address 12. How does a boot block flash differ from flash memory? How do flash, EEPROM, and FLASH EEPROM differ? When do you masked ROM for ROM image and when boot flash ROM in an embedded system? 13. How do the 68HC12 and 68HC16 differ? When you will prefer 68HC12 and 68HC16? 14. How does memory map help in designing a locator program? What are the Intel and Motorola format for ROM image records? 15. What do you mean by the terms: i. Atomic operations ii. Burst mode iii. PowerPC serial power saving modes iv. Encryption key v. QUARTER-CIF vi. EDO RAM vii. RDRAM viii. Peripheral transactions server, ix. Shadow segment x. On-chip DMAC xi. TDM Part B (16 MARKS) 1. 2. 3. 4. 5. 6. 7. 8. 9. Explain structural units in a processor Explain cache mapping technique Explain selection of processor in embedded system Explain various types of memory devices Explain the memory mapping technique Explain DMA processor with modes of operation with neat diagram Describe the Automatic Vending Machine with neat diagram Describe the Chocolate Vending Machine with neat diagram Describe the Digital Camera and Voice Recorder with neat diagram Unit-III Devices and Buses for Devices Network Part A (2 MARKS) 1. Differentiate synchronous communication and iso-synchronous communication.(Page No -134) 2. What are the two characteristics of synchronous communication? 3. What are the three ways of communication for a device? 4. Expand a) SPI b) SCI 5. Define software timer. 6. What is I2C? 7. What are the bits in I2C corresponding to? 8. What is a CAN bus? Where is it used? 9. What is USB? Where is it used? 10. What are the features of the USB protocol? 11. Explain briefly about PCI and PCI/X buses. 12. Define half-duplex communication. 13. Define full duplex communication. 14. Define Real Time Clock (RTC)? 15. Define Time-out or Time Overflow? Part B (16 MARKS) 1. i) Explain the parallel port devices. (8) ii) Explain the sophisticated interfacing features in device ports. (8) 2. Explain the timer and counting devices. (16). 3. i) Explain the signal using a transfer of byte when using the I2C bus and also the format of bits at the I2C bus with diagram. (8) ii) Explain the internal serial communication devices. (8) 4. Explain the following parallel communication devices: DEPARTMENT OF EEE Page 2

Embedded system
i) ISA bus (8) ii) PCI and PCI/X (8) UNIT-IV [I/O PROGRAMMING AND SCHEDULING MECHANISM] Part-A

VVCET

1. What are the criteria by which an appropriate programming language is chosen for embedded software of a given system 2. What is the most important futures in c that makes it popular high level language for an embedded system? 3. What is the most important futures in Java that makes it highly useful high- level language for an embedded system in many network-related applications? 4. Why do you break a program into header files, configuration files, modules and functions? 5. Design a table to give the features of top-down design and bottom-up design of a program . 6. Explain the importance of the following declaration: static, volatile and interrupt in embedded C 7. How and when are the following used in a program? (a) define (b) typedef (c) null pointer (d)passing reference (e) Recursive functions 8. Why do we use infinite loop in embedded system software? 9. What are the advantages of re-entrant functions in embedded system software? 10. How are the queues used for the network? 11. Define ISR 12. Define interrupt pending register 13. Define context and context switching 14. Define interrupt latency and worst case latency 15. Define deadline 16. Define hardware assigned priority and software assigned priority with examples 17. Define polling 18. Define scheduling 19. Define FSM 20. Define Petri Net Model 21. Define process 22. Define threads 23. Define tasks 24. Describe the use of atomic operation for solving shared data problem? 25. What are the steps need to eliminate the shared data problem 26. Define semaphore 27. Define mutex 28. Explain priority inversion situation 29. Explain deadlock situation 30. Define Inter processor communication[IPC] 31. How does a data output generated by a process transfer to another using a IPC 32. What are the parameters at a TCB at task 33. What are the states of task? Which is the entity controlling the transititon from one state to another state? 34. Define critical section of task 35. How does use of the counting semaphore differ from mutex? How counting semaphore is is used? 36. Give an example for deadlock situation during multiprocessing execution 37. What are the advantages and disadvantages of disabling interrupts during the running the critical section of process 38. Explain the multitasking OS and multitasking Scheduler 39. How do the function differ from ISRs, task, threads and processes 40. List the features of P and V semaphore and how these are used as resource key, as a counting semaphore and as mutex DEPARTMENT OF EEE Page 3

Embedded system

VVCET

41. What are the situations, which lead to priority inversion problems? 42. How does an OS solve problem by priority inheritance mechanism 43. What is meant by pipe? How it is differ from queue? 44. What is meant by spinning lock? Explaining the situation in which use of the spin lock mechanism would be highly useful to lock the control to higher priority task? 45. When are sockets used for IPCs? List four examples. When RPCs used? List two examples 46. What are the analogies between task, thread and process? And also list the difference between them 47. Give the advantage and disadvantages of C++ and Java

Part-B Explain the infinite loops within each task for mobile phone system Explain the concept of context switching with example Explain the interrupt servicing mechanism using SWI Explain the Interrupt latency period Explain the device driver using ISR and Without using ISR mechanism Explain the concept of round robin scheduling Explain the concept of priority based scheduling Design a table to clearly distinguish the cases when there is concurrent processing of processes, with task, threads by using scheduler 9. Explain the concept of semaphore with exemplary example and concept of P and V semaphore 10. Write a program for using P and V semaphore function with a mutex property and as counting semaphores 11. Explain FSM model with example 12. Explain Petri net model with example 13. Explain IPC with example 14. Explain the programming elements in C and state the advantages 15. Explain the use of function calls with example program 16. Explain the queue, stack, list 17. i) Tabulate program elements: Macros and Functions and their uses. (ii) Explain the use of pointers, NULL pointers 18. Explain the multiple function calls in the cyclic order in the main. Also write the advantages of building ISR queues. 19. (i) Explain the optimization of memory codes. (ii) Explain the C program compiler and cross compiler. 20. Explain the Embedded programming in C++. 21. Explain the function pointers, function queues and ISR queues. 1. 2. 3. 4. 5. 6. 7. 8.

Unit V Part-A 1. Define process. 2. Define RTOS 3. Mention the Goals of RTOS 4. Mention the modes when an OS the processor in the system runs 5. Give the structure model of RTOS 6. Define Kernel 7. Define IPC 8. Give the types of management function RTOs 9. Mention the types of ISR in RTOs environment 10. Define time slicing 11. Define Spin lock 12. Define Hard & soft real time operability 13. Define scheduling 14. Define task DEPARTMENT OF EEE Page 4

Embedded system
15. 16. 17. 18. Part-B

VVCET

Define TCB Define ICE What are the tools used for debugging an system under development process Define action plan

1. Explain the goals of operating systems 2. Explain the three alternative systems in three RTOS for responding a hardware source call with the neat diagram 3. Explain the scheduler in which RTOS insert into the list and the ready task for sequential executionin a co-operative round robin model. 4. Describe in detail about the design issues in system development process 5. Explain the action plan in detail 6. Explain embedded software development process and tools with neat diagram 7. Discuss the various kinds of debugging tools after development process of embedded system. 8. Explain the following (a) Use of target system (b) emulator (c) IDE (or) host targeting machine (d) ICE

DEPARTMENT OF EEE

Page 5

Embedded system
UNIT-I INTRODUCTION TO EMBEDDED SYSTEM

VVCET

1.

Define a System. A way of working, organizing or doing some tasks by following fixed plan, program, and set of rules Eg.time display system

2.

What is an embedded system? A sophisticated system that has a computer (hard ware with application software and RTOS embedded in it) as one of its components. An embedded system is a dedicated computer based system for an application or product

3.

What are the main components of an embedded system? Microprocessor, memory (primary-RAM, ROM and secondary- hard disk), input units (keyboard, mouse, scanner), output units (video monitor, printer), networking units (Ethernet card, drivers), I/O units (modem).

4.

Define embedded microcontroller. A microcontroller is a single chip VLSI unit (also called microcomputer) which, through having limited computational capabilities possess enhanced i/p-o/p capabilities and a number of on chip functional units

5.

What are the various classifications of embedded systems? General purpose processor- microprocessor, microcontroller, embedded processor, DSP, media processor ASSP-application specific system processor Multiprocessor system using General purpose processor (GPP) and Application specific instruction processor[ASIP] GPP core or ASIP core or VLSI circuit

6.

What are the two essential units of a processor on a embedded system? Program flow control unit- fetching instruction from memory Execution unit- pertaining data transfer operation and data conversion from one form to another. What does the execution unit of a processor in a embedded system do? Execution unit- pertaining data transfer operation and data conversion from one form to another. Executes the instructions for a program control task, say, halt, interrupt, jump or another set of instructions. It can also execute the instructions for a call or branch to another program and for a call to a function. Give examples for general purpose processor. Microprocessor, microcontroller, embedded processor, DSP, media processor Define microprocessor A microprocessor is a single chip VLSI that has a CPU and may also have some other units (for example cache, floating point processing arithmetic unit, pipelining and super-scaling units)

7.

8.

9.

DEPARTMENT OF EEE

Page 6

Embedded system

VVCET

10. When is Application Specific System processors (ASSPs) used in an embedded system? A processing unit for specific tasks, for example, image compression, and that is integrated through the buses with the main processor in the embedded system ASSP is a additional processing unit for running the application specific tasks in place of processing using embedded software 11. What is the need for LCD and LED display? A system requires an interfacing circuit and software to display the status or message for a line, for multiline display, or flashing display. For displaying and messaging, the LCD matrix displays and LED arrays are used in a system. The system provides necessary interfacing circuit and software for the output to display controller and LED interfacing ports. 12. Define ROM image The Process of Converting an assembly language program in to the machine codes and finally obtaining ROM image. It is a program reallocates the linked files of the program application and the RTOS codes at the actual addresses of the ROM memory. It creates a file in a standard format. File is called ROM image. 13. Define device driver. Interrupt service routine software, which runs after the programming of the control register of a peripheral device (or virtual device) and to let the device get the inputs or outputs. It executes on an interrupt to or from the device. 14. Name some of the softwares used for the detailed designing of an embedded system. Editor, interpreter, complier, assembler, cross assembler, simulator, source code engineering software, RTOS, stethoscope, tracescope, integrated development environment [IDE], prototype, Locator. 15. What are the various models used in the design of a embedded system? 1. finite state machine [FSM] 2. control and data flow graph 3. petrinet model 4. Activity diagrams based UML[unified modeling language] model 5. Synchronous data flow model[SDF] 6. Timed petri nets and Extended predicate / Transition net 7. Multithread graph [MTG] system. 16. Give some examples for small scale embedded systems. Automatic chocolate vending machine, washing system, multitasking toys, keyboard controller, serial port controllers, CD drive and hard disk drive 17. Give some examples for medium scale embedded systems Computer networking router, internet appliances, entertainment system, banking system, signal tracking system, communication system, TCP/IP, DNA sequence and pattern storage memory card and DNA pattern recognizer. 18. Give some examples for sophisticated embedded systems LAN, real time video and speech, embedded interface and networking system using high speed (400 MHz), ultra high speed[ 10 gbps], security products and high speed network security, space life boat (NASAs X -38 project)- international space station.

DEPARTMENT OF EEE

Page 7

Embedded system

VVCET

19. What is meant by KERNEL A program with functions for memory allocations and de-allocation, task scheduling, inter processor communication, effective management of shared memory access by using the signals, exception error handling signals, semaphores, queues , mail boxes, pipes, and sockets, i/o management , interrupt control handler, device drivers and management 20. Define SOC Embedded system being designed on single silicon chip called SOC [system on chip]. An embedded processor is a part of the SOC VLSI circuit. An SOC may be embedded with the following components : multiple processors, memories, multiple standard source solutions called IP [intellectual property] cores and logic and analog units. 21. Define charge pump Charge pump for delivering power to the antenna (of 5mm range) for transmission and for system circuits. The charge pump stores charge from received RF at the card antenna hear its host in vicinity [charge pump consists of diode and ferro- material based capacitor] Or A charge pump consists of a diode and followed by capacitor. The diode get forward bias input from an external signal. The charge pump inside the mouse uses to store the charge when the mouse in idle state, the pump dissipates the power when the mouse is used. 22. Mention the function of IP An IP may provide hardwired implement able design of a transform or of an encryption algorithm or a deciphering algorithm An IP may provide a design for adaptive filtering of a signal An IP may provide full design for implementing HTTP or FTP to transmit web page on internet An IP designed for PCI or USB bus controller 23. Assembler= translates the assembly software in to machine codes using a step called assembling Linker= links the code with other required assembled codes. Linking is necessary because of the number of codes to be linked for the final binary file. Loader= performs the task of reallocating the codes after finding the physical RAM addresses available at given instant. It loads in to section of RAM the program that is ready to run. Locating= reallocates the linked file and create a file permanent location of standard format. The format should be in HEX file. And permanently placing them at the actually available ROM addresses. 24. Different program layers in the embedded software Preprocessor commands, main function, ISR, Tasks(1,2.n), kernel scheduler, standard library functions including standard protocol functions for sending and receiving stack 25. Define clock? Fixed frequency pulses that an oscillator circuit generates and that control all operation during processing and all timing reference of the system. Frequency depends on the needs of the processor circuits. DEPARTMENT OF EEE Page 8

Embedded system
26. RESET and RESET CIRCUIT

VVCET

A processor state in which the processor requires the initial values and from which starts an initial program , this program is usually the one that also runs on power up.==> reset A circuit forces reset state and that gets activated for a short period on power up. When reset is activated, the processor generates a reset signal for the other system units needing reset.

27. FPGA Field programmable gate arrays on a chip. This chip has a large number of arrays with each elements having fusable links. Each element of array consists of several XOR,AND, OR, multiplexer, demultiplexer and tristate gates. By appropriate programming of the fusable links, a design of a complex digital circuit is created on chip 28. What is meant by registers? They are associated with processor and temporarily store the variable values from the memory and from the execution unit during processing of an instructions.

29. ADC- a unit that converts, as required, the analog input between + and pins with respect to the reference voltage to digital 8 or 10 or 12 bits. 30. PWM- pulse width modulator to provide pulse of width scaled to the analog output desird. On integrating PWM output, the DAC operation achieved. 31. DAC- digital bits converted to analog signal scaled to reference voltage 32. Physical device= a device such as printer or key Pad connected to ports Virtual device= a file or pipe that programmed for opening and closing and for reading and writing such as program for attaching and detaching a physical device and for I/P and O/P Pipe= a data structure which is sent a byte stream from a data source and which delivers the byte stream to data sink[ reading and writing the streams of bytes or words] File= A data structures which sends the records to the data sink and stores the data from the data source. A file is computer may also stored at the hard disk.[ buffering a stream of bytes] 33. What is meant by device? Purpose of controlling, handling, reading and writing actions can be consists of 3 components [1] control register- it store that bit on setting or resetting by the device driver, control the device actions [ii] status register- it provide the flag to show the device status [iii] device mechanism that controls the device action 34. Functions of device control [i] Initializing that is activated by placing appropriate bit at the control register or word [ii] Calling an ISR on interrupt or on setting a status flag in the status register and run the ISR [iii] Resetting the status flag after interrupt service

DEPARTMENT OF EEE

Page 9

Embedded system

VVCET

35. Device management= it provides codes for detecting the presence of device and initializing these and for testing the device that are present. These modules also include software for allocating and registering port addresses for various device at distinctly different addresses, including codes for detecting any collision between these, if any. 36. Advantages of Stop instruction-power operation [i] on disabling the clock input to the processor [ii] on stopping the external clock circuit functions [iii] on the processor operating in auto shut down mode Advantages of wait instruction- power operation [i] which slows ordisables the clock inputs to the processor units including ALU [ii] when an external circuit becomes non- functional Waiting state changes in to running state by [i] interrupt occurs [ii] reset signal 37. Difference b/w floating point and fixed point arithmetic processing unit FIXED POINT It is faster than floating point processing unit Arithmetic used signed or unsigned integers employing processor register or memory. Fixed point processor speed is 4800 MIPS. Loss of Precession in fixed point. It must take care of overflows. Overflows means an operation in which result exceeds the capacity of the processor register for storing that number in single word. For e.g. Firstly 35967 and 17872786 can be multiplied during fixed point arithmetic processing unit later the intermediate result is divided at the final stage by 1012 to obtain final result. FLOATING POINT Process is slower than the fixed point arithmetic processing unit. Arithmetic using processor register or memory, where the decimal number and fractional numbers are stored in a standard floating point representation Occasionally the precession is needed is such that it may require floating point operations. 38. DIFFERENCE B/W CISC AND RISC ARCHITECTURE CISC RISC It provides the number of addressing It provides very few addressing modes modes It provides fixed instruction length Instructions of variable length Needs a complex complier design. An easy complier design Provides precise and intensive Provides precise and intensive calculation faster than CISC calculation slower than RISC It has a hardwired programmed without Micro programmed unit with control control memory to implement a small memory that implements a large instruction set with a separate h/w for instruction set with a smaller h/w . implementing each instructions.

DEPARTMENT OF EEE

Page 10

Embedded system
UNIT-2

VVCET

1. What are the common structural units in most processors? MAR, MDR, internal data bus, address bus, data bus, control bus, BIU , IR, ID, CU, ARS, ALU, PC, SRS, SP, IQ. 2. What are the special structural units in processors for digital camera systems, real-time video processing systems, speech compression systems, voice compression systems, voice compression systems and video games? FLPU, AOU, FRS, INSTALL CACHE, BT CACHE, DATA CACHE, PFCU,MMU 3. How do separate caches for instruction, data and branch transfer help? I-cache = it sequentially stores, like an instruction queue, the instructions in FIFO mode. It lets the processor execute instruction at greater speed while, through PFCU, the processor accesses external system-memories at relatively much slower speeds. BT cache = it facilitates ready availability of the next instructions-set when a branch instruction like jump, loop or call is encountered. Its fetch unit foresees a branching instruction at the I-Cache D-Cache = it stores the pre fetched data from the external memory. A data cache generally holds both the key and value together at a location. It also stores writethrough data when so configured. Write- through data means resulting data from the execution unit that transfer through the cache to external memory addresses also. 4. What is the advantage of having multi way cache units so that only that part of cache unit is activated necessary data to execute a subset of instructions? List four exemplary processor with multi-way caches Refer ans: 03 , examples: ARM 7, Intel 80960A, power PC MPC604, Intel pentium

5. When you need MAC unit at a processor in the system? RISC architecture improves performance by executing instructions in a single clock cycle (by hardwired implementation of instructions), by using multiple register-set windows and files and by reducing dependency on the external memory accesses for data due to the reduced number of addressing modes. The multiply and accumulate unit at a DSP Provides Fast multiplication of two operands, accumulating result at single address. It computes fast an expression such as the following summation. 6. Explain branch and data dependency penalties Branch penalty= if a branching instruction is encountered at a multistage pipeline, then the instructions have to be executed in part at preceding stages become redundant. These instructions have to be executed in full again later on after completion a of the loop or return from a routine. The time required for reprocessing these is called branch penalty. Data dependency penalty= two instructions in two execution lines during a superscalar operation. Further, that one instruction depends on the data output on another. This is improper alignment. One instruction will now have to wait and cant proceed further till the other instruction is executed. The waiting time is the data dependency penalty.

DEPARTMENT OF EEE

Page 11

Embedded system

VVCET

7. What are the advantages in Harvard architecture? What is the ease of accessing stack and data table at a program memory less in Harvard memory architecture compared to Princeton memory architecture? 8. Essential characteristics of processor structure 1. Instruction cycle time executes simple instruction which is I micro second for the 8051 processor operating at 12 MHZ. 2. Internal Bus Width- 32-bit bus 3. CISC or RISC ability to process complex instructions and complex data sets with fewer registers. 4. Program counter bits and its reset Value 5. Stack pointer bits and its initial value resets 6. Pipelined and super scalar units 7. On chip memories as RAM, register files, windows, caches and ROM 8. External interrupts 9. Interrupt controller 10. Bit manipulation instructions 11. Floating point processor 12. Direct Memory Access [DMA] controller with multiple channels. 9. Explain the three performance metrics of processor: MIPS, MFLOPS, and DHRYSTONE PER SECOND MIPS= it is a measure of processing speed of a processor in million instruction per second MFLOPS= It is a measure of processing speed of a processor or DSP in million floating point operations per second. Dhrystone per second= The metric measures the number of times the program can run in a second 1 MIPS= 1757 Dhrystone/ Second 10. Why Should Program Divided in to data types and data structures and each placed in different memory blocks or segments? Program routines and processes can have different segments. Program code can be segmented and each segment stored at a different memory block. These compromises of different segments for data and different segments for the stacks. Each segment has starting addresses and ending memory addresses. Each segment has pointer and an offset addresses. Using an offset, a code or data word is retrieved from a segment. Data structure- stack, queue, pipe, list, array 11. What do you mean by device, device register and device address Device- a physical or virtual unit has three set of registers data , control and status register and that processors addresses like memory Device register- a register in a device for byte,word of data, flags or control bits. Several device registers have common address. Device address- a device address used by processor to access its set of registers there may be one or more device registers. 12. How does a boot block flash differ from flash memory? How do flash, EEPROM, and FLASH EEPROM differ? When do you masked ROM for ROM image and when boot flash ROM in an embedded system? PROM or OTP- a type of memory which is programmable only once a device programmer. OTP is a one time programmable memory

DEPARTMENT OF EEE

Page 12

Embedded system

VVCET

EPROM- a type of memory that is erasable many times by UV light exposure and programmable by a device programmer. EEPROM- A type of memory each byte of which is erasable many times and then programmable by the instructions of a program as well as device programmer FLASH a type of memory each byte of which is erasable many times in a flash at the same instance in a single cycle. Each erased byte is then programmable by the write instructions of a program as well as by device programmer Boot Back Flash= A flash with a few sectors similar to OTP device, to enable storage of boot up program and initial data.

13. How does memory map help in designing a locator program? A memory allocation table such that the map reflects the available memory addresses for various uses of the processor. A memory map defines the addresses of ROM and RAM of the system. It maps guides to the actual presence of the various memories at the various units, EPROM, PROM, ROM, EEPROM, FLASH, SRAM, DRAM and I/O devices. it reflects the memory allocation for the programs, data and I/O operations by the locator program. It shows the memory block and port devices at the addresses. 14. What do you mean by the terms: Atomic operations- It lets a user complier instruction, when broken in to number of processor instructions called atomic operations, finish before an interrupt of a process occurs. This prevents problems from arising out of sharing data between various routines and tasks. Burst mode-burst transfer at a time and then release of the hold on the system bus. A burst may be few KB. 15. Superscalar processor= It has capacity to fetch (instruction from memory), decode (instructions) and execute more than one instructions in parallel at any instant. Power PC MPC601 [ RISC, FIRST POWERPC, 66 MHZ, 132 MIPS] - 3 execution unit - 1 branch unit - 1 integer unit - 1 floating unit - Can dispatch up to 2 instructions and process 3 every clock cycle. 16. Microcode = inside a CPU, the instructions are decoded to a sequence of microcode instructions, which in turn calls a sequence of nano code commands which controls the sequences and ALU. The instructions do not operate directly on the internal resources. HARDWIRED = The instructions are directly executed by hardware and there wont be any micro coding for processing. Hence instruction will be executed in a single cycle. PIPELINING =It means dividing the ALU circuit in to n sub stages. All common steps [instruction fetch, instruction decode, load operands from memory, execute, store results in memory.] Disadvantages of pipeline stall it is caused when any stage within the pipeline cannot complete its allotted task at same time as its peers. This can occur when [i] Wait states are inserted in to external memory access [ii] Instructions are iterative techniques [iii] There is change of program flow [due to branching]

DEPARTMENT OF EEE

Page 13

Embedded system

VVCET

17. Caching: caches are small, fast memory that holds copies of some of the contents of the contents of main memory. They provide higher speed access for the CPU. A cache controller mediates between the CPU and main memory. Cache hit: if the requested location is available in the cache Cache miss :if the requested location is not available in the cache resulting in cache miss penalty (extra time needed to access the missing memory location) Cache miss can occur due to various reasons: Compulsory miss: the first time the location used [not referenced below] Capacity miss: the program working set is too large. Conflict miss : to particular memory location are fighting for the same cache line.

18. Cache mapping : It is used to assign main memory address to cache address and determine hit or miss Types: Direct mapping, fully associative , set-associative mapping. Cache replacement policy: Technique for choosing which block to replace 1. When fully associative cache is full 2. When set-associative caches line is full Random, LRU[Least recently Used], FIFO. 19. Difference between Princeton and Harvard Architecture 1. Vector and pointers, variables, program segments and memory block for data and stacks have different addresses in the program in the Princeton architecture E.g. 8086 and ARM 7 2. Program segments and memory blocks for data and stacks have separate set of addresses in Harvard Architecture. Control signal read & write instructions are separate. E.g. 8051 20. DMA : A Direct memory access by a controller internal or External. DMA operations facilitating the peripherals and devices of the system to obtain access to the system memories directly without processor controlling the transfer of the bytes in a memory block.

DEPARTMENT OF EEE

Page 14

Embedded system
UNIT-3

VVCET

1. What is meant by port? A port is a device [i]. to receive bytes from external peripherals for reading them later using instructions executed on the processor. [ii] To send the bytes to External peripheral or device or processor using instructins executed on the processor.

2. Differentiate synchronous communication and iso-synchronous communication Synchronous Communication: When a byte or frame in of the data is received or transmitted at the constant time intervals with uniform phase differences, the communication is called as synchronous. Bit of a full frame sent in a prefixed maximum time interval. Iso-synchronous Communication: interval can be varied. Special Case when the maximum time

3. What are the two characteristics of synchronous communication? 1. Bytes maintain a constant phase difference. It means they are synchronous. They are no permission for sending either the bytes or the frames at random time intervals, this mode provides for no handshaking during communication. The transmitter is the master and receiver is slave. 2. A clock is ticking at a certain rate ha to be always there for transmitting serially the bits for all the bytes. The clock is not implicit to the synchronous data receiver Asynchronous Communication 1. Bytes need not to be maintain a constant phase difference and are asynchronous. Bytes or frames can be sent at variable time intervals. This mode facilitates in between handshaking between serial transmitter and serial receiver port. 2. It is always implicit to the asynchronous data receiver. The transmitter does not transmit along with the serial stream of bit any clock rate information in asynchronous communication. The receiver does not maintain identical frequency and constant phase difference with transmitter clock. 4. What are the three ways of communication for a device? Synchronous communication, iso synchronous communication, asynchronous communication. 5. Expand a) SPI b) SCIs SPI- Synchronous Peripheral Interfacea. Programmable rates for the clock b. Programmable as slave or master c. Programmable for the instance of the occurrence of negative or positive clock edge d. Programmable for open-drain output SCI- Serial Connect interface a. SCI baud rates are fixed as per rate and prescaling bits b. Transmitter and receiver for the inter processor communication

DEPARTMENT OF EEE

Page 15

Embedded system
5. Define software timer.

VVCET

This is software that executes or increases or decreases a count variable on an interrupt from a timer output or from a real time clock interrupt. A software timer can also generate interrupt on overflow of count value or on finishing value of the counter value [reaching the predefined value] 6. What is I2C? A standard bus that follows a communication protocol and is used between multiple ICs. It permits a system to get data and send data to multiple compatible ICs connected on bus 7. What are the bits in I2C corresponding to? 1st bit- start bit like an UART 2nd- called address field. It defines the slave address, which is being sent the data frame by the master. 3rd- whether a read or write cycle is in progress 4th- bit defines whether the present data is an acknowledgement 5th- IC device data byte 6th NACK [negative acknowledgement] bit 7th- stop bit like in an UART 8. What is a CAN bus? Where is it used? CAN bus is a control area network CAN is a serial bus for interconnecting a central control network. It is mostly used in automobiles. It has fields for bus arbitration bits, control bit for address and data length, data bits, CRC check bits, acknowledgement bits and ending bits 9. What is USB? Where is it used? USB is a standard bus for fast serial transmission and reception. USB is a serial bus for interconnecting a system. It attaches and detaches a device from the network. It uses a root hub. Nodes containing the devices can be organized like a tree structure. It is mostly used in networking IO device like scanner in a computer system 10. What are the features of the USB protocol? USB protocol has this features- a device can be attached, configured and used, reset, reconfigured and used, share the bandwidth with other devices, detached and reattached. 11. Explain briefly about PCI and PCI/X buses. PCI= peripheral component interface PCI/X- extended PCI bus Buses are used and these are independent from the IBM architecture. PCI/X is an extension of PCI and supports 64/100 MHz. PCI provides three types of synchronous parallel interfaces. It has two versions 32/33 Mhz and 64/66 MHz 12. Define half-duplex communication. A serial port having one common I/O line. For E.g. a Telephone line. Message flows one way at a distance

DEPARTMENT OF EEE

Page 16

Embedded system
13. Define full duplex communication.

VVCET

A serial port having two distinct I/O lines. For E.g. a modem connection to the computer COM port. There are two lines TxD and RxD at 9- bins or 25 pins connector. Message flows both ways at an instance. 14. Define Real Time Clock (RTC), system clock, hardware timer? A clock that continuously generates interrupts at regular intervals endlessly. An RTC interrupts at present in the system E.g.SWT System Clock A clock scaled to the processor clock and which always increments without stopping or resetting and generates interrupts at present time intervals. Hardware Timer A timer present in the system as hardware and which gets the inputs from the internal clock with the processor or system clock. A device driver program it like any other physical device. 15. Define Time-out or Time Overflow? A state in which the number of count inputs exceeds the last acquirable value and on reaching that state, an interrupt can be generated. 16. Counter Unit for getting the count- inputs on the occurrence of events that may be at irregular intervals 17. Free running counter A counter, which starts on power-up, which is driven by an interval clock and which can be neither be stopped nor be reset 18. Watchdog timer An important timing device in an system that resets the system after a predefined time out. This time may be definable within the first few clock cycles after resets 19. Iso synchronous communication Communication in which a constant phase difference is not maintained between the frames but maintained within the frame. Clocks that guide the transmitter and receiver not separate. Only the maximum time interval is not pre-fixed between which a frame of bytes transmits i.e. it can be variable. Asynchronous communication A communication in which a constant phase difference is maintained and the clocks that guide the transmitter and receiver are separate. Time interval between which a frame of bytes transmits is not-prefixed and is indeterminate Synchronous communication Communication in which a constant phase difference maintained between the clocks that guide transmitter and receiver 20. HDLC High level data link control protocol for synchronous communication between primary [master] and secondary [slave] as per standard defined. It is a bit-oriented protocol.

DEPARTMENT OF EEE

Page 17

Embedded system
UNIT-4 & 5 I/O PROGRAMMING & SCHEDULE MECHANISM & RTOS

VVCET

1. What are the advantages of Assembly language? It gives the precise control of the processor internal devices and full use of processor specific features in its instruction sets and addressing modes. The machine codes are compact, which requires only small memory. Device drivers need only few assembly instructions. 2. What are advantages of high level languages? Data type declaration Type checking Control structures Probability of non-processor specific codes 3. Define In -line assembly Inserting an assembly code in between is said to be in-line assembly. 4. Mention the elements of C program. 1. Files: 1. Header files 2. Source files 3. Configuration files 4. Preprocessor directives 2. Functions: 1. Macro function 2. Main function 3. Interrupt service routines or device drivers 3. Others: 1. Data types 2. Data structures 3. Modifiers 4. Statements 5. Loops and pointers 5. What is the use of MACRO function? A macro function executes a named small collection of codes, with the values passed by the calling function through its arguments. It has constant saving and retrieving overheads. 6. What is the use of interrupt service routines or device drivers? It is used for the declaration of functions and datatypes, typedef and executes named set of codes. ISR must be small (short), reentrant or must have solution for shared data problem. 7. What are the datatypes available in C language? Char 8 bit; byte 8 bit; short 16 bit; unsigned short 16 bit; unsigned int 32 bit; int 32 bit; long double 64 bit; float 32 bit; double 64 8. Mention the data structures available in C language. 1. Queue 2. Stack 3. Array (1-dimentional and multi-dimentional) 4. List 5. Tree 6. Binary-tree

DEPARTMENT OF EEE

Page 18

Embedded system
9. Write the syntax for declaration of pointer and Null-pointer. Syntax for pointer: void *portAdata Syntax for Null-pointer: #define NULL (void*) 0x0000 10. Explain pass by values. The values are copied into the arguments of the function. Called programs does not change the values of the variables 11. What are the three conditions that must be satisfied by the re-entrant function? 1. All the arguments pass the values and none of the argument is a pointer. 2. When a non-atomic operation, that function should not operate on the function declared outside. 3. A function does does not call a function by itself when it is not reentrant.

VVCET

12. Explain pass by reference. When an argument value to a function is passed through a pointer, then the value can be changed. New value in the calling function will be returned from the called function 13. Write the syntax for function pointer. Syntax: void *<function_name> (function arguments) 14. Define queue. A structure with a series of elements. Uses FIFO mode. It is used when an element is not directly accessed using pointer and index but only through FIFO. Two pointers are used for insertion and deletion. 15. Define stack. A structure with a series of elements which uses LIFO mode. An element can be pushed only at the top and only one pointer is used for POP. Used when an element is not accessible through pointer and index, but only through LIFO. 16. Define List. Each element has a pointer to its next element. Only the first element is identifiable and it is done using list-top pointer (header). Other element has no direct access and is accessed through the first element. 17. What is Object oriented programming? An object-oriented programming language is used when there is a need for re-usability of defined objects or a set of objects that are common for many applications. 18. What are the advantages of OOPs? Data encapsulation Reusable software components inheritance 19. What are the characteristics of OOPs? An identity reference to a memory block A state data, field and attributes A behavior methods to manipulate the state of the object 20. Define Class. A class declaration defines a new type that links code and data. It is then used to declare objects of that class. Thus a class is an logical abstraction but an object has physical existence. DEPARTMENT OF EEE Page 19

Embedded system
21. Define NULL function NULL defines empty stack or no content in the stack/queue/list.

VVCET

22. What is Multiple Inheritance? Inheritance is the process by which objects of one class acquire the properties of objects of another class. In OOP, the concept of inheritance provides the idea of reusability. 23. Define Exception handling Exceptions are used to report error conditions. Exception handling is built upon three keywords: 1. try 2. catch 3. throw 24. What is a Preprocessor Directive? A preprocessor directive starts with # sign. The following are the types of preprocessor directives: 1. Preprocessor global variables 2. Preprocessor constants 25. Mention the flags available for queue. 1. QerrrorFlag 2. HeaderFlag 3. TrailingFlag 4. cirQuFlag 5. PolyQuFlag 26. Define process. A process is a program that performs a specific function. 27. Define task and Task state. A task is a program that is within a process. It has the following states: 1. Ready 2. Running 3. Blocked 4. Idle 28. Define (TCB) The TCB stands for Task Control Block which holds the control of all the tasks within the block. It has separate stack and program counter for each task. 29. What is a thread? A thread otherwise called a lightweight process (LWP) is a basic unit of CPU utilization, it comprises of a thread id, a program counter, a register set and a stack. It shares with other threads belonging to the same process its code section, data section, and operating system resources such as open files and signals. 30. What are the benefits of multithreaded programming? The benefits of multithreaded programming can be broken down into four major categories: Responsiveness Resource sharing Economy Utilization of multiprocessor architectures

DEPARTMENT OF EEE

Page 20

Embedded system

VVCET

31. Compare user threads and kernel threads. User threads Kernel threads User threads are supported above the kernel and are implemented by a thread library at the user level Kernel threads are supported directly by the operating system Thread creation & scheduling are done in the user space, without kernel intervention. Therefore they are fast to create and manage Thread creation, scheduling and management are done by the operating system. Therefore they are slower to create & manage compared to user threads Blocking system call will cause the entire process to block If the thread performs a blocking system call, the kernel can schedule another thread in the application for execution 32. Define RTOS. A real-time operating system (RTOS) is an operating system that has been developed for real-time applications. It is typically used for embedded applications, such as mobile telephones, industrial robots, or scientific research equipment. 32. Define task and task rates. An RTOS facilitates the creation of real-time systems, but does not guarantee that they are real-time; this requires correct development of the system level software. Nor does an RTOS necessarily have high throughput rather they allow, through specialized scheduling algorithms and deterministic behavior, the guarantee that system deadlines can be met. That is, an RTOS is valued more for how quickly it can respond to an event than for the total amount of work it can do. Key factors in evaluating an RTOS are therefore maximal interrupt and thread latency 33. Define CPU scheduling. CPU scheduling is the process of switching the CPU among various processes. CPU scheduling is the basis of multi-programmed operating systems. By switching the CPU among processes, the operating system can make the computer more productive. 34. Define Synchronization. Message passing can be either blocking or non-blocking. Blocking is considered to be synchronous and non-blocking is considered to be asynchronous. 35. Define Inter process communication. Inter-process communication (IPC) is a set of techniques for the exchange of data among multiple threads in one or more processes. Processes may be running on one or more computers connected by a network. IPC techniques are divided into methods for message passing, synchronization, shared memory, and remote procedure calls (RPC). The method of IPC used may vary based on the bandwidth and latency of communication between the threads, and the type of data being communicated. 36. Define Semaphore. A semaphore S is a synchronization tool which is an integer value that, apart from initialization, is accessed only through two standard atomic operations; wait and signal. Semaphores can be used to deal with the n-process critical section problem. It can be also used to solve various synchronization problems. The classic definition of wait wait (S){ while (S<=0) ; S--; DEPARTMENT OF EEE Page 21

Embedded system

VVCET

Embedded Systems SCT-DEPARTMENT OF ECE } The classic definition of signal signal (S){ S++; } 37. What is a semaphore? Semaphores -- software, blocking, OS assistance solution to the mutual exclusion problem basically a non-negative integer variable that saves the number of wakeup signals sent so they are not lost if the process is not sleeping another interpretation we will see is that the semaphore value represents the number of resources available 38. Give the semaphore related functions. A semaphore enforces mutual exclusion and controls access to the process critical sections. Only one process at a time can call the function fn. SR Program: A Semaphore Prevents the Race Condition. SR Program: A Semaphore Prevents Another Race Condition. 39. When the error will occur when we use the semaphore? i. When the process interchanges the order in which the wait and signal operations on the semaphore mutex. ii. When a process replaces a signal (mutex) with wait (mutex). iii. When a process omits the wait (mutex), or the signal (mutex), or both. 40. Differentiate counting semaphore and binary semaphore. Binary Semaphore: The general-purpose binary semaphore is capable of addressing the requirements of both forms of task coordination: mutual exclusion and synchronization. A binary semaphore can be viewed as a flag that is available (full) or unavailable (empty). Counting semaphores are another means to implement task synchronization and mutual exclusion. Counting Semaphore: The counting semaphore works like the binary semaphore except that it keeps track of the number of times a semaphore is given. Every time a semaphore is given, the count is incremented; every time a semaphore is taken, the count is decremented. When the count reaches zero, a task that tries to take the semaphore is blocked. As with the binary semaphore, if a semaphore is given and a task is blocked, it becomes unblocked. However, unlike the binary semaphore, if a semaphore is given and no tasks are blocked, then the count is incremented. This means that a semaphore that is given twice can be taken twice without blocking. 41. What is priority inheritance? Priority inheritance is a method for eliminating priority inversion problems. Using this programming method, a process scheduling algorithm will increase the priority of a process to the maximum priority of any process waiting for any resource on which the process has a resource lock. 42. Define Message Queue. A message queue is a buffer managed by the operating system. Message queues allow a variable number of messages, each of variable length, to be queued. Tasks and ISRs can

DEPARTMENT OF EEE

Page 22

Embedded system

VVCET

send messages to a message queue, and tasks can receive messages from a message queue (if it is nonempty). Queues can use a FIFO (First In, First Out) policy or it can be based on priorities. Message queues provide an asynchronous communications protocol. 43. Define Mailbox and Pipe. A mailboxes are software-engineering components used for interprocess communication, or for inter-thread communication within the same process. A mailbox is a combination of a semaphore and a message queue (or pipe). Message queue is same as pipe with the only difference that pipe is byte oriented while queue can be of any size. 44. Define Socket. A socket is an endpoint for communications between tasks; data is sent from one socket to another. 45. Define Remote Procedure Call. Remote Procedure Calls (RPC) is a facility that allows a process on one machine to call a procedure that is executed by another process on either the same machine or a remote machine. Internally, RPC uses sockets as the underlying communication mechanism. Other Important Questions 46. Define thread cancellation & target thread. The thread cancellation is the task of terminating a thread before it has completed. A thread that is to be cancelled is often referred to as the target thread. For example, if multiple threads are concurrently searching through a database and one thread returns the result, the remaining threads might be cancelled. 47. What are the different ways in which a thread can be cancelled? Cancellation of a target thread may occur in two different scenarios: Asynchronous cancellation: One thread immediately terminates the target thread is called asynchronous cancellation. Deferred cancellation: The target thread can periodically check if it should terminate, allowing the target thread an opportunity to terminate itself in an orderly fashion. 48. What is preemptive and non-preemptive scheduling? Under non-preemptive scheduling once the CPU has been allocated to a process, the process keeps the CPU until it releases the CPU either by terminating or switching to the waiting state. Preemptive scheduling can preempt a process which is utilizing the CPU in between its execution and give the CPU to another process. 49. What is a Dispatcher? The dispatcher is the module that gives control of the CPU to the process selected by the short-term scheduler. This function involves: Switching context Switching to user mode Jumping to the proper location in the user program to restart that program. 50. What is dispatch latency? The time taken by the dispatcher to stop one process and start another running is known as dispatch latency. 51. What are the various scheduling criteria for CPU scheduling? The various scheduling criteria are DEPARTMENT OF EEE Page 23

Embedded system
CPU utilization Throughput Turnaround time Waiting time Response time

VVCET

52. Define throughput? Throughput in CPU scheduling is the number of processes that are completed per unit time. For long processes, this rate may be one process per hour; for short transactions, throughput might be 10 processes per second. 53. What is turnaround time? Turnaround time is the interval from the time of submission to the time of completion of a process. It is the sum of the periods spent waiting to get into memory, waiting in the ready queue, executing on the CPU, and doing I/O. 54. Define race condition. When several process access and manipulate same data concurrently, then the outcome of the execution depends on particular order in which the access takes place is called race condition. To avoid race condition, only one process at a time can manipulate the shared variable. 55. What is critical section problem? Consider a system consists of n processes. Each process has segment of code called a critical section, in which the process may be changing common variables, updating a table, writing a file. When one process is executing in its critical section, no other process can allowed executing in its critical section. 56. What are the requirements that a solution to the critical section problem must satisfy? The three requirements are Mutual exclusion Progress Bounded waiting 57. Define deadlock. A process requests resources; if the resources are not available at that time, the process enters a wait state. Waiting processes may never again change state, because the resources they have requested are held by other waiting processes. This situation is called a deadlock. 58. What are conditions under which a deadlock situation may arise? A deadlock situation can arise if the following four conditions hold simultaneously in a system: 1. Mutual exclusionA deadlock situation can arise if the following four conditions hold simultaneously in a system: 1. Mutual exclusion 2. Hold and wait 3. No pre-emption 4. Circular wait 59. What are the various shared data operating system services? explain how operating systems provide abstraction from the computer hardware. describe the meaning of processes, threads and scheduling in a multitasking operating system. describe the role of memory management explaining the terms memory swapping, memory paging, and virtual memory. DEPARTMENT OF EEE Page 24

Embedded system

VVCET

contrast the way that MS-DOS and unix implement file systems compare the design of some real operating systems. 60. Define Action plan A plan for action of the development process 61. Define Assembler A tool for assembling the edited codes in mnemonics 62. What is Big Endian & Little Endian An order in which the highest byte of a number is taken first-big endian An order in which the lowest byte of a number is taken first-low endian 63. Define ICE An emulator of microprocessor of target circuit, such that a host system connects to the ICE through serial link for debugging purpose and emulating various versions of a microcontroller family during development phase using remaining part of the target circuit.

DEPARTMENT OF EEE

Page 25