DLL Design Examples, Design Issues - Tips

IC Design Education Center
Delay-Locked Loop
- Design Examples, Design Issues/Tips
Changsik Yoo @ DRAM Design 4, Samsung Electronics
Agenda
Introduction Building blocks of DLL Design issues of DLL DLL examples Design examples
DLL for DDR SDRAM DLL for direct RDRAM
Summary
Why DLL in DRAM?

tAC
Clock @ Transmitter DOUT @ Transmitter
tF
tCC > tAC + tF +tS tCC : clock period tAC : clock to DOUT delay tF : data flight time tS : data setup time
Clock @ Receiver DIN @ Receiver
tS
SDRAM system timing
tAC, tF and tS should be minimum.

Delay to be compensated tAC Clock buffer & data output buffer tS Data input buffer & clock buffer PLL & DLL can do this job.
Changsik Yoo @ DRAM Design 4, Samsung Electronics 3
Is DLL better than PLL for DRAM?

Yes !!!
Frequency multiplication is not necessary. There is no jitter accumulation in DLL. DLL is a first-order system.
- Inherently stable - Parasitic pole due to the feedback delay exists and thus the stability should be considered as well.
PLL & DLL Loop Topologies
PLL
Second-order system Phase alignment by VCO
DLL
First-order system Phase alignment by VCDL
Transient Response to Supply Step

Ref. IEEE Micro98
Jitter of VCO accumulates until the loop feedbacks correcting action takes effect. VCDL in DLL ; no jitter accumulation
6
Delay Locked Loop

d1 Ext. Clock tCC - (d1 + d2) d1 + d2 Compensation Delay
Variable Delay Line
PD
LPF
Ext. Data
DOUT Buffer
Int. Clock
Data from Array d2
Agenda
Summary
Variable Delay Line Schemes - 1

Variable unit delay
min max
- Conventional
Variable number of delay stages

min max
- Digital DLL (SMD, HPLD )
Variable number of delay stages & variable unit delay

coarse fine
- SEC DDR SDRAM

9
Variable Delay Line Schemes - 2

Variable unit delay
Simple control. Limited locking range due to stuck/harmonic-lock problem.
Variable number of delay stages

Fast locking and/or fast standby-mode exit. For wide locking range, large silicon area is required. Inherently large skew (resolution = fixed unit delay).
Variable number of delay stages & variable unit delay

Wide locking range. Complex control.
10
Compensation Delay
Compensation delay
Sum of the delays of input clock buffer, data buffer, and internal clock buffer.
Loading and bias differences between original buffers and replica buffers.
Compensation delay cannot be exactly the same as the original delay. Fuse/metal options for post-tuning.
11
Wafer Level Comp. Delay Control

Hitachi, SOVC00
Ext.
12
Delay Cell
Single-ended delay cell
Simple Dynamic power only (no static current)
Differential delay cell

Complex biasing Static power consumption Immune to supply noise and thus smaller jitter
Variables for delay control

Current Capacitance Resistance Voltage swing
13
Single-Ended Delay Cell
Vctrl
Variable loading capacitance
Vctrl
Pull-down strength control
14
Differential Delay Cell

Vctrl
Vlow
Replica biasing ensures constant voltage swing independent of control voltage.

Phase Detector - D F/F

CLK1 CLK2 CLK1 CLK2 Up CLK1 CLK2 Down D Q Up Down
D F/F can be used as a phase detector. Bang-bang jitter. Uncertainty window as large as set-up/hold window of D F/F.
Phase Detector - PFD

Reset D Q A Reset D Q B A B Up Dn A B Up Dn A B Up Dn Dn B Up B Up=0 Dn=1 A Up=0 Dn=0 B Up=1 Dn=0 A A
17
Direct Phase Comparison

Hitachi, SOVC00
External clock is directly compared with the replica clock. No need for replica input clock buffer. Slew rate independent skew control.
Charge Pump
In analog DLL, PD output is converted to charge by charge pump. Charge pump output is low-pass filtered by a capacitor.
19
Loop Filter
In conventional analog DLL, a capacitor is sufficient. For fast standby-mode exit, locking information can be stored in a digital code.
In digitally controlled DLL, a digital low-pass filter is necessary. Feedback delay should be considered when designing the digital low-pass filter.
20
Agenda
Summary
21
Delay Range Problem of DLL - 1

tD = delay from Ref-CLK to DLL-CLK tCC = clock period tVCDL_max = max. delay of VCDL tVCDL_min = min. delay of VCDL
DLL cannot distinguish between tD= & tD=tCC+.

Delay Range Problem of DLL - 2

To prevent stuck/harmonic-lock problem, the following relationship should be ensured.
0.5 x tCC < tVCDL_min < tCC, tCC < tVCDL_max < 1.5 x tCC Max ( tVCDL_min, 2/3 x tVCDL_max ) < tCC < Min ( 2 x tVCDL_min, tVCDL_max)
Limited locking range.
23
Stuck/Harmonic-Lock Free DLL - 1

For wide locking range, control range of tVCDL should be as large as possible.
for min. tCC for max. tCC
Wide tVCDL range leads to stuck/harmonic-lock problem.
24
Stuck/Harmonic-Lock Free DLL - 2

Initial locking starts with tVCDL_max or tVCDL_min.
If locking starts from tVCDL_min or tVCDL_max, it is clear that tVCDL should be increased/decreased till DLL is locked.
Use a PD which can prevent stuck/harmonic-lock problem. Develop a DLL which can find the stuck/harmoniclock free initial condition.
25
Stuck/Harmonic-Lock Free PD
SEC, ISSCC99
CLK1 - External Clock CLK2 - Internal Clock CLKM - Center-tap of VCDL (a)
(b)
With conventional PD, case (a) and (b) would give the same PD output, and thus stuck/harmonic-lock occurs.
26
Stuck/Harmonic-Lock Free DLL - Ex.

SNU, CICC99
tRDC is settled at 1/8 x tCC by replica delay line.

Stuck/harmonic-free locking range is greatly increased.
27
Locking Time
Closed-loop DLL
Locking time > several hundred clock cycles Conventional DLL with feedback loop
Open-loop DLL
Locking time < several clock cycles Synchronous mirror delay (SMD) type
28
Fast-Lock Technique - Ex. 1

Hitachi, ISSCC98
Fast-lock by successive approximation < 64 cycles Counter-mode operation during normal cycle
29
Fast-Lock Technique - Ex. 1 (contd)
30
Fast-Lock Technique - Ex. 2

d1 d1+d2 Ext.. CLK pclk Dummy Delay(I) Clock Buffer Compare & Latch Flag tCK Unit Delay Meas. Delay Line
Patent Pending, SEC
Voltage Unit Delay PD up down Vcont CP&LPF
Controlled
VDL DLL_Enable
Clock Driver d2 Internal Clock
DLL Block
FB
d1 Dummy Delay(II)
31
DLL Locking Time for DDR SDRAM

In DDR SDRAM, DLL should be locked within 200 cycles after power-up sequence.
Not a hard job. In DDR SDRAM, DLL is necessary only during read cycle. For small standby current, it is desirable to turn off DLL except read cycle which requires DLL to be able to provide stable clock within 4 cycles after turn-on. Initial locking right after power-up need not be faster than 200 cycles. Fast standby-mode exit is the key issue.
32
Agenda
Summary
33
Synchronous Mirror Delay (SMD) - 1

tCC d1 Ext. Clock d1+d2 NEC, ISSCC96
Meas. Delay Line Compare & Transfer Int. Clock Var. Delay Line
d2
tCC-(d1+d2)
Open-loop system ; fast locking < 2 cycles Area penalty for wide freq. range and locking accuracy.
Synchronous Mirror Delay (SMD) - 2

Ext. Clock Input Buffer Meas. Delay Line Var. Delay Line Int. Clock d1 d1+d2 tCC - tCC - d2 (d1+d2) (d1+d2)
2*tCC - (d1+d2)
35
Hierarchical Phase-Locking Delay

~ tCC
CLK BUFF. DELAY d1
SEC, SOVC96
COARSE DELAY STAGE
d1+d2
~ tCC - (d1 + d2)
CLK
TDS
C1
C2
C3
DELAY ELEMENT
C4
COMPARATOR
Cm-1
COARSE DELAY ELEM. (~1ns) Cm
Dm PCLK D1 D2 D3 D4
SWITCH
F1
F2
F3
F4
Fn-1
Fn
FINE DELAY ELEM. (~0.2ns)
G1
G2
G3
G4
FINE DELAY STAGE
Gn
PCLK_HPLD
CLK DRIVER DELAY d2
TUNING
Number of Delay Stage @ 50MHz (tCC=20ns)

CONVENTIONAL
(DELAY ELEM. 0.2ns)
20ns / 0.2ns = 100 (stage) 20ns / 1ns + 1ns / 0.2ns = 25 (stage)
HIERARCHICAL
(COARSE DELAY ELEM. : 1ns FINE DELAY ELEM. : 0.2ns)
36
Bi-Directional Delay (BDD)

NEC, ISSCC99
Open-loop system ;
Fast locking < 2 cycles
High resolution Area penalty

Register Controlled DLL - 1

Fujitsu, ISSCC97,98
Delay step size is too large.
38
Register Controlled DLL - 2

Fujitsu, ISSCC97,98
Locking information is stored as a digital code.

Fast standby-mode exit
High resolution thanks to vernier type delay line.

Loop Configurations of DLL

Initial lock 180 64M DDR 128M DDR A B C D RAMBUS E None Variable Variable Variable Variable Variable Coarse None no. of stages no. of stages no. of stages Fine unit delay unit delay unit delay unit delay 180 None Fixed Fixed Fixed Fixed Variable (dual loop) Active lock Coarse None Fixed Fixed Variable (dual VDL) Variable Variable Fine Variable Variable Variable (partial) Variable (partial) Variable Variable Variable Variable
no. of stages interpolation no. of stages unit delay interpolation unit delay
Unit delay + Selection (Reference loop) Unit delay + Selection (Reference loop)
Variable Fixed Variable (dual VDL)
40
Agenda
Summary
41
DLL for DDR SDRAM

Wide locking range
tCC ; 6ns ~ 15ns
Jitter specification is not tough.

tAC, tDQSCK ; +/-0.75ns tDQSQ ; +/-0.5ns @ tCC = 7.5ns But, most of the jitter comes from SSO noise of DOUT buffer and thus the DLL jitter should be minimized.
Locking time < 200 cycles Power consumption < 20mA

As small as possible
42
Hybrid DLL for DDR SDRAM - 1

SEC, ISSCC99
43

Coarse locking + Fine locking = Wide freq. range
tCC-(t1+t2)-
Coarse locking finds the optimum number of delay cells for the specific tCC. Fine locking controls the skew to be < several 10ps.
tCC-(t1+t2)
44
45

CAS
DQS
~ 420ps Preamble Most of the jitter comes from SSO noise of VDDQ/VSSQ. (not from DLL)
46
DLL for Direct RAMBUS DRAM - 1

Direct RDRAM channel structure
Source synchronous data transmission
Rx clock Controller CTM RDRAM CFM Tx clock CFM CTM
Tx/Rx on both edges of clock Tx is in quadrature
47
DLL for Direct RAMBUS DRAM - 2

DLL purpose
On-chip buffer delay compensation. Quadrature phase generation for transmission clock.
@ RDRAM CFM Rx data CTM Tx data Phase relationship between CTM and CFM varies with channel location.
48
DLL Operation in RDRAM

Reference loop
Multi-phase clock generation. Locking information is stored as a digital code which is converted to analog quantity by a D/A converter. Reference loop is shared by Rx/Tx fine loops.
Rx/Tx fine loop

Locking information is stored as a digital code which controls the phase mixer.
Major locking information is stored as a digital code and thus fast standby-mode exit.
49
Rx Clock Generation in RDRAM

CTM is used as the clock source because it is closer to the external clock source than CFM.
RAMBUS Proprietary
50
Tx Clock Generation in RDRAM
Compensation delay
RAMBUS Proprietary
51
90 Phase Generation
RAMBUS Proprietary
52
Phase Mixing
Similar to variable delay element. Mixes two 45o spaced signals. Mixing weight is controlled by IK1 and IK2.
RAMBUS Proprietary
53
Duty Cycle Correction

For maximum valid data window DCC information is stored in a loop capacitor.
If tHigh = tLow, control voltage is stabilized.

RAMBUS Proprietary
54
Agenda
Summary
55
Summary
DLL should be designed considering the system requirement.
Locking time Power consumption Standby-mode exit Area
56

DLL Design Examples, Design Issues - Tips

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

DLL Design Examples, Design Issues - Tips

Uploaded by

Copyright:

Available Formats

IC Design Education Center

Changsik Yoo @ DRAM Design 4, Samsung Electronics

Changsik Yoo @ DRAM Design 4, Samsung Electronics

Why DLL in DRAM?

Clock @ Receiver DIN @ Receiver

SDRAM system timing

tAC, tF and tS should be minimum.

Is DLL better than PLL for DRAM?

Changsik Yoo @ DRAM Design 4, Samsung Electronics

PLL & DLL Loop Topologies

Changsik Yoo @ DRAM Design 4, Samsung Electronics

Transient Response to Supply Step

Changsik Yoo @ DRAM Design 4, Samsung Electronics

Delay Locked Loop

Variable Delay Line

Data from Array d2

Changsik Yoo @ DRAM Design 4, Samsung Electronics

Changsik Yoo @ DRAM Design 4, Samsung Electronics

Variable Delay Line Schemes - 1

Variable number of delay stages

Variable number of delay stages & variable unit delay

- SEC DDR SDRAM

Variable Delay Line Schemes - 2

Variable number of delay stages

Variable number of delay stages & variable unit delay

Changsik Yoo @ DRAM Design 4, Samsung Electronics

Changsik Yoo @ DRAM Design 4, Samsung Electronics

Wafer Level Comp. Delay Control

Changsik Yoo @ DRAM Design 4, Samsung Electronics

Differential delay cell

Variables for delay control

Changsik Yoo @ DRAM Design 4, Samsung Electronics

Single-Ended Delay Cell

Variable loading capacitance

Pull-down strength control

Changsik Yoo @ DRAM Design 4, Samsung Electronics

Differential Delay Cell

Replica biasing ensures constant voltage swing independent of control voltage.

Phase Detector - D F/F

Phase Detector - PFD

Changsik Yoo @ DRAM Design 4, Samsung Electronics

Direct Phase Comparison

Changsik Yoo @ DRAM Design 4, Samsung Electronics

Changsik Yoo @ DRAM Design 4, Samsung Electronics

Changsik Yoo @ DRAM Design 4, Samsung Electronics

Delay Range Problem of DLL - 1

DLL cannot distinguish between tD= & tD=tCC+.

Delay Range Problem of DLL - 2

Limited locking range.

Changsik Yoo @ DRAM Design 4, Samsung Electronics

Stuck/Harmonic-Lock Free DLL - 1

Wide tVCDL range leads to stuck/harmonic-lock problem.

Changsik Yoo @ DRAM Design 4, Samsung Electronics

Stuck/Harmonic-Lock Free DLL - 2

Changsik Yoo @ DRAM Design 4, Samsung Electronics

Changsik Yoo @ DRAM Design 4, Samsung Electronics

Stuck/Harmonic-Lock Free DLL - Ex.

tRDC is settled at 1/8 x tCC by replica delay line.

Changsik Yoo @ DRAM Design 4, Samsung Electronics

Changsik Yoo @ DRAM Design 4, Samsung Electronics

Fast-Lock Technique - Ex. 1

Changsik Yoo @ DRAM Design 4, Samsung Electronics