MIPS + Cache Practice Questions Question 1 1. Describe how the lw and sw instructions work on the MIPS. 2.

On MIPS, how are constants loaded into registers? 3. Suppose you have two values stored in memory at locations 0x40000010 and 0x40000014 and you want to add the two numbers and write the result in location 0x40000020, write the shortest sequence of MIPS instructions to do this. Question 2 1. What is an instruction pipeline and how does it enhance the performance of processor. 2. What are pipeline stalls and what causes them on the MIPS processor? You should provide examples where possible. 3. The MIPS processor has data-forwarding between arithmetic instructions. What is dataforwarding, how does it work on the MIPS and what makes it possible. 4. Discuss the difference (if any) between RISC and CISC style processors. Question 3 1. Write down the machine language (i.e. binary) version of lw $15, 160($7) 2. What control signal settings are needed to execute a beq instruction? 3. How can constants be loaded into MIPS registers? 4. Suppose you have two values stored in memory at locations 0x40000010 and 0x40000014 and you want to add the two numbers and write the result in location 0x40000020, write the shortest sequence of MIPS instructions to do this. Question 4 Find all data dependencies in the following instruction sequence. For every data dependence, identify its type, the instructions involved, and the dependence location. I1: lw $1,40($2) I2: add $2,$3,$3 I3: add $1,$1,$2 I4: sw $1,20($2) Question 5 Identify all of the RAW data dependencies in the following code. Which dependencies are data hazards that will be resolved by forwarding? Which dependencies are data hazards that will cause a stall? I1: add $3, $4, $2 I2: sub $5, $3, $1 I3: lw $6, 200($3) I4: add $7, $3, $6

Question 6 Recall that the AMAT for a cache is dened as AMAT = hit time + miss rate miss penalty The hit time is the time to access memory when we have a cache hit. When we have a cache miss, the time to access memory (the miss time) equals hit time + miss penalty. Thus, we can also view AMAT as: AMAT = hit rate hit time + miss rate miss time Find the AMAT for a cache with: Cache access time (Hit time) of 1 cycle = 2 ns Miss penalty of 20 clock cycles Miss rate of 0.05 per access Question 7 A multilevel cache has the following features: Miss RateL1 = 4%, Miss RateL2 = 25% Hit time of L1 cache is 1 cycle and of L2 cache is 10 cycles Miss penalty from L2 cache to memory is 100 cycles Memory access per instruction = 1.25 (25% data accesses) Compute AMAT and memory stall cycles per instruction. Question 8 Consider a processor with a 2 ns clock cycle, a miss penalty of 20 clock cycles, a miss rate of 0.05 misses per instruction, and a cache access time (hit time) of 1 clock cycle. Assume that the read and write miss penalties are the same. i. Find the average memory access time (AMAT). ii. Suppose we can improve the miss rate to 0.03 misses per instruction by doubling the cache size. However, this causes the cache access time to increase to 1.2 cycles. Using the AMAT as a metric, determine if this is a good trade-off.