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C S D A 2/e
Difference between hardwired control unit and microprogrammed control unit Microprogram Microinstruction Macroinstruction Control store and micro-branching Horizontal and vertical microprogramming
C S D A 2/e
Important Trends/Concepts that Led to Microprogramming 1940s Stored program computers Program instructions can be stored in memory along with data and can be manipulated like data 1947 MIT Whirlwind real-time flight simulator control store two-dimensional lattice rows time sequence columns control signals
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MIT Whirlwind
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Signal Generator
Computer Systems Design and Architecture Second Edition 2004 Prentice Hall
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C S D A 2/e
1970s
Complex instruction sets
Trend towards instruction sets very similar to high-level languages
C S Important Trends that Led to Microprogramming D A 2/e Control logic design Complex and error-prone Need a simpler method of developing the control logic for a computer Writing a program
Simpler than designing the logic Easier to change
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Recall control sequence for 1-bus SRC Concrete RTN MA PC: C PC+4; MD M[MA]: PC C; IR MD; A R[rb]; C A + R[rc]; R[ra] C; Control Sequence PCout, MAin, Inc4, Cin, Read Cout, PCin, Wait MDout, IRin Grb, Rout, Ain Grc, Rout, ADD, Cin Cout, Gra, Rin, End
Computer-aided design tools have improved Yes, but benefits need to be weighed against costs: Complex ISAs such as IA-32 sometimes have more complex instructions implemented as microprograms. Pentium, Pentium 4, special-purpose processors, etc.
Computer Systems Design and Architecture Second Edition 2004 Prentice Hall
Control unit job is to generate the sequence of control signals How about building a computer to do this?
Computer Systems Design and Architecture Second Edition 2004 Prentice Hall
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1. 2. 3. 4.
Microprogramming Process Develop microinstruction set Write microprogram Microassemble microprogram Place the microassembled program (microcode) onto PLA or ROM
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A control store word, or microinstruction, contains a bit pattern telling which control signals are true in a specific step The major issue is sequencing
What order to read instructions?
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What Goes in a Microinstruction? Designing the Microinstruction set How many fields?
What does each field represent?
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What control signals are controlled by each field? How will sequencing (next microinstruction to execute) be determined?
Microinstruction has branch control, branch address, and control signal fields Micro-program counter can be set from several sources to do the required sequencing
1. 2.
3.
Next sequential Start address of next macro inst Microinst specified address
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Contents of a Microinstruction
f ormat
Branch address
Cont rol
signals E n d
Main component is list of 1/0 control signal values There is a branch address in the control store There are branch control bits to determine when to use the branch address and when to use PC+1
P o C u M ti A n P i C n Co u t Ai n
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a1 Microaddress a2
Code for br
a3
Common inst. fetch sequence Separate sequences for each (macro) instruction Wide words
232
2n-1
m bits wide k branch control bits c control signals n branch addr. bits
1024 16
1
Computer Systems Design and Architecture Second Edition 2004 Prentice Hall Computer Systems Design and Architecture Second Edition 2004 Prentice Hall
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1 0 0 0 0 0
0 1 0 0 0 1
0 0 1 0 0 0
0 0 0 1 1 0
1 0 0 0 0 0
1 0 0 0 1 0
0 1 0 0 0 0
0 0 1 0 0 0
0 0 0 1 0 0
0 0 0 0 0 1
1 0 0 0 0 0
1 0 0 0 0 0
0 1 0 0 0 0
0 0 0 0 1 0
0 0 0 0 0 1
0 0 0 1 0 0
0 0 0 0 1 0
0 0 0 0 0 1
Addresses 101103 are the instruction fetch Addresses 200202 do the add Change of control from 103 to 200 uses a kind of branch
1) Branch to start of code for a specific inst. 2) Conditional control signals, e.g. CON PCin 3) Looping on conditions, e.g. n0 ... Goto6 Conditions will control branches instead of being ANDed with control signals Microbranches are frequent and control store addresses are short, so it is reasonable to have a branch address field in every instruction
C Fig 5.24 Branching Controls in the Microcoded S Control Unit D A Z N Sequencer 2/e PLA
2 2 2 2 2 Incr. PC Branch address 2 41 Mux External address
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5 branch conditions
NotN N NotZ Z Uncondit. 00 01 10 11 11 11 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0
Co nt r o l Si g n al s 0 0
Branching
act ion
Nonenext inst ruct ion Branch t o out put of PLA Br if Z t o Ext ern. Addr. Br if N t o 3 0 0 ( else next ) Br if N t o 2 0 6 ( else next ) Br t o 2 0 4
Control store
Control signals
24410
To 1 of 4 places
Next inst. PLA Extern. addr. Branch addr.
Mux Ctl 00 01 10 11
If the control signals are all zero, the inst. only does a test Otherwise test is combined with data path activity
In horizontal microcode, each control signal is represented by a bit in the instruction Fewer control store words of more bits per word In vertical microcode, a set of true control signals is represented by a shorter code
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Vertical code only allows RTs in a step for which there is a vertical instruction code Thus vertical code may take more control store words of fewer bits
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PC
n to 2n decoder
A set of m such signals can be encoded using log2m bits (log2(m+1) to allow for no signal true) The raw control signals can then be generated by a k to 2k decoder, where 2k m (or 2k m+1) This is a compromise between horizontal and vertical encoding
Cin
Inc4
MAin
PCout
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Addr. 100 101 102 200 201 202
Using the 1-bus SRC data path design gives a specific set of control signals There are no condition codes, but data path signals CON and n=0 will need to be tested We will use branches BrCON, Brn=0, & Brn0 We adopt the clocking logic of Fig. 4.9 on p. 4-20 Logic for exception and reset signals is added to the microcode sequencer logic Exception and reset are assumed to have been synchronized to the clock
Microbranching to the output of the PLA is shown at 102 Microbranch to 100 at 202 starts next fetch
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Bus
P 5
So that the input to the PLA is correct for the branch in 102, it has to come from MD, not IR An alternative is to use see-thru latches for IR so the op code can pass through IR to PLA before the end of the clock cycle
D 5
PLA
R 10
PC9 ..0
Cl
Data must have time to get from MD across Bus, through IR, through the PLA, and satisfy PC set up time before trailing edge of S
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CON
n=0
Exception
F9 Branch address
1 0 bit s
Mux Ct l
00 01 10 11
Out In End s ig n al s s ig n al s
41 Mux
PC n
0 00 BrUn 0 Cont . 0 0 0 PCout 0 01 BrCON 1 End 0 0 1 C out 0 10 BrCON 0 1 0 MDout 0 11 Br n=0 0 1 1 Rout 1 00 Br n0 1 0 0 BA out 1 01 None 1 0 1 c1 out 1 1 0 c2 out 3 bit s 1 bit 1 1 1 None 3 bit s
Read 0 0 Gra Wait 0 1 Grb Ld 1 0 Grc Decr 1 1 None CONin Cin St op None 2 bit s
21 Mux
2 b it s
3 bit s
1 0 bit s
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Multi-way branches: often an instruction can have 4-8 cases, say address modes
Could take 2-3 successive branches, i.e. clock pulses The bits selecting the case can be ORed into the branch address of the instruction to get a several way branch Say if 2 bits were ORed into the 3rd & 4th bits from the low end, 4 possible addresses ending in 0000, 0100, 1000, and 1100 would be generated as branch targets Advantage is a multi-way branch in one clock
A hardware push-down stack for the PC can turn repeated sequences into subroutines Vertical code can be implemented using a horizontal engine, sometimes called nanocode
Computer Systems Design and Architecture Second Edition 2004 Prentice Hall
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