FACULTY OF ELECTRICAL ENGINEERING UNIVERSITI TEKNOLOGI MALAYSIA

MEL 1173 ADVANCED DIGITAL SYSTEM DESIGN

ASSIGNMENT 1: (TEST FAULT PROGRAMMING)

PREPARED BY: Sinan S. Mohammed Sheet

INSTRUCTORS: DR. Ooi Chia Yee

ABSTRACT

Testing techniques for VLSI circuits are today facing many exciting and complex challenges. In the era of large systems embedded in a single system-on-chip (SOC) and fabricated in continuously shrinking technologies, it is important to ensure correct behavior of the whole system. This report presented a fault simulation Technique via two of fault models that are serial and parallel models. In addition, fault simulation typically used to evaluate the fault coverage obtained by that set of test vectors. The process start with input test pattern to two circuits correct and faulty, at same time inject single fault by time. So each time single fault had injected, new faulty circuit was been presented. The simulation result of correct and faulty circuits were compared, if the result was zero mean the fault didnt detect while when it 1 meaning fault detected. In order to get correct fault coverage a scan loop added to search for repeated or duplicate discovered faults to keep first copy and erase other copies. Finally, results show that using parallel technique gave better results compare to serial algorithm. It approved that the fault coverage percentage and simulation speed were higher.

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1.0

Introduction

Fault models are necessary for generating and evaluating a set of test vectors because of the diversity of VLSI defects, it is difficult to generate tests for real defects. Generally, a good fault model should satisfy two criteria: (1) It should accurately reflect the behavior of defects, and (2) it should be computationally efficient in terms of fault simulation and test pattern generation. Many fault models have been proposed [Abramovici 1994], but, unfortunately, no single fault model accurately reflects the behavior of all possible defects that can occur. For a given fault model there will be k different types of faults that can occur at each potential fault site (k = 2 for most fault models). A given circuit contains n possible fault sites, depending on the fault model. Assuming that there can be only one fault in the circuit, then the total number of possible single faults, referred to as the single-fault model or single-fault assumption, is given by:

Number of single faults = kn

Because there are many faults to follow for fault detection analysis, fault simulation time is much greater than that required for design verification. To accelerate the fault simulation process, improved approaches have been developed in the following order. Parallel fault simulation uses bit-parallelism of logical operations in a digital computer. Thus, for a 32-bit machine, 31 faults are simulated simultaneously. 2.0 Objectives In this work there are two jops as shown below:
 Develop a fault simulator using programming language C++.

 Determine fault coverage by the fault simulator.

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3.0

Specification
Design a simple combinational circuit which is composed of 10 gates and 3 inputs to be

used to exhibit the fault simulator.

4.0

Methodology
Fault simulation method used Fault simulation algorithms Serial and Parallel. The

flowchart below explains a step-by-step solution to a given problem and it represented serial algorithm. Start Open Test & faults text file Input test pattern for both faulty and correct circuits Simulate correct circuit

Inject fault

Simulate faulty circuit Increment total fault counter

Compare the results of faulty and correct circuits 0

No >324 Yes Printout results

Fault detected 1 Store detected fault Increment detected fault counter

Update detected fault counter Delete equivalent faults

Figure 4.1 Flowchart of representing serial algorithm by c++

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Figure 4.2 Fault simulation concept In order to discover the different between serial and parallel algorithm, a module represented a parallel algorithm have been built and next flowchart explain the solving the problem by this algorithm. A word width w= 55, where the w represent 54 fault plus one which is fault free simulation.

Start

Open text file

Read test pattern and fault Increment fault counter

Input test pattern and in inject fault in parallel

Store detected fault Simulate circuit

Compare among first bit output and others

1 Printout results

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5.0

C++ Codes 5.1 Serial algorithm see appendix A. Test pattern and faults type that the software input and inject it are stored at text file called Test pattern which can be seen at appendix B. 5.2 parallel algorithm see appendix C. Test pattern and faults type that the software input and inject it are stored at text file called myfile which can be seen at appendix D.

6.0

Circuit-under-test

Figure 6.1 shows a logical circuit consist of ten logic gates that are 7 And gates and 3 or gates, this circuit had been used in as circuit under test.

Figure 6.1 Logic circuit under test 7.0 Result and Analysis 7.1 Serial Algorithm:

Figure 7.1 Simulation result of Tester software that represented serial algorithm 6|P ag e

In figure 7.1 it can be seen that the tester model discover 15 faults among total 54 faults the total fault number is equal to total faults number that had been found by theoretical calculation as shown below: Total fault = # of inputs+ # of logic gates+ # fanout branches T.f.= 3+10+14= 27 , so for k*2 27*2=54 faults

7.2 Parallel Algorithm:

Figure 7.2 Simulation result of Tester software that represented parallel algorithm Figure 7.2 shows that using parallel algorithm concept made the number of detected fault increase and became 49. As well, the percentage of fault coverage became better around 91% .

7.3 Time comparison: In order to find the difference in time simulation of both algorithms, the extra parts in both software models are commented. So it capable to see that the simulation time for parallel algorithm shorter equal to 8 msec, while for serial 21 msec as shown in figures below.

Figure 7.3 serial algorithm 7|P ag e

Figure 7.3 parallel algorithm

8.0

Conclusion

The results obtained are functioning according to the design requirement, and according to timing analysis that represent real time simulation, the serial algorithm tester has long delay time than tester that use parallel algorithm. In addition, the percentage of fault coverage improved with using parallel algorithm concept too.

References [1] Laung-Terng Wang, C.-W. W. (2006). VLSI Test principles and artchitectures. Elsevier. [2] Michael L. Bushnell, V. D. (2000). Essentials Of Electronic Testing. Kluwer Academic Publishing.

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Appendices Appendix A

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Appendix B Part of Test pattern .text file that had been used with serial algorithm contain faults and T.p.
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A0 A1 a10 a11 a20 a21 B0 B1 b10 b11 b20 b21 C0 C1 c10 c11 c20 c21 d0 d1 d10 d11 d20 d21 e0 e1 e10 e11 e20 e21 k0 k1 k10 k11 k20 k21 l0 l1 l10 l11 l20 l21 m0 m1 n0 n1 n10 n11 n20 n21 j0 j1 h0 h1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A0 A1 a10 a11 a20 a21 B0 B1 b10 b11 b20 b21 C0 C1 c10 c11 c20 c21 d0 d1 d10 d11 d20 d21 e0 e1 e10 e11 e20 e21 k0 k1 k10 k11 k20 k21 l0 l1 l10 l11 l20 l21 m0 m1 n0 n1 n10 n11 n20 n21 j0 j1 h0 h1

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Appendix C

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Appendix D Below is the myfile.text file that had been used with parrallel algorithm contain faults and T.p.
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A0 A1 a10 a11 a20 a21 B0 B1 b10 b11 b20 b21 C0 C1 c10 c11 c20 c21 d0 d1 d10 d11 d20 d21 e0 e1 e10 e11 e20 e21 k0 k1 k10 k11 k20 k21 l0 l1 l10 l11 l20 l21 m0 m1 n0 n1 n10 n11 n20 n21 j0 j1 h0 h1

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