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CD4020BC CD4040BC CD4060BC 14-Stage Ripple Carry Binary Counters 12-Stage Ripple Carry Binary Counters 14-Stage Ripple Carry Binary Counters
General Description
The CD4020BC, CD4060BC are 14-stage ripple carry binary counters, and the CD4040BC is a 12-stage ripple carry binary counter. The counters are advanced one count on the negative transition of each clock pulse. The counters are reset to the zero state by a logical 1 at the reset input independent of clock.
Features
s Wide supply voltage range: s High noise immunity: 1.0V to 15V 0.45 VDD (typ.) s Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS s Medium speed operation: 8 MHz typ. at VDD = 10V s Schmitt trigger clock input
Ordering Code:
Order Number CD4020BCM CD4020BCN CD4040BCM CD4040BCSJ CD4040BCN CD4060BCM CD4060BCN Package Number M16A N16E M16A M16D N16E M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.
Connection Diagrams
Pin Assignments for DIP and SOIC CD4020BC Pin Assignments for DIP, SOIC and SOP CD4040BC
Top View
Top View
DS005953.prf
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Connection Diagrams
Top View
Schematic Diagrams
CD4020BC
CD4040BC
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CD4060BC
Crystal Oscillator
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Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The tables of Recommended Operating Conditions and Electrical Characteristics provide conditions for actual device operation. Note 2: VSS = 0V unless otherwise specified.
Note 3: Data does not apply to oscillator points 0 and 0 of CD4060BC. IOH and IOL are tested one output at a time.
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AC Electrical Characteristics
Symbol tPHL1, tPLH1 Parameter Propagation Delay Time to Q1
(Note 4)
Conditions Min Typ 250 100 75 150 60 45 100 50 40 125 50 40 Max 550 210 150 330 125 90 200 100 80 335 125 100 No Limit No Limit No Limit 1.5 4 5 4 10 12 200 100 80 200 100 80 5 50 450 210 170 450 210 170 7.5 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns ns ns pF pF
CD4020BC, CD4040BC TA = 25C, CL = 50 pF, RL = 200k, tr = tf = 20 ns, unless otherwise noted VDD = 5V VDD = 10V VDD = 15V tPHL, tPLH Interstage Propagation Delay Time from Qn to Qn+1 tTHL, tTLH Transition Time VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V tWL, tWH Minimum Clock Pulse Width VDD = 5V VDD = 10V VDD = 15V trCL, tfCL Maximum Clock Rise and Fall Time VDD = 5V VDD = 10V VDD = 15V fCL Maximum Clock Frequency VDD = 5V VDD = 10V VDD = 15V tPHL(R) Reset Propagation Delay VDD = 5V VDD = 10V VDD = 15V tWH(R) Minimum Reset Pulse Width VDD = 5V VDD = 10V VDD = 15V CIN CPD Average Input Capacitance Power Dissipation Capacitance Any Input
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AC Electrical Characteristics
Symbol tPHL4, tPLH4 Parameter Propagation Delay Time to Q4
(Note 5)
Conditions Min Typ 550 250 200 150 60 45 100 50 40 170 65 50 Max 1300 525 400 330 125 90 200 100 80 500 170 125 No Limit No Limit No Limit 1 3 4 3 8 10 200 100 80 200 100 80 5 50 450 210 170 450 210 170 7.5 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns ns ns pF pF
CD4060BC TA = 25C, CL = 50 pF, RL = 200k, tr = tf = 20 ns, unless otherwise noted VDD = 5V VDD = 10V VDD = 15V tPHL, tPLH Interstage Propagation Delay Time from Qn to Qn+1 tTHL, tTLH Transition Time VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V tWL, tWH Minimum Clock Pulse Width VDD = 5V VDD = 10V VDD = 15V trCL, tfCL Maximum Clock Rise and Fall Time VDD = 5V VDD = 10V VDD = 15V fCL Maximum Clock Frequency VDD = 5V VDD = 10V VDD = 15V tPHL(R) Reset Propagation Delay VDD = 5V VDD = 10V VDD = 15V tWH(R) Minimum Reset Pulse Width VDD = 5V VDD = 10V VDD = 15V CIN CPD Average Input Capacitance Power Dissipation Capacitance Any Input
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16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D
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CD4020BC CD4040BC CD4060BC 14-Stage Ripple Carry Binary Counters 12-Stage Ripple Carry Binary Counters 14-Stage Ripple Carry Binary Counters
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E
LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.