Foundry Design Kit (FDK) User Guide

Copyright UMC, 2007 All information contained herein is subject to change without prior notice. No liability shall be incurred from its use or application.

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Revision History
Version 1.0 1.1 Date 2007/05/16 2007/08/09 Initial Release Revised chapter 1-2 typo on page 20 Description

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Table of Contents
Preface...................................................................................................................................... 4 Setting Up Your Design Environment .................................................................................... 6

Chapter 1. Schematic Entry with Composer .................................................... 8

1-1. Generating Symbol View ........................................................................................... 18 1-2. Simulation in Spectre Using the Virtuoso Analog Design Environment ..................... 20

Chapter 2. Layout with Virtuoso ...................................................................... 31 Chapter 3. Physical Verification ...................................................................... 36

3-1. Assura in GUI Mode .................................................................................................. 36 3-2. Assura in Batch Mode ............................................................................................... 43 3-3. Calibre in GUI Mode .................................................................................................. 50 3-4. Calibre in Batch Mode ............................................................................................... 66

Chapter 4. Post-Layout Simulation ................................................................. 69

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Preface
Under the design environment of foundtry design kit (FDK), the technology file and a fair amount of custom SKILL code have been integrated. FDK contains useful information for analog/mixed-mode, RF, and full-custom CMOS IC designs by the UMC fabrication. It includes the layer definitions (e.g., colors, patterns, etc.), the parasitic capacitances, layout PCells, SPICE simulation parameters, Calibre/Assura rules for design rules check (DRC), RCL extraction (including resistance, capacitance, and inductance), layout verus schematic (LVS) verification, and various enhancement of graphic user interface (GUI). This environment is named as UMC Foundry Design Kit (UMC FDK).

Contents of FDK
Types Cell View Descriptions auCdl, auLvs, hspiceS/D, ivpcell, layout (PCell), spectre, symbol DRC rule file Assura, Calibre; LVS rule file Assura, Calibre; ERC rule support Assura, Calibre; RLC extraction Assura RCX, XRC; Technology File Virtuoso, Virtuoso XL; ICC File Virtuoso XL. Spectre, HSpice CallBack re-trigger, Alphabet Generator User Guide, Application Note, and Release Note

Technology File

SPICE Model Utility Documentation

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Benefits

FDK

1. Provide a total solution about Logic/ Mixed Mode/RF/CMOS Image Sensor/ High Voltage technology for circuit designer 2. Huge enhance productivity

Schematic Entry
1. Symbol Call-back Function 2. Component Description File

Presimulation
1. Simulation Environment 2. SPICE Model 3. Netlist Views 4.Netlist Procedure

Physical Design (Layout)

1. Layout Edit Technology Files 2. Parameterized Cells 3. Auto-router Technology Files 4. Layout Utilities

Physical Verification DRC/LVS/ ERC/RCX

1. DRC/LVS/ERC/ RCX Technology Files 2. LVS Netlist View

Postsimulation

Release as IPs, Standard Library, IO or tape-out.

1. Layout Parasitic Extraction 2. Back-annotation Methodology 3. SPICE Model

To ease the introduction of the FDK design flow, a simple design is used as an example to go through the whole design flow based on the FDK technology. This user guide aims at learning how to run the EDA tools with FDK on your workstation, starting from the schematic capture, the physical verification, and ending at the post-layout simulation. Note that this user guide does not focus on the complete tool usage. For more detailed usage of the related tools, please contact the EDA vendors.

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Setting Up Your Design Environment

Before starting this user guide, several setup files should be installed in your working directory. These files will determine the design environment where the EDA tools run and can be edited to meet personal preference. Please note that this user guide can be adapted in every released UMC FDK document and is written herein as an example for the 90 nm design rules.

1. Set up the working directory First, you need to create a working directory in your personal computer. To do this, type: cd ~ mkdir myDesignDir (e.g.) 2. Choose the working environment for CADENCE Before you start your new design, you need to perform the following steps. (1) Go to the directory of myDesignDir by typing: cd myDesignDir (2) Create setup files (.simrc, cds.lib, display.drf) in the directory by typing: cp /fdkInstallPath/.simrc ./.simrc cp /fdkInstallPath/cds.lib ./cds.lib cp /fdkInstallPath/display.drf ./display.drf

(3) Modify the cds.lib files in the directory. The original cds.lib contents: DEFINE cdsDefTechLib $CDS_INST_DIR/tools/dfII/etc/cdsDefTechLib DEFINE basic $CDS_INST_DIR/tools/dfII/etc/cdslib/basic DEFINE analogLib $CDS_INST_DIR/tools/dfII/etc/cdslib/artist/analogLib DEFINE umc90nm ./umc90nm

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The new cds.lib contents: DEFINE cdsDefTechLib $CDS_INST_DIR/tools/dfII/etc/cdsDefTechLib DEFINE basic $CDS_INST_DIR/tools/dfII/etc/cdslib/basic DEFINE analogLib $CDS_INST_DIR/tools/dfII/etc/cdslib/artist/analogLib DEFINE umc90nm ./umc90nm INCLUDE /fdkInstallPath/cds.lib (The 4th line, DEFINE umc90nm ./umc90nm, needs to be modified to INCLUDE /fdkInstallPath/cds.lib.) After you complete the above-mentioned modification of the new cds.lib, save this cds.lib file. (4) Contact your CAD team and create a configuration file (.cshrc) in your working directory by typing: cp /yourCadTeam/.cshrc ./myCshrc Type ls -a in your working directory, and you will see the files that have been copied there. Add the analog design environment setting in myCshrc by typing: setenv CDS_Netlisting_Mode Analog (5) To use UMC FDK, you need to re-source it in the current terminal window. Type: source myCshrc Several ways can be applied to start the new design with UMC FDK depending on which features are needed.

We will use icfb which is for front-end to back-end design. For starters, type the following command in your working directory: icfb& If you want to quit CADENCE, select File and Exit in the command interface window (CIW). Then, a message window will appear to confirm your command. Select OK to exit.

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Chapter 1. Schematic Entry with Composer

At this stage, you should have the setup files in your working directory for running CADENCE with UMC FDK. Otherwise, please refer to Setting up Your Design Envrionment. We will build the lowest level of library cell, Inverter, as an example.

Design Entry through Schematic Capture

To start CADENCE, type icfb& in the command line, and then you should get the command interface window (CIW) (Figure 1-1).

Figure 1-1. Command interface window (CIW)

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Open Library Manager

Select Tools Library Manager (Figure 1-2).

Figure 1-2. Library Manager

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Creating a New Library

1. Select File New Library in Library Manager.

2. Key in a library name, as shown in Figure 1-3(a). Then, choose Attach to an existing techfile, as shown in Figure 1-3(b).

Figure 1-3(a). Create a new library

Figure 1-3(b). Attach to an existing technology file

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3. Specify Technology Library for umc90nm, as shown in Figure 1-3(c).

Figure 1-3(c). Select the Technology Library

4. Click on OK. Now, the new library of this particular case, MyDesignLib, should be shown in your Library Manager, as shown in Figure 1-4.

Figure 1-4. Library Manager with MyDesignLib library

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Creating a New Schematic

1. Select File view. 2. Key in a name for Cell Name and View Name and choose Composer-Schematic as the tool. View Name should be schematic exactly, as shown in Figure 1-5. New Cell view in Library Manager, and choose the desired library to create in the new cell

Figure 1-5. Create a new cell view 3. Click on OK. A blank Composer-Schematic window will appear.

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Placing Instances on Schematic

To draw the inverter, you need to add PMOS/NMOS transistors, ground, power supply, pins for input and output, and wire them together. To add components to your schematic, please perform the following steps. 1. From the Composer-Schematic window, select Add Instance. This brings out the Add Instance form

(Figure 1-6(a)). Click on Browse, the Library Browser window will appear (Figure 1-6(b)).

Figure 1-6(a). Add an instance

Figure 1-6(b). Browse for components

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2.

To select transistors, click on N_10_SP for the NMOS transistors and P_10_SP for the PMOS transistors. You should have the Add Instance window like the one shown in Figure 1-7.

Figure 1-7. Get NMOS and PMOS devices

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3.

Repeat Step 2 to get power VDD and ground bus by a click on Supply_Nets in Component Browser. The components in Supply_Nets are actually global signals. The pin names for global signals are automatically given. If you make a mistake and need to exit from the Add Instance window, press the Esc key. By now, you should have the schematic as illustrated in Figure 1-8.

Figure 1-8. Create CMOS inverters

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Wiring and Creating Pins

After the instances are created and placed, you can connect them by wires to form the inverter. Please perform the following steps to add wires. 1. 2. From the Composer-Schematic window, select Add Wire (narrow).

Click the left mouse button on the starting point, and click the left mouse button again on the desired transition points. If you want to end adding wires, double click the left mouse button.

After wiring, you need to create pins for input and output nodes, as indicated in the following steps. 1. 2. From the Composer-Schematic window, select Add Pin. Then, an Add Pin form appears.

Create the Pin Names (e.g., A Y, A X, X Y, etc.), and ensure the Direction is input, as shown in Figure1-9.

Figure 1-9. Add Pins

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3. 4.

Move the cursor to the Schematic window. Then, click the left mouse button to place pin A. Move the cursor back to the Add Pin form, and change Direction from input to output. Then, repeat the Step 3.

5. 6.

The completed schematic view of an inverter will be similar to the one illustrated in Figure 1-10. Remember to save the file by selecting Design Check and Save in the Composer-Schematic window.

Figure 1-10. A completed schematic

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1-1. Generating Symbol View

In this section, we are going to create a symbol for inverters to generate a hierarchical schematic at the logic gate level as follows. 1. Select File cell view. 2. Key in a name for Cell Name and View Name and choose Composer-Symbol as the tool. View Name should be symbol exactly, as shown in Figure 1-11. New Cell view in Library Manager, and choose the desired library to create in the new

Figure 1-11. Create a symbol Then, the Symbol Editing window will appear. It allows you to draw any kind of shape to represent you logic gate.

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To import a symbol, please perform the following steps. 1. In the Symbol Editing window, select Add Import Symbol. This brings out the Import Symbol form.

Click on Browse, and select inverter in the sample library. The form should be the same as Figure 1-12.

Figure 1-12. Import Symbol 2. The symbol will be automatically generated in the Symbol Editing window as shown in Figure 1-13.

Figure 1-13. The inverter symbol 3. Remember to save the file by selecting Design Check and Save in the Symbol Editing window.

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1-2. Simulation in Spectre Using the Virtuoso Analog Design Environment

This section explains how to simulate your circuit. In this case of inverter, Virtuoso Analog Design Environment is used.

Creating a Test Bench

To simulate inverters, you need to create a test bench with its cell named as myInv_test in the library of MyDesignLib. An inverter, power supply, input source, and a ground are included in this schematic and will be tested of its transient response. Figure 1-14(a) explains how to create the new file, while Figures 1-14(b) to 1-14(e) demonstrate how to add the symbol of inverter, input source, power supply, and capacitor. Then, repeat the section of Schematic Entry with Composer.

Figure 1-14(a). Create new schematic view

Figure 1-14(b). Add myInv symbol

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Figure 1-14(c). Add input source

Figure 1-14(d). Add power supply

Figure 1-14(e). Add capacitor

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Press the Esc key to exit from the Add Instance Mode, and connect them in wires, as shown in Figure 1-15.

Figure 1-15. The completed test circuit

Remember to save the file by selecting Design

Check and Save in the Composer-Schematic window.

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Simulating Your Circuit with Typical Models

To simulate your circuit in this case of myInv_test, please perform the following steps. 1. In the Composer-Schematic window, select Tools Analog Design Environment window (Figure 1-16). Analog Environment. This brings out the Virtuoso

Figure 1-16. Virtuoso Analog Design Environment 2. In the Virtuoso Analog Design Environment window, select Setup Simulator/Directory/Host. The

Choosing Simulator/Directory/Host window will appear (Figure 1-17). Ensure that the simulator is set to spectre and click on OK.

Figure 1-17. Set up the simulator

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3.

In the Virtuoso Analog Design Environment window, select Setup

Model Path. The Setting Model

Path window will appear. Check the model directories and you will have the same window as Figure 1-18.

Figure 1-18. Set up the model path

4.

In the Virtuoso Analog Design Environment window, select Analyses form as indicated in Figure 1-19.

Choose, and then fill out the

Figure 1-19. Set up transient analysis

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5.

In the Virtuoso Analog Design Environment window, select Outputs

To Be Plotted

Select On

Schematic. Then, go back to the schematic and click on the wires of the inverter input and output. The wires should be selected (Figure 1-20(a)).

Figure 1-20(a). Select analyses points on the schematic

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Press the Esc key to exit from the Selection Mode. The signals should be added in the outputs window, (Figure 1-20(b)).

Figure 1-20(b). Virtuoso Analog Design Environment ready for a simulation

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6.

In the Virtuoso Analog Design Environment window, select Simulation simulation will appear in Waveform Window (Figure 1-21).

Run. Then, the plot of the

Figure 1-21. Simulation result

7.

Remember to save your simulation conditions by selecting Session Analog Design Environment window.

Save State

OK in the Virtuoso

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Simulating Your Circuit with Monte Carlo Models

To run Monte Carlo simulation in this case of myInv_test, please perform the following steps. Also note that when running Monte Carlo simulation, the version of CANDENCE tool should be IC5141 USR3 and/or above. 1. Disable the original model file and then re-load the Monte Carlo model file. Set Section to mc, as shown in Figure 1-22.

Figure 1-22. Set the Monte Carlo model path

2.

Create a variable that named sigma and set its value to 3, as shown in Figure 1-23.

Figure 1-23. Create a variable sigma

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3.

Select Tools

Monte Carlo, as shown in Figure 1-24.

Figure 1-24. Select Tools

Monte Carlo

4.

Complete Analysis Setup (Figure 1-25(a)) and run the Monte Carlo simulation (Figure 1-25(b)).

Figure 1-25(a). Complete Analysis Setup

Figure 1-25(b). Run Monte Carlo simulation

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5.

Please check the statistical analysis results (Figure 1-26).

Figure 1-26. Statistical Analysis Results window

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Chapter 2. Layout with Virtuoso

After a schematic of your design is completed, the next step is to create masks for fabrication by using the layout editor, Virtuoso. The layers in a layout represent the physical characteristics of the devices and have more details than schematics. Therefore, in the design flow of your circuit, verification with layout is critical. We will use PCell developed in UMC to create an inverter layout based on the UMC 90 nm technology. The CADENCE Virtuoso XL design flow will be implemented. This includes basic connectivity of connection layers, wells, substrates, and symbolic contacts. Names will be displayed on the layout views to aid in schematic-layout instance correlation. The auto-abutment devices for MOSFET are supported. Pin permuting of MOSFET and resistor devices is also supported. The skilled PCell layouts are compiled into the FDK. The guidelines listed below may be followed in layout design.

The schematic-driven layout in the Virtuoso XL Environment can be used to obtain the maximum leverage from FDK. This flow will produce a correct design layout.

The CADENCE chip assembly router (CCAR) can be employed to perform the interconnection of the layout. The CCAR rule file for the target process is provided with the FDK.

Notes: a. Skilled PCell source code is not included in the FDK. b. Abutment is currently supported only for MOS transistors. In addition, abutment works only on the schematic-driven layouts.

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To start your layout with Virtuoso, please perform the following steps. 1. 2. Open the schematic view of your design. In the Schematic window, select Tools Design Synthesis Layout XL, as shown in Figure 2-1.

Figure 2-1. Virtuoso XL for the schematic-driven layout

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3.

In the Virtuoso XL Layout window, select Design

Gen from source. The Layout Generation Options

window will appear (Figure 2-2(a)). Then, users need to set up the options in Layout Generation, I/O Pins, and Boundary.

Figure 2-2(a). Layout Generation Options window

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Click on OK. A layout window including transistors and I/O pins will appear (Figure 2-2(b)).

Figure 2-2(b). I/O pins and devices generated in the layout window

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4.

Place the N_10_SP and P_10_SP in the layout view. Then, add M1_NWELL, M1_SUB, and power rails. Meanwhile, create the source, drain, gate, and body pickups, and then add the labels. The final layout is shown in Figure 2-3.

Figure 2-3. Complete the layout and add the TEXT to the pin

Now, you are ready for Design Rule Check (DRC).

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Chapter 3. Physical Verification

After the layout creation is completed, we are going to run the physical verification flow to ensure that the layout contains no DRC violations and each device in the layout completely matches with its corresponding component in the original schematic. After that, the parasitic extraction also needs to be performed for the post-layout simulation to ensure our design still works well after taking the parasitic RC effects.

3-1. Assura in GUI Mode

3-1-1. DRC (Design Rule Check) in Assura
In this section, you are going to verify the inverter you have made in the previous section by Design Rule Check (DRC) and to extract SPICE netlist for simulation. You can also verify the layout by CADENCE Assura. A basic understanding of layout rules, particularly the CMOS design rules applied in UMC, is required herein for the users. 1. Select Assura interface (GUI). Run DRC in the layout window (Figure 3-1) to invoke Assura DRC graphic user

Figure 3-1. Invoke Assura DRC graphic user interface

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2.

Fill in the Run Directory, and then select the desired options in Technology and Rule Set (Figure 3-2) in the Run Assura DRC window. You can also set the Assura DRC switches and other parameters, if needed.

Figure 3-2. Run Assura DRC window 3. Click on OK to run the Assura DRC. You may have the DRC violations as shown in Figure 3-3; however, these violations can be waived here.

Figure 3-3. Error Layer window

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3-1-2. LVS (Layout Versus Schematic) in Assura

After the layout is DRC clean, the next step is to run the LVS (Layout Versus Schematic) checking to ensure that the layout totally matches with the schematic. The physical verification procedures for the Assura DFII flow are indicated as follows. 1. Select Assura interface (GUI). Run LVS in the layout window (Figure 3-4) to invoke Assura LVS graphic user

Figure 3-4. Invoke Assura LVS graphic user interface

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2.

Fill in the Run Directory, and then select the desired options in Technology and Rule Set (Figure 3-5) in the Run Assura LVS window. You can also set the Assura LVS switches and other parameters, if needed.

Figure 3-5. Run Assura LVS window 3. Click on OK to run the Assura LVS and the result is shown in Figure 3-6.

Figure 3-6. The LVS run result

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3-1-3. RC Extraction in Assura

After the layout is both DRC and LVS clean, the next step is to perform the RC extraction. 1. Select Assura interface (GUI). Run RCX in the layout window (Figure 3-7) to invoke Assura RCX graphic user

Figure 3-7. Invoke Assura RCX graphic user interface

2.

Select the desired options in Technology and Rule Set.

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3.

In the Setup folder of the Assura Parastic Extraction Run Form window, select Output View (Figure 3-8).

Extracted

Figure 3-8. Select Extracted View in Output

4.

In the Extraction folder of the Assura RCX window, select the Extraction Mode and click on Apply.

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5.

After the RC extraction is completed, a new view (av_extracted view, Figure 3-9) which contains not only the original components but also the parasitic devices will be generated and can be then used for the postlayout simulation.

Figure 3-9. Assura av_extracted view

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3-2. Assura in Batch Mode

Before starting the Assura CDL verification flow, users have to prepare the CDL netlist and the GDS file.

Export CDL Netlist

1. Select File Export CDL in the CIW window to export the schematic netlist (Figure 3-10).

Figure 3-10. Export CDL netlist in CIW

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2.

Select the top cell name to your design, and ensure that the Netlisting Mode is Analog, then fill in the output file name of the netlist.

3.

If the source_added file (empty sub-circuit file) is provided along with the LVS file, you have to attach this file to the output netlist file (obtained from Step 2), as shown in Figure 3-11.

Figure 3-11. Virtuoso CDL Out window

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4.

The result of the exported CDL netlist is shown in Figure 3-12.

Figure 3-12. Exported CDL netlist

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Export GDS File

1. 2. Select File Export Stream in the CIW window to export the GDS file. Select the top cell name to your design, and fill in the layer map table and the output file name of the GDS file (Figure 3-13).

Figure 3-13. Export GDS layout

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3-2-1. DRC (Design Rule Check) in Assura

After the GDS file is exported, you have to edit the Assura ASCII run specific file (RSF) to specify the input data, output data, and types of checking to be run in Assura DRC. 1. Edit the Assura DRC RSF to specify the necessary information (Figure 3-14).

Figure 3-14. Edit Assura DRC RSF file 2. Run the Assura DRC checking in UNIX and check the results. %asssura drc.rsf 3. If the GDS is not DRC clean, you have to go back to fix your layout and re-stream out the GDS for the DRC checking.

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3-2-2. LVS (Layout Versus Schematic) in Assura

When the GDS file contains no DRC violations, you can continue to run the Assura LVS. 1. Edit the Assura LVS RSF to specify the necessary information (Figure 3-15).

Figure 3-15. Edit Assura LVS RSF file

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2.

Run the Assura LVS checking in UNIX and check the results. %asssura lvs.rsf

3.

If the GDS is not LVS clean, you have to go back to fix your layout and re-stream out the GDS for the LVS checking.

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3-3. Calibre in GUI Mode

3-3-1. DRC (Design Rule Check) in Calibre
You can also verify the layout by Mentor Calibre. 1. In the Layout Editing window, select Calibre Run DRC (Figure 3-16) to invoke the Calibre

Interactive DRC window, and click on Cancel or specify your runset file here (Figure 3-17). Then, specify the Calibre DRC Rules File and the Calibre DRC Run Directory (Figure 3-18).

Figure 3-16. Run Calibre DRC

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Figure 3-17. Load Runset File in Calibre Interactive DRC window

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Figure 3-18. Specify Calibre DRC Rules File and Calibre DRC Run Directory

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2.

Specify the Top Cell in the Calibre Interactive DRC window (Figure 3-19). If you need to change some DRC switches, you have to edit the Calibre DRC file first.

Figure 3-19. Specify the Top Cell

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3.

You can see those rules running fast in the Calibre Interactive DRC window (Figure 3-20). Finally, you may have Calibre DRC RVE and DRC Summary Report with the DRC violations as indicated in Figures 3-21 and 3-22; however, these violations can be waived here.

Figure 3-20. Calibre Interactive DRC window

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Figure 3-21. Calibre DRC RVE

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Figure 3-22. DRC Summary Report

After your inverter is laid out without the DRC violations, it is time to run Layout Versus Schematic (LVS) to ensure that the layout is consistent with the schematic.

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3-3-2. LVS (Layout Versus Schematic) in Calibre

In this section, you are going to perform LVS (Layout versus Schematic) using the inverter you have made in the previous section. An LVS can ensure that your laid-out circuit is equivalent to your schematic. 1. In the Layout Editing window, select Calibre Run LVS (Figure 3-23) to invoke the Calibre

Interactive LVS window, and click on Cancel or specify your runset file here (Figure 3-24). Then, specify the Calibre LVS Rules File and the Calibre LVS Run Directory (Figure 3-25).

Figure 3-23. Run Calibre LVS

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Figure 3-24. Load Runset File in Calibre Interactive LVS window

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Figure 3-25. Specify Calibre LVS Rules File and Calibre LVS Run Directory

2.

Specify the Top cell in the Calibre Interactive LVS window. If you need to change some LVS switches, you have to edit the Calibre LVS file first.

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3.

You can see those rules running fast in the Calibre Interactive DRC window (Figure 3-26). Finally, you may have Calibre LVS RVE and LVS Report File as indicated in Figure 3-27.

Figure 3-26. Calibre Interactive LVS window

Figure 3-27. Successful completion of an LVS check

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3-3-3. RC Extraction in Calibre

After the layout is both DRC and LVS clean, the next step is to perform the RC extraction. Here are the two ways to acquire the RC extracted netlist from the layout view. One is to get the ASCII RC extracted netlist file directly from the Calibre XRC interface, and the other is to have the calibre view which is a schematic view containing the connectivity, intentional devices, and parasitic devices extracted by the Calibre-LVS and xCalibre tools. You can simulate the calibre view in CADENCE Analog Design Environment. 1. In the Layout Editing window, select Calibre Run PEX (Figure 3-28) to invoke the Calibre

Interactive PEX window, and click on Cancel or specify your runset file here. Then, specify the Calibre LPE Rules File and the Calibre PEX Run Directory (Figure 3-29).

Figure 3-28. Run Calibre PEX

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Figure 3-29. Specify Calibre PEX Rules File and Calibre PEX Run Directory

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2.

In the Netlist folder, drop down the Format list and select CALIBREVIEW, as shown in Figure 3-30.

Figure 3-30. Select the CALIBREVIEW format

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3.

Click on Run PEX. After the extraction run is completed, the Calibre View Setup window will appear (Figure 3-31). Specify the Cellmap File and Click on OK in the Calibre View Setup window to create the calibre view. This will generate a CADENCE schematic that contains both the intentional and parasitic devices. Generating an extracted view makes it easier to do re-simulation within the CADENCE ADE Environment. The generated calibre view is shown in Figure 3-32.

Figure 3-31. Calibre View Setup window

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Figure 3-32. Calibre extracted view

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3-4. Calibre in Batch Mode

3-4-1. DRC (Design Rule Check) in Calibre
After the GDS file is ready, you have to perform the following steps.

Edit the Calibre DRC file, and specify the GDS file name and the top cell name (Figure 3-33). Check the switches in the file and correctly set these switches when necessary. Run Calibre DRC in UNIX and check the DRC results.

%calibre drc hier calibre.drc

Figure 3-33. Edit Calibre DRC file

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3-4-2. LVS (Layout Versus Schematic) in Calibre

When the DRC checking is completed and the layout contains no DRC violations, the next step is to perform the LVS checking.

Edit the Calibre LVS file, and specify the GDS file name, the top cell name, and the CDL netlist file (Figure 3-34). Check the switches in the file and correctly set these switches when necessary. Run Calibre LVS in UNIX and check the LVS results.

%calibre lvs hier spi layout.net calibre.drc

Figure 3-34. Edit Calibre LVS file

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3-4-3. RC Extraction in Calibre

After the layout is both DRC and LVS clean, the next step is to perform the RC extraction. This step is to prepare the layout extracted netlist for post-layout simulation.

Edit the Calibre RC file, and specify the GDS file name, the top cell name, and the CDL netlist file (Figure 3-35). Check the switches in the file and correctly set these switches when necessary. Run XRC LPE in UNIX and obtain the extracted netlist.

%calibre xrc phdb calibre.drc %calibre xrc pdb c calibre.drc %calibre xrc fmt c calibre.drc

Figure 3-35. Edit Calibre RCX file

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Chapter 4. Post-Layout Simulation

When accomplishing the physical verification, the last stage to tape-out is to perform the post-layout simulation on the extracted netlist/view. During the post-layout simulation, not only the original components but also the parasitic RC (depends on what you have extracted in the RCX stage) of the interconnection are considered. Therefore, we assume that the post-layout simulation result is much closer to the real silicon comparing with the original pre-layout simulation result. Furthermore, based on the difference of the RC extraction flows you have chosen, the post-layout simulation would be performed in different ways. If you choose to output an extracted view during the RC extraction phase (such as going through the Calibre GUI RCX flow or the Assura DFII RCX flow), you may plan to perform the post-layout simulation with the GUI Mode in the CADENCE Analog Artist Environment. Here, we exemplify the av_extracted view that obtained from the Assura DFII RCX flow, and perform the post-layout simulation with Spectre simulator in the CADENCE Analog Artist Environment. 1. Create a config view for the test fixture schematic and switch the calibre (or av_extracted) view of the configuration view (Figures 4-1 and 4-2).

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Figure 4-1. Switch design view to calibre view

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Figure 4-2. Switch design view to av_extracted view 2. Use either the Virtuoso Analog Design Environment or the Hierarchy Editor to simulate the newly created calibre view (Figure 4-3).

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Figure 4-3. Open the Analog Artist Environment and use the config view of the test fixture for simulation
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3.

Run the simulation in the Virtuoso Analog Design Environment.

Figure 4-4. The simulation result 4. You can also generate a netlist in the Virtuoso Analog Design Environment (Figure 4-5) and run the simulation in Batch Mode. The available netlist formats are Hspice and Spectre (Figure 4-6).

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Figure.4-5. Generate a netlist in the Virtuoso Analog Design Environment

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Figure 4-6. Output the netlist for post-simulation

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