74LCX16244 Low Voltage 16-Bit Buffer/Line Driver with 5V Tolerant Inputs and Outputs

February 1994 Revised May 2005

74LCX16244 Low Voltage 16-Bit Buffer/Line Driver with 5V Tolerant Inputs and Outputs
General Description
The LCX16244 contains sixteen non-inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. The LCX16244 is designed for low voltage (2.5 or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The LCX16244 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation.

Features
s 5V tolerant inputs and outputs s 2.3V to 3.6V VCC specifications provided s 4.5 ns tPD max, 10 PA ICCQ max s Power down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s r24 mA output drive (VCC

3.0V)

s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance:

Human body model ! 2000V Machine model ! 200V

s Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC through a pull-up resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver.

Ordering Code:
Order Number 74LCX16244G (Note 2)(Note 3) 74LCX16244MEA (Note 3) 74LCX16244MTD (Note 3) Package Number BGA54A MS48A MTD48 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Note 2: Ordering code G indicates Trays. Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Logic Symbol

GTO is a trademark of Fairchild Semiconductor Corporation.

2005 Fairchild Semiconductor Corporation

DS012000

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74LCX16244

Connection Diagrams
Pin Assignment for SSOP and TSSOP

Pin Descriptions
Pin Names OEn I0I15 O0O15 NC Description Output Enable Input (Active LOW) Inputs Outputs No Connect

FBGA Pin Assignments

1 A B C D E F G H J O0 O2 O4 O6 O8 O10 O12 O14 O15 2 NC O1 O3 O5 O7 O9 O11 O13 NC 3 OE1 NC VCC GND GND GND VCC NC OE4 4 OE2 NC VCC GND GND GND VCC NC OE3 5 NC I1 I3 I5 I7 I9 I11 I13 NC 6 I0 I2 I4 I6 I8 I10 I12 I14 I15

Truth Tables
Inputs OE1 L L Pin Assignment for FBGA H Inputs OE2 L L H Inputs OE3 L L (Top Thru View) H Inputs OE4 L L H
H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance

Outputs I0I3 L H X O0O3 L H Z Outputs I4I7 L H X O4O7 L H Z Outputs I8I11 L H X O8O11 L H Z Outputs I12I15 L H X O12O15 L H Z

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Functional Description
The LCX16244 contains sixteen non-inverting buffers with 3-STATE standard outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. The 3-STATE outputs are controlled by an Output Enable (OEn) input for each nibble. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs.

Logic Diagram

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74LCX16244

Absolute Maximum Ratings(Note 4)

Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 5) VI  GND VO  GND VO ! VCC V mA mA mA mA mA

0.5 to 7.0 0.5 to 7.0 0.5 to 7.0 0.5 to VCC  0.5 50 50 50 r50 r100 r100 65 to 150

qC

Recommended Operating Conditions (Note 6)

Symbol VCC VI VO IOH/IOL Supply Voltage Input Voltage Output Voltage Output Current HIGH or LOW State 3-STATE VCC VCC VCC TA Free-Air Operating Temperature Input Edge Rate, VIN 0.8V2.0V, VCC 3.0V 3.0V  3.6V 2.7V  3.0V 2.3V  2.7V Parameter Operating Data Retention Min 2.0 1.5 0 0 0 Max 3.6 3.6 5.5 VCC 5.5 Units V V V

r24 r12 r8 40

0 85 10

mA

qC
ns/V

't/'V

Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The Recommended Operating Conditions table will define the conditions for actual device operation. Note 5: IO Absolute Maximum Rating must be observed. Note 6: Unused inputs must be held HIGH or LOW. They may not float.

DC Electrical Characteristics
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH IOH IOH IOH IOH VOL LOW Level Output Voltage IOL IOL IOL IOL IOL II IOZ IOFF Input Leakage Current 3-STATE Output Leakage Power-Off Leakage Current Conditions VCC (V) 2.3  2.7 2.7  3.6 2.3  2.7 2.7  3.6 TA

40qC to 85qC
Max

Min 1.7 2.0

Units V

0.7 0.8 VCC  0.2 1.8 2.2 2.4 2.2 0.2 0.6 0.4 0.4 0.55

100 PA 8 mA 12 mA 18 mA 24 mA

100 PA 8 mA 12 mA 16 mA 24 mA

2.3  3.6 2.3 2.7 3.0 3.0 2.3  3.6 2.3 2.7 3.0 3.0 2.3  3.6 2.3  3.6 0

0 d VI d 5.5V 0 d VO d 5.5V VI VIH or VIL 5.5V VI or VO

r5.0 r5.0
10

PA PA PA

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74LCX16244

DC Electrical Characteristics
Symbol ICC Parameter Quiescent Supply Current Increase in ICC per Input VI VIH

(Continued)
VCC (V) V CC or GND VCC 0.6V 2.3  3.6 2.3  3.6 2.3  3.6 TA

Conditions

40qC to 85qC
Max 20

Units

Min

3.6V d VI, VO d 5.5V (Note 7)

r20
500

PA PA

'ICC

Note 7: Outputs disabled or 3-STATE only.

AC Electrical Characteristics
TA Symbol Parameter VCC CL Min tPHL tPLH tPZL tPZH tPLZ tPHZ tOSHL tOSLH Output to Output Skew (Note 8) Output Disable Time Propagation Delay Data to Output Output Enable Time 1.0 1.0 1.0 1.0 1.0 1.0 3.3V r 0.3V 50 pF Max 4.5 4.5 5.5 5.5 5.4 5.4 1.0 1.0

40qC to 85qC, RL 500 :

VCC CL Min 1.0 1.0 1.0 1.0 1.0 1.0 2.7V 50 pF Max 5.2 5.2 6.3 6.3 5.7 5.7 VCC CL Min 1.0 1.0 1.0 1.0 1.0 1.0 2.5 r 0.2V 30 pF Max 5.4 5.4 7.2 7.2 6.5 6.5 ns ns ns ns Units

Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).

Dynamic Switching Characteristics

Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL CL CL CL CL 50 pF, VIH 30pF, VIH 50 pF, VIH 30pF, VIH Conditions 3.3V, VIL 2.5V, VIL 3.3V, VIL 2.5V, VIL 0V 0V 0V 0V VCC (V) 3.3 2.5 3.3 2.5 TA 25qC 0.8 0.6 Typical Unit V V

0.8 0.6

Capacitance
Symbol CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter VCC VCC VCC Open, VI 3.3V, VI 3.3V, VI Conditions 0V or VCC 0V or VCC 0V or VCC, f 10 MHz Typical 7 8 20 Units pF pF pF

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AC LOADING and WAVEFORMS Generic for LCX Family

FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test tPLH, tPHL tPZL, tPLZ tPZH,tPHZ Switch Open 6V at VCC 3.3 r 0.3V VCC x 2 at VCC 2.5 r 0.2V GND

Waveform for Inverting and Non-Inverting Functions

3-STATE Output High Enable and Disable Times for Logic

Propagation Delay. Pulse Width and trec Waveforms

Setup Time, Hold Time and Recovery Time for Logic

3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tR = tF = 3ns) Symbol Vmi Vmo Vx Vy VCC 3.3V r 0.3V 1.5V 1.5V VOL  0.3V VOH  0.3V 2.7V 1.5V 1.5V VOL  0.3V VOH  0.3V

trise and tfall

2.5V r 0.2V VCC/2 VCC/2 VOL  0.15V VOH  0.15V

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74LCX16244

Schematic Diagram Generic for LCX Family

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74LCX16244

Physical Dimensions inches (millimeters) unless otherwise noted

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A

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74LCX16244

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A

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74LCX16244 Low Voltage 16-Bit Buffer/Line Driver with 5V Tolerant Inputs and Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 10 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com