ASIC DESIGN FLOW

ASIC Design is based on a flow that uses HDL as the entry level for design, which applies for both Verilog and VHDL. The following description describes the flow from specification of design upto tapeout, which is the form sent to silicon foundry for fabrication.

The following are the steps for the flow:1. Specification: This is the beginning and most important step towards designing a chip as the features and functionalities of the chip are defined. Both design at macro and micro level are taken into consideration which is derived from the required features and functionalities. Speed, size, power consumption are among the considerations on which the accepted range of values are specified. Other performance criteria are also set at this point and deliberated on its viability; some form of simulation might be possible to check on this. 2. RTL Coding: The microarchitecture at specification level is then transformed in RTL code which marks the beginning of the real design phase towards realising a chip.As a real chip is expected, so the code has to be a synthesiable RTL code. 3. Simulation and Testbench: RTL code and testbench are simulated using HDL simulators to check on the functionality of the design. If Verilog is the language used a Verilog simulator is required while VHDL simulator for a VHDL code. Some of the tools available at CEDEC include: Cadences Verilog XL, Synopsyss VCS, and Mentor Graphics Modelsim. If the simulation results do not agree with the intended function expected, the testbench file or the RTL code could be the cause. The process of debugging the design has to be done if the RTL code is the source of error. The simulation has to be repeated once either one of the two causes, or both, have been

corrected. There could be a possiblity of the loop in this process, until the RTL code correctly describes the required logical behaviour of the design. 4. Synthesis: This process is conducted on the RTL code. This is the process whereby the RTL code is converted into logic gates. The logic gate produced is the functional equivalent of the RTL code as intended in the design. The synthesis process however requires two input files: firstly, the standard cell technology files and secondly the constraints file. A synthesised database of the design is created in the system. 5. Pre-Layout Timing Analysis: When synthesis is completed, the synthesized database along with timing information from the synthesi process is used to perform a Static Timing Analysis (STA). Tweaking (making small changes) has to be done to correct any timing issues. 6. APR: This is the Automatic Place and Route process whereby the layout is being produced. In this process, the synthesized database together with timing information from synthesis is used to place the logic gates. Most designs have critical paths whose timings required them to be routed first. The process of placement and routing normally has some degree of flexibility. 7. Back Annotation: This is the process where extraction for RC parasitics are made from the layout. The path delay is calculated from these RC parasitics. Long routing lines can significantly increase the interconnect delay for a path and for sub-micron design parasitics cause significant increase in delay. Back annotation is the step that bridges synthesis and physical layout. 8. Post-Layout Timing Analysis: This step in ASIC flow allows real timing violations such as hold and setup to be detected. In this step, the net interconnect delay information is fed into the timing analysis and any setup violation should be fixed by optimizing the paths that fail while hold violation is fixed by introducing buffers to the path to increase the delay. The process between APR, back annotation and postlayout timing analysis go back and forth until the design is cleared of any violation. Then it will be ready for logic verification. 9. Logic Verification: This step acts as the final check to ensure the design is correct functionally after additional timing information from layout. Changes have to be made on the RTL code or the post-layout synthesis to correct the logic verification. 10. Tapeout: When the design passed the logic verification check, it is now ready for fabrication. The tapeout design is in the form of GDSII file, which will be accepted by the foundry.