Professional Documents
Culture Documents
International Conference on Advances in Information Communication Technology and VLSI Design–Aug 6 &7 2010
Abstract— Multi-threshold CMOS is popular circuit technique and their comparative results. We have compared CMOS and
that enables high performance and low power operation. This MTCMOS circuits power dissipation over VDD range using
technology features both low threshold voltage and high- BSIM3V3 180nm.
threshold voltage MOSFET in a circuit. While the low-threshold
voltage transistors are used to reduce the propagation delay II. SOURCES OF POWER DISSIPATION
time ,the high-threshold voltage transistors are used to reduce
the power consumption . This paper describes a low-power full adder
with MTCMOS technology. Comparing with the conventional CMOS In digital complementary metal-oxide-semiconductor
circuit, the proposed circuit is achieved to reduce the power consumption (CMOS) circuits there are three sources of power dissipation
by 59%.Simulation has been done on tanner EDA tool at namely, the dynamic power dissipation, the short-circuit
BSIM3v3 180nm technology. power dissipation and the leakage power dissipation [3]. The
average dynamic power dissipation of the CMOS logic gate,
can be calculated from the energy required to charge down the
Keywords— Multithreshold CMOS (MTCMOS), low power total output load capacitance to ground level and charge up the
circuit, full adder. output node to VDD driven by a periodic input voltage
waveform with ideally zero rise- and fall-times.The dynamic
I. INTRODUCTION power dissipation can be shown as [5]
With the advent of integrated circuits, greater emphasis was Pdynamic = α .Cload .V2DD .fCLK (!)
given on performance and miniaturization. But with the
increasing prominence of portable and battery operated Where fCLK is the operating frequency, Cload is the equivalent
appliances the key factor that requires attention is power capacitance of the circuit; VDD is the power-supply voltage
consumption. The feature size is shrinking due to the and α is the activity factor that indicates how often the circuit
advancement in fabrication technology which causes switches with respect to the operating frequency.
integration of more transistors in an integrated circuit. As a A signal of finite rise and fall time applied to the input of a
result, the magnitude of power per unit area is growing[1] and CMOS circuit causes the short-circuit power dissipation. Both
the accompanying problem of heat removal and cooling is the NMOS and the PMOS transistors conduct simultaneously
worsening. To maintain the chip temperature at an acceptable for a short duration due to the finite rise and fall time of input
level the dissipated heat must be removed effectively, the cost signal, forming the direct current path between the power-
of heat removal and cooling becomes a significant factor in supply and ground. For a symmetric CMOS inverter with very
these circuits. The reliability of the chip will be greatly small capacitive load, VTn = VTp = VT and kn = kp = k and
degraded with high power dissipation due to silicon failure input is driven with a waveform with τrise = τfall = τ, the short-
mechanism such as electro migration. The linear scaling of circuit power dissipation can be shown as [5]
supply voltage with the feature size was started from half-
micron technology. But the power supply scaling affects the
speed of the circuit [2]. The need of the time is to put efforts
P (short-circuit) =1/12.k.τ. fCLK. (VDD-2VT)3 (2)
in designing low-power and high speed circuits.
Multi-threshold CMOS (MTCMOS) technology uses both The short-circuit power dissipation depends on the rise and
low threshold voltage and high-threshold voltage MOSFET in fall time of input signal.The two components of leakage
current in CMOS circuit are reverse leakage current and
a single LSI. Multi-threshold CMOS has emerged as an
subthreshold leakage current are illustrated in fig.1 and fig.2
effective technique for reducing subthreshold currents in
respectively. When the P-N junction between the drain and the
standby mode while maintaining circuit performance.
bulk of the transistor is reversely biased the reverse diode
This paper deals with various CMOS and MTCMOS circuits
leakage occurs. The reverse leakage current of the P-N ID(subthreshold) ≈ (qDnWxcn0/ LB).(e qФr/kT). (eq/kT. (A.Vgs+B.Vds)) (4)
junction is shown as [5]
xc= Subthreshold channel depth,Dn = Electron
Ireverse = A.Js. (eqVbias/kT - 1) (3) diffusion coefficient,LB =Length of the barrier
A = Junction area, Js =Reverse saturation current density, region in the channel ,Фr= Reference potential.
q=Charge of electron, Vbias= Reverse bias voltage across the
P-N junction, K= Boltzmann constant and T =Temperature of The leakage current flows through the circuit when
the junction. the circuit is not switching. The leakage power
dissipation can be shown as
Pleakage=VDD.Ileakage (5)
τpα(Cload..VDD)/A.(VDD–VT)2 (6)
Cload =load capacitance of the circuit, VDD=Power-supply
voltage, VT =Threshold voltage of MOSFET.
It is evident from the equation (6), as VDD approaches to VT
the τp will increase. Although the dynamic power dissipation
decreases as the power supply voltage reduces,[6] the
unavoidable design trade-off is the increase of delay. The
propagation delay expressions for the CMOS inverter circuit
can be approximately shown as [5]
(7)
Fig.2 Subthreshold leakage current path in a CMOS inverter with high input
If the power supply voltage is being scaled down while all
other variables are kept constant, can the propagation delay
voltage
time will increase.Fig.3 shows the variation of propagation
The subthreshold leakage current is shown as delay of a CMOS inverter as a function of VDD, where the
threshold voltages of the NMOS and the PMOS are 0.8 V and In the active mode, the high VT transistors are turned on and
-0.8 V respectively. the logic consisting of low VT transistors can operate with low
switching power dissipation and small propagation delay.
When the circuit is driven into standby mode on the other
hand the high VT transistors are turned off and the conduction
paths for any sub-threshold leakage current that originate from
the internal low VT circuitry are effectively cut off.
Fig.6 Power dissipation of full adder using CMOS technology for different
values of supply voltage.
(b)
Fig.5 Schematic of full adder using (a) CMOS (b) MTCMOS technology
VII. CONCLUSION
In this paper low power full adder using MTCMOS was
designed. This technology uses MOSFET with two different
threshold voltages on a single chip and introduces a sleep
control scheme for efficient power management.Low-
threshold voltage MOSFET improving the speed performance
at a low supply voltage, while high-threshold MOSFET
. reduces the standby power dissipation. Comparing with the
conventional CMOS full adder, the proposed full adder circuit
is achieved to reduce the power dissipation by 59% at 180nm technology in tanner EDA tool.
1V.Proposed full adder circuits is simulated at BSIM3v3
TABLE I
COMPARISION TABLE
Power Dissipation(µW)
Gate type Vdd=1.2V VDD=1.0V VDD=0.8
CMOS MTCMOS CMOS MTCMOS CMOS MTCMOS
FULLADDER 10.9 8.04 7.34 3.03 4.29 1.78
II. REFERENCES
[1] Carothers, J.D. and Radjassamy, R., “Low-power VLSI
design techniques-Current State”, IOS Press, 1998.
[2] Chang, M.C. et al, “Transistor-and circuit-design
optimization for low-power CMOS” IEEE Transactions
on electronic devices, Vol. 55, pp. 84-95, January 2008.
[3] Chandrakasan, A.P et al, “Low-Power CMOS Digital
Design”, pp. 473-484, April 1992.
[4] Mutoh S et al, “1-V Power Supply High-Speed Digital
Circuit Technology with Multithreshold-Voltage CMOS”,
pp. 847-854, August 1995
[5] Kang, S and Leblebici, Y., “CMOS Digital Integrated
Circuits”, TMGH, 2003.
[6] Neil H. E. Weste and K. Eshraghian, Principle of CMOS
VLSIDesign, 2nd Ed.addison Wesley, 1993.
[7] J. Yuan and C. Svensson, “High-Speed CMOS
CircuitTechnique,” IEEE J. Solid-State Circuits, vol. 24,
Feb. 1989.