Chapter I

Reed Solomon encoder

1.1 Introduction

Reed– Solomon (RS) codes are non-binary cyclic error-correcting codes invented in
1960; Irving Reed and Gus Solomon published a paper in the Journal of the Society for Industrial
and Applied Mathematics. They described a systematic way of building codes that could detect
and correct multiple random symbol errors. Reed-Solomon coding is a type of forward-error
correction that is used in data transmission (vulnerable to channel noise) plus data-storage and
retrieval systems. Reed- Solomon code’s (encoders/decoders) can detect and correct errors
within blocks of data. Reed-Solomon code’s operate on blocks of data, these codes are generally
designated as (n, K) block codes, K is the number of information symbols input per block, and n
is the number of symbols per block that the encoder outputs. Reed Solomon Decoder is useful in
correcting burst noise; it replaces the whole word if it is not a valid code word. This Reed
Solomon Decoder is designed according to CCSDS Standards.

Reed-Solomon codes are used to perform Forward Error Correction (FEC). FEC
introduces redundancy in the data before it is transmitted. The redundant data (check symbols)
are transmitted with the original data to the receiver. For example, a Reed-Solomon decoder is
used to help recover any error data. The codes are referred to in the format RS (n,k) where k is
the number of s-bit wide information (data) symbols and n is the total number of s-bit wide
symbols in a codeword. The Reed-Solomon encoder generates a code such that the first k
symbols output from the encoder are the information symbols and the next n-k symbols from the
encoder are the check symbols added for error correction.

1.2 Features

Scaling factor for the generator polynomial root index:1

Number of information or data symbols in a code block: 223

Number of symbols in an entire code block: 255

Galois Field polynomial: 285

Bus-width of DATA_IN and DATA_OUT: 4

Fig1: Reed solomon encoder

1.3 Introduction to physical design

In integrated circuit design, physical design is a step in the standard design cycle which
follows after the circuit design. At this step, circuit representations of the components (devices
and interconnects) of the design are converted into geometric representations of shapes which,
when manufactured in the corresponding layers of materials, will ensure the required functioning
of the components. This geometric representation is called integrated circuit layout. This step is
usually split into several sub-steps, which include both design and verification and validation of
the layout.

Modern day Integrated Circuit (IC) design is split up into Front-end design using HDL's,
Verification and Back-end Design or Physical Design. The next step after Physical Design is the
Manufacturing process or Fabrication Process that is done in the Wafer Fabrication Houses. Fab-
houses fabricate designs onto silicon dies which are then packaged into ICs.

Each of the phases mentioned above have Design Flows associated with them. These
Design Flows lay down the process and guide-lines/framework for that phase. Physical Design
flow uses the technology libraries that are provided by the fabrication houses. These technology
files provide information regarding the type of Silicon wafer used, the standard-cells used, the
layout rules, etc.

Technologies are commonly classified according to minimal feature size. Standard sizes,
in the order of miniaturization, are 2μm, 1μm, 0.5μm, 0.35μm, 0.25μm, 180nm, 130nm, 90nm,
65nm, 45nm, 28nm, 22nm, 18nm. Etc

1.4 Physical design flow

Gate Level Netlist

Design Library Constraints

Floor Planning

Power Planning

Placement

Clock Tree Distribution

Routing

Timing Analysis

DRC, ERC, LVS

1.4.1 Physical Design Input Data

Types of data that are required to start a physical design are
− Technology and library files
− Circuit description of the design in the form of netlist representation
− Timing requirements or design constraints
− Floor plan or the physical layout structure
1.4.2 Library Preparation

Library preparation (data preparation) process is done using the tool called Milky Way.
The Milky Way and the data preparation functions can perform several tasks essential for cell
library and data preparation, including the following,
− Creating cell libraries
− Importing cell data
− Specifying technology information
− Writing technology information to a file
− Removing cell hierarchy
− Specifying power and ground port types
− Optimizing the standard cell layout
− Extracting pin and blockage information
− Setting place and route boundaries
− Defining wire tracks

The input for data preparation is the LEF file from foundry. The data preparation for
standard cell using Milky Way is done with the following steps,

Step 1: Run and Read LEF to import LEF files

Step 2: Extract blockage pin and via

Step 3: Set place and route boundary

Step 4: define wire tracks

Technology Library files

− Technology File (tf)

− Library Exchange Format (LEF)
 − Design Exchange Format (DEF)
− Physical library (PLIB)
− Physical Design Exchange Format (PDEF)
− Cell Library Format File (CLF)
− Top Design Format File (TDF)
− Table Look up (TLU)
− Advanced Library Format (ALF)
− Interconnect Technology Files (ITF)

1.4.3 Design Constraints

Design constraints are ASIC design specifications that are applied during logic and
physical synthesis. Each tool attempts to meet two general design constraints
− Timing constraints
− Design rule constraints
Timing constraints are user-specified and are related to speed, area, and the power
consumption of the ASIC design. Timing constraints utilized by physical design tools are
performance related.The most basic timing constraints are as follows
− System clock definition and clock delays
− Multiple cycle paths
− Input and output delays
− Minimum and maximum path delays
− Input transition and output load capacitance
− False paths

1.4.4 Floor Planning

Floor planning is the process of:
− Positioning blocks on the die or within another block, thereby defining routing areas
between them
− Creating and developing a physical model of the design in the form of an initial
optimized layout
A good floor planning should meet the following constraints,
− Minimize the total chip area
− Make the subsequent routing phase easy
− Improve performance, by, for example, reducing signal delays
The input details provided for the floor planning are the design netlist, area requirements,
power requirements, timing constraints, physical partitioning information, die size, etc. After the
floor planning done the output will be a die with the core and I/O area, the macro areas, power
grid designed, power pre-routing, standard cell placement areas defined to the particular design.

1.4.5 Power planning

Power is limiting factor affection performance and features in most important products.
Power management issues are affecting every aspect of the design Software architecture, design
techniques, process technology and design methodology.
Chip-level power management can be treated as two parts,
− Core cell power management
− I/O cell power management

1.4.6 Placement
Exact placement of the modules (modules can be gates, standard cells, macros…) is done
in the process of placement. The goal is to minimize the total area and interconnect cost. Gate-
level netlists contain references to standard cells and macros, which are stored in the logical
libraries, as well as other hierarchical logic blocks. Before placing one must ensure that all
references can be resolved. Placement process done in two steps,
− Global placement: Standard cells must be grouped in a way that the number of
connections between groups is minimum. This issue is solved through circuit
partitioning. As a basic criterion, the minimum is taken among group connections.
− Detailed placement: In detailed placement coarse placement and legalization of the
placement is done. All the cells are placed in the approximate locations but they are not
legally placed and the logic optimization is not done. Legal placement of cells is not
 required for analyzing routing congestion at an early stage, ensuring that the final
placement is legal before saving the design.

1.4.7 Clock tree synthesis

Before going for the clock tree synthesis the design placement should be completed and
power and ground nets are pre-routed, congestion estimation is done which is acceptable,
acceptable timing estimation os completed (~0ns slack).
The goal of clock tree synthesis is to,
• Meet logical Design Rule Constraints (DRC):
− Maximum transition delay
− Maximum load capacitance
− Maximum fanout
− Maximum buffer levels and
• Meet the clock tree targets:
− Maximum skew
− Min/Max insertion delay
Clock Distribution Systems
The types of clock distribution system are as follows,
− Unconstrained tree - Automated buffer placements with unconstrained trees.
− Balanced tree - Multiple levels of balanced tree segments H-tree is most common
− Central spine-Central clock driver.
− Spines with matched branches - Multiple central structures with length (or delay)
matched branches.
− Grid - Interconnected (shorted) clock structure.
− Hybrid distribution - Combination of multiple techniques common theme is tree + grid or
spine + grid.
1.4.8 Routing
Routing is the process of creating physical connections to all clock and signal pins
through metal interconnects. The Routed paths must meet setup and hold timing, max cap/trans,
power and clock skew requirements and also the metal traces must meet physical DRC
requirements. Given a placement, and a fixed number of metal layers, it is required to find a
valid pattern of horizontal and vertical wires that connect the terminals of the nets. The typical
objectives are area (channel width), wire delays, number of layers, number of bends, vias, etc.

The process of routing is done in two levels,

− Global routing: Assigns nets to the global routing cells through which they pass. For each
global routing cell, the routing capacity is calculated according to the blockages, pins,
and routing tracks inside the cell. The objective is to minimize wire length, balance the
congestion, meet timing, noise driven and
− Detailed routing: Detail route is concerned with fixing all the DRC violations after track
assignment. The detail router does not work on the whole chip at the same time like track
assignment determining exactly how each signal is routed through each region Seeking to
reduce routing area.

1.4.9 Design sign-off

In this step the design which is routed is verified for the DRC, LVS and ERC errors and it
has to be corrected for optimization and to meet proper functionality of design. Then the design
is ready for manufacturing process.
Chapter II
Synopsys IC-Compiler
2.1 Introduction
IC Compiler is a single, convergent netlist-to-GDSII or netlist-to-clock-tree-synthesis
design tool for chip designers developing very deep submicron designs. It takes as input a gate-
level netlist, a detailed floorplan, timing constraints, physical and timing libraries, and foundry
process data, and it generates as output either a GDSII-format file of the layout or a Design
Exchange Format (DEF) file of placed netlist data ready for a third-party router. IC Compiler can
also output the design at any time as a binary Synopsys Milkyway database for use with other
Synopsys tools based on Milkyway or as ASCII files (Verilog, DEF, and timing constraints) for
use with tools not from Synopsys.

2.2 IC Compiler design flow

The IC Compiler design flow is an easy-to-use, single-pass flow that provides convergent
timing closure. Figure 2.1 shows the basic IC Compiler design flow, which is centered around
three core commands that perform placement and optimization (place_opt), clock tree synthesis
and optimization (clock_opt), and routing and postroute optimization (route_opt).

Figure 2.1 IC Compiler design flow

Chapter III
Design description and implementation
3.1 Achieving frequency at 400 MHZ
****************************************
Report : clocks
Design : rs_encode
Version: C-2009.06-ICC
Date : Tue Apr 12 23:56:01 2011
****************************************
Clock Period Waveform Attrs Sources
--------------------------------------------------------------------------
master_clock 2.50 {0 1.25} {clkin}
--------------------------------------------------------------------------
Rise Fall Min Rise Min fall Uncertainty
Object Delay Delay Delay Delay Plus Minus
--------------------------------------------------------------------------
master_clock 0.60 0.60 0.60 0.60 0.12 0.25

3.2 Logic area and IO pin

--------------------------------------------------------------------------
FLOORPLAN INFORMATION
--------------------------------------------------------------------------
SITE ROW INFORMATION
--------------------
Site Type Hrows Vrows Tiles Width Height Row area
unit 63 0 41202 0.20 1.80 14832.72

CHIP AND CORE INFORMATION

-------------------------
Width Height Area
Core 130.800 121.200 15852.960
Chip 172.800 163.200 28200.960

--------------------------------------------------------------------------
UTILIZATION INFORMATION
--------------------------------------------------------------------------

CELL INSTANCE SECTION

---------------------
Cell Instance Type Count Area Sites
Placed Cells 2034 8040.96 unit:22336
Fixed Cells 0 0.00 --
Soft Fixed Cells 0 0.00 --
Unplaced Cells 0 0.00 --
Fixed Cells 2 16.56 unit:46
Non-Fixed Cells 2032 8024.40 unit:22290
UTILIZATION RATIOS
------------------
Chip area : 28200.96
Core Area : 15852.96
SiteRow area : 14832.72
Non-SiteRow area : 1020.24
Cell/Core Ratio : 50.7221%
Cell/Chip Ratio : 28.5131%

3.3 Floorplanning and PG network

VDD rail
W_vertical – Metal 8 = 8 microns
W_horizontal – Metal 9 = 8 microns

VSS rail:
W_vertical – Metal 8 = 8 microns
W_horizontal – Metal 9 = 8 microns

Core to IO clearance width = 21 microns

Core Area IO Pads

Power (VDD) and

Ground (VSS) rails
 Power and
Ground
pins

3.4 Placement
 Power
straps

3.5 Clock tree synthesis information

Timing report before clock tree synthesis

-----------------------------------------------------------
data required time 2.31
data arrival time -2.37
-----------------------------------------------------------
slack (VIOLATED) -0.06

Clock distribution before clock tree synthesis

Clock distribution after CTS

Timing report after CTS

-----------------------------------------------------------
data required time 2.36
data arrival time -2.28
-----------------------------------------------------------
slack (MET) 0.08

3.7 Routing with 9 layer metal

3.8 DRC

--------------------------------------------------------------------
Rule: Met1 Spacing: minimum spacing = 0.09 um 220 errors
Rule: Met1 Overlap: metal & blockage overlap 4 errors
Rule: Met1 specEoLSpc: spacing= 0.11 ,crnKeepOut= 0.035 um(mode = 4 )
1 error
Rule: Met1 FatWireSpc: fat metal ( 0.201 um, 0.381 um) minimum spacing
= 0.11 um 62 errors
Rule: Met1 FatWireSpc: fat metal ( 0.421 um, 0.421 um) minimum spacing
= 0.16 um 1 error
Chapter IV
Design attributes

4.1 Power architecture

Power strap width calculations

Number of cell instances = 2145

Number of nets = 2289
Total dynamic power = 1.3502 mw
Supply voltage (v) = 1.32

Aspect ratio / Core utilization = (Number of cell instances) / (Number of nets)

= 0.937
Total dynamic core current
(Total dynamic power) / (Supply voltage)
= 1.022 ma
Current supply from each side of the block
Width of the block = 131
Height of the block = 121

= 0.265 ma

= 0.0245 ma
Calculation of power-strap width [IR]
Max Current density of M8 and M9 = 80.96
Roe of M8 and M9 = 0.0218

= 0.0032 microns

= 0.0030 microns
Calculation of power-strap width [EM]
W strap_vertical = (I top X Roe X Hblock) / 0.07VDD
= 8 microns

W strap_vertical = (I top X Roe X Hblock) / 0.07VDD

= 8 microns

Power refresh straps

Number of power/ground refresh
N refresh_horizontal = Wstrap_horizontal / W refresh
=3
N refresh_horizontal = Wstrap_horizontal / W refresh
=3
Spacing of each refresh
S refresh_horizontal = H block / W refresh_horizontal
= 48 microns
S refresh_vertical = W block / W refresh_vertical
= 45 microns
4.2 Design constraints
###################################################################

# Created by write_sdc on Thu Mar 31 22:21:30 2011

###################################################################
set sdc_version 1.8

set_units -time ns -resistance kOhm -capacitance pF -voltage V

-current mA
set_operating_conditions BCCOM -library tcbn65lpbc
create_clock [get_ports clkin] -name master_clock -period 2.5
-waveform {0 1.25}
set_max_dynamic_power 2 mw
set_max_leakage_power 10 uw
set_clock_latency 0.6 [get_clocks master_clock]
set_clock_uncertainty -setup 0.25 [get_clocks master_clock]
set_clock_uncertainty -hold 0.125 [get_clocks master_clock]
set_clock_transition -fall 0.025 [get_clocks master_clock]
set_clock_transition -rise 0.025 [get_clocks master_clock]

4.3 Reports

Timing report after routing

****************************************
Report : timing
-path full
-delay max
-max_paths 1
Design : rs_encode
Version: C-2009.06-ICC
Date : Tue Apr 12 10:39:19 2011
****************************************
Operating Conditions: BCCOM Library: tcbn65lpbc

Startpoint: b15/out_reg[2]
(rising edge-triggered flip-flop clocked by
master_clock)
Endpoint: b8/out_reg[5]
(rising edge-triggered flip-flop clocked by master_clock)
Path Group: master_clock
Path Type: max
-----------------------------------------------------------
data required time 2.36
data arrival time -2.28
-----------------------------------------------------------
slack (MET) 0.08
Power report after routing

****************************************
Report : power
-analysis_effort low
Design : rs_encode
Version: C-2009.06-ICC
Date : Tue Apr 12 23:58:04 2011
****************************************

Library(s) Used:
tcbn65lpwc (File:
/home/libraries/std/Front_End/timing_power_noise/tcbn65lpwc.db)

Operating Conditions: BCCOM Library: tcbn65lpbc

Wire Load Model Mode: segmented

Design Wire Load Model Library

------------------------------------------------
rs_encode ZeroWireload tcbn65lpwc

Global Operating Voltage = 1.32

Power-specific unit information :
Voltage Units = 1V
Capacitance Units = 1.000000pf
Time Units = 1ns
Dynamic Power Units = 1mW (derived from V,C,T units)
Leakage Power Units = 1nW

Cell Internal Power = 1.1041 mW (80%)

Net Switching Power = 283.2232 uW (20%)
---------
Total Dynamic Power = 1.3873 mW (100%)

Cell Leakage Power = 2.4163 uW

Chapter V

Results and Conclusion

5.1 Results
 Achieved frequency is 400 MHz
 Slack is met with the value 0.08
 The logic area is 51%
Width Height Area
o Core 130.800 121.200 15852.960
o Chip 172.800 163.200 28200.960
 Chip width is 131 microns
 Chip height is 121 microns
 Power and Ground rail width of 8 microns
 Timing is met with the skew of 0.08 after CTS
 Routing is done with 9 layer metal
 The design is free from all DRC violations except the Met 1 violations
 The total dynamic power of the chip after routing is 1.3873 mw with the leakage power
of 2.4163 um
5.2 Conclusion
Implementation of the High speed Reed Solomon encoder using Synopsys IC compiler is
successfully completed meeting all design specifications.
The design is successfully implemented .to work with the operating frequency of 400
Mhz with the supply voltage of 1.32v.
The timing constraint of the design is met with the positive slack of 0.08 ns.
The total dynamic power achieved is 1.3873 mw which is within the range of dynamic
power specified (i.e. 2 mw).
The total area of the chip is 28200.960 microns out of wich 51% of the area is occupied
by the core of the design.