3.

INTRODUCTION TO MICRO COMPUTER AND MICROPROCESSOR

3.0 Introduction

A Microprocessor is a multipurpose programmable logic device which reads the

binary instructions from a storage device called ‘Memory’ accepts binary data as input and
process data according to the instructions and gives the results as output. So, you can
understand the Microprocessor as a programmable digital device, which can be used for both
data processing and control applications. In view of a computer student, it is the CPU of a
Computer or heart of the computer. A computer which is built around a microprocessor is
called a microcomputer. A microcomputer system consists of a CPU (microprocessor),
memories (primary and secondary) and I/O devices as shown in the block diagram in Fig 3.1.
The memory and I/O devices are linked by data and address (control) buses. The CPU
communicates with only one peripheral at a time by enabling the peripheral by the control
signal. For example to send data to the output device, the CPU places the device address on
the address bus, data on the data bus and enables the output device. The other peripherals
that are not enabled remain in high impedance state called tristate.

3.1 Evolution of Microprocessors

The first Microprocessor was designed by Intel Corporation which was founded by Moore
and Noyce in 1968. In the early years, Intel focused on developing semiconductor memories
(DRAMs and EPROMs) for digital computers. In 1969, a Japanese Calculator manufacturer ,
Busicom approached Intel with a design for a small calculator which need 12 custom chips. Ted
Hoff, an Intel Engineer thought that a general purpose logic device could replace the multiple
components.This idea led to the development of the first so called microprocessor. So,
Microprocessors started with a modest beginning of drivers for calculators. Fedrico Faggin and
Stanely Mazor implemented the ideas of Ted Hoff’s and designed the Intel 4000 family of
processors comprising 4001 (2K-ROM), the 4002 (320 bit RAM), the 4003 (10 bit I/O shift-
register) and the 4004, a 4 bit CPU. Intel introduced the 4004 microprocessor to the world wide
market on November 15, 1971. It was a 4-bit PMOS chip with 2300 transistors. Around the
same time Texas Instruments developed a 4-bit microprocessor TMS 1000 and became the
owner of microprocessor patent. Later Intel introduced world’s first 8 bit general purpose
microprocessor 8008 in 1972. This processor was used in the popular computer ‘Mark-8’ in
those days. In 1974, Intel introduced the improved version of 8008, the 8080 microprocessor.
This 8080 is the much more highly integrated chip than its predecessorswhich is built around N-
channel MOS technology.It could execute upto 290,000 operations per second and could
address upto 64K.bytes of memory. The other notable 8 bit microprocessors include Motorola
6800, Rockwell PPS-8 and Signetics 2650 with powerful architecture and instruction set.

With developments in integration technology Intel was able to integrate the additional
chips like 8224 clock generator and the 8228 system controller along with 8080 microprocessor
with in a single chip and released the 8 bit microprocessor 8085 in the year 1976. The 8085
microprocessor consisted of 6500 MOS transistors and could work at clock frequencies of 3-5
M.Hz.It works on a single +5 volts supply.The other improved 8 bit microprocessors include
Motorola MC 6809, Zilog Z-80 and RCA COSMAC.

In 1978 ,Intel introduced the 16 bit microprocessor 8086 and 8088 in 1979. IBM selected
the Intel 8088 for their personal computer (IBM-PC).8086 microprocessor made up of 29,000
MOS transistors and could work at a clock speed of 5-10 M.Hz.It has a 16-bit ALU with 16-bit
databus and 20-bit address bus.It can address up to 1MB of address space.The pipelining
concept was used for the first time to improve the speed of the processor.It had a pre-fetch
queue of 6 instructions where in the instructions tobe executed were fetched during the execution
of an instruction.It means 8086 archtecture supports parallel processing.The 8088

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microprocessor is similar to 8086 processor in architecture ,but the basic difference is it has only
8-bit data bus even though the ALU is of 16-bit.It has a pre-fetch queue of 4-instructions only.

In 1982 Intel released another 16-bit processor called 80186 designed by a team under the
leadership of Dave Stamm.This is having higher realiability and faster operational speed but at a
lower cost.It had a pre-fetch queue of 6-instructions and it is suitable for high volume applications
such as computer workstations,word-processor and personal computers.It is made up of 134,000
MOS transistors and could work at clock rates of 4 and 6 M.Hz.This is also comes under first
generation of Microprocessors.

Intel released another 16 bit microprocessor 80286 having 1,34,000 transistors in 1981. It was
used as CPU in PC-ATs in 1982. It is the second generation microprocessor ,more advanced to
80186 processor. It could run at clock speeds of 6 to 12.5 M.Hz .It has a 16-bit data bus and 24-
bit address bus ,so that it can address upto 16MB of address space and 1GB of virtual memory.It
had a pre-fetch queue of 6 instructions .Intel introduced the concept of protected mode and
virtual modeto ensure proper operation.It also had on-chip memory management unit (MMU)
.This was popularly called as Intel 286 in those days.

In 1985, Intel released the first 32 bit processor 80386, with 275,000 transistors. It has 32-
bit data bus and 32-bit address bus so that it can address up to a total of 4GB memory also a
virtual memory space of 64TB.It could process five million instructions per second and could
work with all popular operating systems including Windows.It has a pre-fetch queue of length 16-
bytes with extensive memory management capabilities. It is incorporated with a concept called
paging in addition to segmentation technique. It uses a math co-processor called 80387.

Intel introduced 80486 microprocessor with a built-in maths co-processor and with 1.2 million
transistors . It could run at the clock speed of 50 M.Hz This is also a 32 bit processor but it is
twice as fast as 80386.The additional features in 486 processor are the built-in Cache and built-in
math co-processors.The address bus here is bidirectional because of presence of cache
memory.

On 19th October,1992, Intel released the Pentium Processor with 3.1 million transistors. So,the
Pentium began as fifth generation of the Intel x86 architecture.This Pentium was a backward
compatible while offering new features.The revolutionary technology followed is that the CPU is
able to execute two instruction at the same time..This is known as super scalar technology. The
Pentium uses a 32-bit expansion bus ,however the data bus is 64 bits.

The 7.5 million transistors based chip,Intel Pentium II processor was released in 1997. It works
at a clock speed of 300M.Hz. Pentium II uses the Dynamic Execution Technology which consists
of three different facilities namely, Multiple branch preditction,Data flow analysis, and Speculative
execution unit. Another important feature is a thermal sensor located on the mother board can
monitor the die temperature of the processor.for thermal management applications.

Intel Celeron Processors were introduced in the year 1999. Pentium-III processor with 9.5
million transistors was introduced in 1999. It also uses dynamic execution micro-architecture ,a
unique combination of multiple branch prediction ,dataflow analysis and speculative
execution.The Pentium III has improved MMX and processor serial number feature.The improved
MMX enables advanced imaging,3D streaming audio and vedio,and speech recognition for enhanced
Internet facility.

Pentium-IV with 42 million transistors and 1.5 G.Hz clock speed was released by Intel in
November 2000. The Pentium 4 processor has a system bus with 3.2 G-bytes per second of
bandwidth.This high bandwidth is a key reason for applications that stream data from
memory.This bandwidth is achieved with 64 –bit wide bus capable of transferring data at a rate of

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400 MHz. The Pentium 4 processor enables real-time MPEG2 video encoding and near real-
time MPEG4 encoding, allowing efficient video editing and video conferencing.

Intel with partner Hewlet-Packard developed the next generation 64-bit processor
architecture called IA-64 .This first implementation was named Itanium.Itanium processor which
is the first in a family of 64 bit products was introduced in the year 2001.The Itanium processor
was specially designed to provide a very high level of parallel processing ,to enable high
performance without requiring very high clock frequencies .Key strengths of the Itanium
architecture include ,up to 6 instructions/cycle.The Itanium processor can handle up to 6
simultaneous 64 –bit instructions per clock cycle.

The Itanium II is an IA-64 microprocessor developed jointly by Hewlet-Packard (HP)

and Intel and released on July 8,2002..It is theoretically capable of performing nearly 8 times
more work per clock cycle than other CISC and RISC architectures due to its parallel computing
micro-architecture.The recent Itanium processor features a split L2 cache,adding a dedicated
1MB L2 cache for instructions and thereby effectively growing the original 256KBL2 cache, which
becomes a dedicated data cache. The first Itanium 2 processor (code named McKinley) was
more powerful than the original Itanium processor , with approximately two times performance .

Pentium 4EE was released by Intel in the year 2003 and Pentium 4E was released in the
year 2004.

The Pentium Dual-Core brand was used for mainstream x86-architecture microprocessors
from Intel from 2006 to 2009 The 64 bit Intel Core2 was released on July 27,2006. In terms of
features, price and performance at a given clock frequency, Pentium Dual-Core processors were
positioned above Celeron but below Core and Core 2 microprocessors in Intel's product range. The
Pentium Dual-Core was also a very popular choice for overclocking, as it can deliver optimal
performance (when overclocked) at a low price.
•
The Pentium Dual Core, which consists of 167 million transistors was released on January 21,
2007. Intel Core Duo consists of two cores on one die, a 2 MB L2 cache shared by both cores,
and an arbiter bus that controls both L2 cache and FSB access.

Core 2 Quad processors are multi-chip modules consisting of two dies similar to those used in
Core 2 Duo, forming a quad-core processor. While this allows twice the performance to a dual-
core processors at the same clock frequency in ideal conditions, this is highly workload specific
and requires applications to take advantage of the extra cores.

In September.2009, new Core i7 models based on the Lynnfield desktop quad-core processor
and the Clarksfield quad-core mobile were added, and models based on the Arrandale dual-core
mobile processor have been announced. The first six-core processor in the Core lineup is the
Gulftown, which was launched on March 16, 2010. Both the regular Core i7 and the Extreme
Edition are advertised as five stars in the Intel Processor Rating.

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3.2 The Intel 8085 Microprocessor

Intel 8085A is a single chip 8-bit N-channel microprocessor which works at +5V DC
power supply. It is a 40 pin IC available as a DIP (Dual Inline Package) chip. 8085A can
operate with a 3MHZ single phase clock and 8085A-2 version can operate at a maximum
frequency of 5MHZ. This 8085 is an enhanced version of its predecessor the 8080A. Its
instruction set is upward compatible with that of the 8080A. 8085A has an on-chip clock
generator with external crystal, LC or RC network. This 8085 microprocessor is built with
nearly 6200 transistors. The enhanced version of 8080a is the Intel 8085AH. It is an N
channel depletion load, silicon gate (HMOS) 8-bit processor. Here 3MHZ, 5MHZ and 6MHZ
selections are available. It has 20% lower power consumption than 8085A for 3MHZ
and5MHZ. Its instruction set is 100% software compatible with the 8085A. It is also 100%
compatible with 8085A.

3.3 Central Processing Unit (CPU)

The Central Processing Unit of any microcomputer is the microprocessor. Hence

microprocessor is also known as the heart of the computer. The CPU performs the various
activities in response to set of instructions called a program. Programs are stored in the
memory. The CPU reads in data control signals (instructions) through the input ports and
executes one instruction at a time.
So, generally speaking, a microprocessor Is nothing but the CPU the Intel 8085 CPU
is an 8-bit device with a clock speed of 3-5 MHZ. It has 80 basic instructions and 146
opcodes. Its clock cycle is 320 ns. The time for the clock cycle of Intel 8085 is 200 ns. The
block diagram of 8085 is shown in Fig 3.1.. The 8085 CPU consists of three major sections,
They are: (i) Arithmetic and logic unit (ALU)
(ii) Registers
(iii)Timing and Control unit.

3.3.1 Arithmetic and logic unit (ALU): The ALU performs all the arithmetic and logical operations
like addition, subtraction, complementing, logical AND, logical OR, logical Exclusive OR,
incrementing and decrementing, rotate, shift and clear. An ALU is made of many logic gates
and adders etc.

The arithmetic and logic unit consists of the following units:

(a).Accumulator (A).
(b).Temporary register.
(c).Flag register.

(a).Accumulator (A): It is an 8-bit register which is treated as a special function register. Most of
the arithmetic and logic operations are performed using the accumulator. All the I/O data
transfers between 8085 and I/O devices are performed via accumulator. One of the operands
for arithmetic operations in ALU is from the accumulator. After performing the arithmetic
operations the result is stored back in accumulator. It is from the accumulator only, the data
is sent out to an output device. Similarly. The data from an input device is read only through
the accumulator. The data in the accumulator alone can be rotated or shifted. No other
register can be used for these operations. Certain instructions like DAA are performed using
only accumulator. So, many times the Accumulator register is treated as a default register.

(b).Temporary register: This is 8-bit register which is not accessible to the user. This register is
used by the microprocessor to load the second operand during arithmetic/logical operations
in ALU. The final result is stored in the Accumulator and the flags are set or reset according
to the result of the operation. For example when MVI M, 17H instruction is fetched, IR
register will receive the opcode for MVI M and the Temporary register will receive 34H.

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 In arithmetic and logical operations, that involves two operands. The accumulator
provides one operand. And the other is provided by the temporary register. For example in
ADD C instruction C register
contents are moved to the Temp. Register and the addition of A and Temp. Register contents is
performed by the ALU.
(c).Flag register: The flag register is an 8- bit register which generally reflect data conditions in
the accumulator with certain exceptions. Hence this flag register is also known as status
register. Through this flag register is an eight bit register, it contains only 5 flag bits and the
remaining three bits are undefined as shown below. In the Flag register each flag bit is a Flip-
Flop. i.e., the bit may be either in the flip state or flop state

S - Sign Flag: After execution of an arithmetic and logic operation, if bit D 7 of the result (Normally
in the Accumulator) is 1, the sign flag is set. This Flag is used with signed numbers.
For example in a given byte, if D 7 is 1, the number is treated as a negative number. Else (if
it is zero), it is viewed as a positive.
In arithmetic operations with signed numbers bit D 7is reserved for indicating the sign and
the remaining seven bits are used to denote the magnitude of the number.

Z - Zero Flag: This Flag is set (made 1) if the result after any arithmetic operation is zero, and the
flag is reset (made 0) if the result is not zero. So, this flag is set or reset based on the results
in the accumulator as well as in the other registers.

AC – Auxiliary carry Flag: In this arithmetic operation, when a carry is generated by and passed
on to bit bit4, the AC flag is set. This flag is used internally for BCD arithmetic and is not
available for the programmer to change the sequence of a program with a jump instruction.
But the Z and CY flags can be used for this purpose.

Parity Flag: If the result after an arithmetic and logical operation has an even number of 1s, this
parity flag is set to 1 otherwise (if number of 1s is odd) the flag is reset (made0).
For example the data byte 10111101 has even parity and the data byte 10011011 has odd parity.
So P bit=0.

CY-Carry flag: After an arithmetic operation, like addition, subtraction if there exists a carry or
barrow, this flag CY is set to 1 else it is reset (made0)
Example: Let us consider the addition of two binary numbers 11011001 and 11101101 and check
the Flag register. D7 D0
11011001
11101101

In the result, the sum is not zero, So Z-Flag is reset (Z=0).

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There is a carry from the third bit to fourth bit. So AC Flag is set (AC=1).
The D7 bit=1, so, the sign Flag is set (S=1).
In the result, the no. of 1s is even. So, parity is even (P=1).
After addition, there is a carry. So carry Flag is set (CY=1).
Therefore the Flag register contents after addition are as shown below

1 0 X 1 X 1 X 1

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3.3.2 Timing and control Unit: This unit of the microprocessor issues necessary timing and
control signals for the execution of instructions. It generates three types of signals namely
status, control and timing signals required for the operation of memory and I/O devices. This
unit with the help of these signals controls the entire operation of the microprocessor and the
peripherals. The signals associated with this unit are two control signals. and these

status signals IO/ , S1 and S0 to identify the nature of the operation, and one special signal
ALE which indicates the starting of the operation. These signals are explained below.
-Read (active low): This is a Read control signal. This signal indicates that the selected I/O
or memory device is to be read and data are available on the data bus.

- Write (active low): This is a Write control signal. This signal indicates that the data on the
data bus are to be written into a selected memory or I/O device.
IO/ : This is a status signal used to differentiate between I/O and memory operations. When this
signal is high, it indicates an I/O operation, when it is low it denotes a memory operation. This
signal is combined with Read ( ) and Write to generate necessary I/O and memory
control signals.
S1 and S0 : These signals are also status signals like IO/ , used to identify various operations.
The complete operation of the microprocessor can be understood by these three signals. The
various operations and the associated status signals are given in Table 3. .
ALE – Address Latch Enable: This is a positive going pulse generated every time the 8085
begins an operation, It indicates that the bits on AD7 - AD0 are address bits. This signal is
used primarily to latch the low-order address from the multiplexed bus and generate a set of
eight address lines A7 – A0.

S. No IO/ S1 S0 Status

1 0 0 0 Memory Write

2 0 1 0 Memory Read
1 0 I/O Write
3 1 1 1 I/O Read
4 1/0 1 0 Opcode fetch
5 1 1 1
Interrupt
6 * 0 Acknowledge
7 * X 1 Halt
8 * X 0 Hold
9 Reset
X
X

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 Table3. Status signal of 8085

3.3.3 Register Organization:

The 8085 microprocessor has different types of registers. It includes six 8 – bit registers
(B,C,D.E,H and L), one 8-bit Accumulator and two 16-bit registers (SP and PC). In addition
there are two 8-bot temporary registers W and Z. Among these registers W and Z are not
accessible to user, They are used by the processor for internal, intermediate operations. The
remaining registers are accessible to the user. The organization of 8085 registers is shown in
Fig 3. .
The various registers of 8085 are classified into three types. They are
(i) Temporary registers.
(ii)General purpose registers
(iii)Special purpose registers.

(i) Temporary registers: The (i) Temporary registers are Temporary data registers, W register
and Z register. All are 8-bit registers. The Temporary data register is associated with the ALU
operations. One of the operand is stored in this register. This will not accessed by the user.
Similarly W and Z are also temporary registers used to hold 8-bot data during execution of
certain instructions, As these registers are internally used by the CPU, they are not
accessible to the user.
The W and Z registers are used by the processor during CALL instruction. When a CALL
instruction is encountered in any program, the current program counter (PC) contents are
pushed on to the stack and the given address is loaded on to PC. The given address is
temporarily stored in W and Z registers and placed on the bus for the fetch cycle. Thus the
program control is transferred to the address given in the instruction.
Another example is during the execution of XCHG instruction, the contents of H-L pair are
exchanged with D-E pair. At the time of exchange W and Z registers are used for temporary
storage of data.

(ii)General purpose registers: B, C, D, E, H and L are six, 8-bit general purpose registers to store
data. These registers can be used as separate 8-bit registers and also can be paired as 16-
bit registers to store the address of a memory location. But they must be paired as B-C; D-E
and H-L register pairs only as shown

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When used as pair, In example B-C, the higher order byte moves to the first register (B) and the
low order byte moves to the second register (C). the HL pair also functions as a data pointer
or memory pointer
For Ex: LXI H, 8500 H.
This will load immediately the address of memory location (8500) in to H-L pair is now the H-L
pair points to the location 8500 H.

(iii)Special purpose registers: The Special purpose registers as their name indicates, are used for
some specific purpose. The Special purpose registers are Accumulator (A), Flag Register,
Instruction Register, Program Counter (PC) and Stack Pointer (SP).

Accumulator (Register A): It is an 8-bit tristate register. It is mainly used for arithmetic, logic, load
and store operations. It is also used in I/O operations. In most of operations, the result is
stored in Accumulator after execution.

Flag Register: It is an 8-bit register. Which consists of only five flags, each flag bit is a flip flop
that indicates either a set or reset state. The five flags are Sign, Zero, Auxiliary carry, Parity
and Carry as shown below

Here X means undefined.

Sign Flag: The sign flag is set to1 if the most significant bit of the result of an arithmetic or logoc
operations is 1. Else it is reset (0).

Zero Flag: The Zero status flag is set to 1 if the result of an arithmetic or logic operation is Zero
For non-Zero result it is reset to 0.

Auxiliary carry Flag: This flag is set if there is a carry from 3rd bit to 4th bit during BCD operations
(carry from lower nibble to higher nibble). This flag is not accessible to the user.

Parity Flag: Parity is defined by the number of 1s present in a binary number stored in A register.
After any arithmetic or logical operation, if the result has even number of 1s it is called even
parity and the Parity Flag is set to 1. Otherwise. i.e. If there is odd number of 1s in the result,
it is called Odd Parity and the Parity flag is set 0.

Instruction Register: It is an 8-bit register, which is a part of ALU. When an instruction is fetched
from memory, it is loaded in the Instruction Register. This register holds the instruction unit it
is decoded by the Decoder. The instruction register is not programmable and cannot be
accessed through any instruction.

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Program Counter (PC): It is a 16-bit special purpose register, which stores the address of the
next instruction to be fetched or executed. The execution of a program is initiated by loading
the PC by the address of the first instruction of the program. Once the first instruction is
executed, the PC is automatically incremented to point to the next instruction unless a jump
to some specific address is necessary. This process is repeated till the last instruction of the
program.
In case of JUMP or CALL instructions is stored in the Program Counter. The processor
then fetches the next instruction from the new address specified by the JUMP or CALL
instruction. In conditional JUMP and conditional CALL instruction, if the condition is not
satisfied, the processor increments the Program Counter by three so that it points the
instruction followed by the conditional JUMP or CALL instruction, otherwise processor
fetches the next instruction from the new address specified by JUMP or CALL instruction.

Stack Pointer (SP): It is a 16-bit special purpose register which always stores the top address of
the Stack. i.e. it always points to top of the Stack. Stack is a part of the memory location used
to store the data temporarily. A stack works on Last in First out (LIFO) basis. As the Stack
pointer always points to the top of the Stack, only top of the Stack of the memory can be
accessed. When a Write operation (PUSH) takes place, the contents of the stack pointer is
decremented by two so that the SP points to the new location. Similarly when the Read
operation (POP) occurs, the Stack pointer is incremented by two to point to the next data on
top of the Stack.
The Stack Pointer is initialized by load register pair immediate instruction.
LXI SP, 8530
Here 8530 is the 16 bit address of the top of Stack location.

The remaining blocks of 8085 microprocessor block diagram are explained below.

Instruction Register and Decoder:

The instruction register and the decoder are also part of the ALU. When an instruction
is fetched from memory, it is loaded in the instruction register. The Decoder decodes the
instruction and develops the sequence of events to follow. The instruction register is a 8 – bit
special register, but it is not a programmable and is not accessible to the user. He instruction
at a binary level and sends the appropriate signals to the control unit.

Increment/ Decrement Address Latch:

This is a 16 bit special register not accessible to the user. This register is used by the
CPU to increment/ decrement the contents of the Stack Pointer (SP) and increment program
counter (PC) during instruction execution. During first T - state of op code fetch machine
cycle (T1) the micro processor increments the PC register contents to point to the next
location. This increment operation takes place on increment/ decrement register address
latch. The 16 bit address that is sent out through AD0-AD7 and A8-A15 are latched into this
register. The address bus AD0-AD7 continues to be available on the bus after T 1 state from
this latch.

Address Buffer:

This is an 8-bit unidirectional buffer. It is used to drive external higher order address bus. It
is also used to tri-state the higher order address (A8-A15) bus under certain conditions like
reset, hold, and halt and also when address lines are not in use.

Address/Data Buffer:

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 This is an 8-bit bi-directional buffer. It is used to drive multiplexed address/data bus. It
means low order address bus(A7-A0) and data bus (D7-D0). It is also used to tri-state the
multiplexed address/data bus under certain conditions like reset, hold, and halt and also
when data lines are not in use.
The address and data bus buffers are used to drive external address and data buses
respectively. Due to these buffers the address and data buffers can be tri-stated when they
are not in use. In actual practice, in a microprocessor the driving capacity of the address
pins after the internal buffering may not be adequate. So, there will be external buffer chips
also available.

Serial I/O control:

This control provides, two lines SOD (Serial Out Data) and SID (serial In Data) for serial
communication. These lines are used during serial data transmission over long distance
where data is transmitted and received bit by bit. The Serial Output Data (SOD) pin is used
to send data serially and serial Input Data (SID) pin is used to receive data serially by the
8085 microprocessor.
Interrupt control:
This is an important block related to interrupts. This block is linked to the CPU through the 8-
bit internal data bus. This interrupt control has five interrupt signals. They are TRAP, RST
7.5, RST 6.5, RST 5.5 and INTR. The control block will take care of enabling and disabling of
these interrupts etc…

3.4 Address, Data and Control Buses:

Intel 8085 has 16-bit unidirectional address bus which carries the address of memories
and peripheral devices. A bus is nothing but a group of electrical lines used to transmit the
information as electrical signals. So, this 16-bit parallel address bus carries address from
microprocessor to memories/peripherals. Hence it is Uni-directional. The width of the parallel
bus determines now much memory that a microprocessor can address, the 8085
microprocessor with 16-bit address bus can address a maximum of 2 16= 65536=64 KB of
memory locations. The size of the address bus is independent of the size of the
microprocessor.
In INTELL 8085 microprocessor, the 8 most significant bits of the address are
transmitted by the high order address bus A8-A15. But the 8 least significant bits of the
addresses are transmitted by Address/Data bus or A/D bus. i.e. the lower order address lines
are multiplexed with the data bus. So, the AD bus operates in a time shared mode. i.e. the
data and address are sent on the same lines but at different instants of time. A 0-A7 will
always have the address during the first T state (T1) of the machine cycle. To Demultiplexed
the AD bus the pin ALE is used. When ALE=1 (high) the AD bus acts as a lower order
address bus else it acts as Data bus.
The Data bus is a bidirectional bus which is used to send data to and from the
microprocessor. This is also a parallel bus. The size of the data bus determines the size of
the microprocessor. The 8085 microprocessor has 8-bit data bus and hence it is called an 8-
bit microprocessor. This refers to the width of the data bus but not the address bus.
Similarly8086 is a 16-bit microprocessor and its data bus width is 16 bits
INTEL 8085 has Address/ Data bus namely AD7-AD0. i.e. at some instances it acts as a
8- bit address bus and at other instances it works as a 8-bit data bus. INTEL used this time
multiplexing technique to save the pins. Generally the size of the internal general purpose
registers matches the size of the data bus
Thus, the INTEL’s 8-bit general purpose registers matches with its 8-bit data bus. The size of the
internal registers. So that all the bits on the bus can at one time come into or go out of any of
the registers.

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 The control bus of 8085 is a uni-directional bus because the microprocessor alone sends
control signals to memories or peripheral devices. The size of the control bus depends upon
the specific microprocessor. Typical control signals are Read or Write signals. It means
whether the microprocessor operation is a read or writes and whether it is memory or I/O
operation. In addition to this it includes state signals, and address latch enables. A
microprocessor may also have certain additional control signals and such as interrupt
signals, acknowledgement signals and hold signals. But they are not considered as part of
control bus even through they take part in control of microprocessor based systems.
The above three buses that interface the CPU to the system components are combinedly
known as the
System bus.

3.5 Interrupt structure of 8085

The 8085 microprocessor has five interrupts. They are TRAP, RST 7.5, RST 6.5, RST5.5 and
INTR. Among all these interrupts TRAP has the highest priority and INTR (Interrupt) has the
lowest priority. The TRAP is also a non maskable interrupt. The numbers succeeding the
RST (7.5, 6.5, and 5.5) are related to the call location. The various interrupts, their locations
in the order of highest to lowest priority are given in Table 3. . Here RST means RESTART.
Among these interrupts INTR is the only non-vector interrupt whereas the interrupts are
vectored interrupts.

TRAP: It is a non maskable interrupt with highest priority. It means that whenever the pin is
activated, the 8085 will always get interrupted even if the 8085 is in DI (Disable Interrupt)
state. Trap input is both edge and level sensitive. So, the microprocessor is interrupted when
the input is both edge and level sensitive. So, the microprocessor is interrupted when the
input pulse goes from low to high or when it remains high when interrupted, the
microprocessor loads the program counter with 0024H.

RST 7.5: It is an edge sensitive pin, Internal to 8085 there is a flip-flop connected to RST 7.5
interrupt pin . This flip flop is set 1, when a positive –going edge occurs on RST 7.5 input.
RST 7.5 interrupt has a higher
priority than RST 6.5, RST 5.5 and INTR. This RST 7.5 is a maskable interrupt known as MI. This
interrupt is enabled under program control with two instructions EI (Enable Interrupt) and SIM
(Set Interrupt Mask)

RST 6.5and RST 5.5: These interrupts level sensitive, it means the triggering level should be on
until the microprocessor completes the execution of the current instruction. If the
microprocessor is not able to respond to the requests immediately, they should be stored or
held by external hardware. These two interrupts are also maskable interrupts. RST 6.5 and
RST 5.5 have higher priority than INTR interrupt. The condition of these interrupts can be
known using RIM (Read Interrupt Mask) instruction and the condition of the masking interrupt
can be set and reset using SIM instruction (Set Interrupt Mask).

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INTR: It is only non-vectored interrupt in 8085 microprocessor. This interrupt has the lowest
priority among all the interrupts. This is also a maskable interrupt and can be disabled using
the instruction DI (Disable Interrupt). The mask on INTR can be removed by executing EI
(Enable Interrupt) instruction. When EI instruction is executed, the flip flop associated with
this is set and the mask is removed. This is a non-vectored interrupt because when the
remaining interrupts are initialized, they are automatically transferred (vectored) to specific
locations on memory page 00H without any external hardware. They do not require the
signal. The necessary hardware is already implemented inside the 8085. But coming
to INTR, interrupt, it executes interrupt acknowledge machine cycle. During this cycle, the
device that has interrupted this microprocessor will provide the operation code. The

signal works as a signal during acknowledge machine cycle. During this time, the
microprocessor loads the code into instruction register from I/O device. Based on the code,
the remaining operation is executed by the processor

S.N o Interrupts Call locations

1 TRAP (Top priority) 0024H

2 RST 7.5 (7.5 x 8)H = 003CH

3 RST 6.5 (6.5 x 8)H = 0034H

4 RST 5.5 (5.5 x 8)H = 002CH

INTR (least priority)

5 No location

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3.6 Pin configuration: The 8085 microprocessor is shown in Fig 3. . From the figure it is clear that it
is 40 pin DIP chip. The various pins of 8085 microprocessor can be grouped in the following categories
 Power Supply and Clock pins
 Data bus and Address bus
 Control and Status signals
 Interrupt signals
 DMA signals
 Serial I/O signals
The description of various pins is given below.

Power supply and clock pins

• Vcc: +5V power supply
• Vss: Ground reference.
• X1 and X2: A Crystal (or RC, LC Network) is connected at these two pins. The internal clock
generator divides oscillator frequency by 2, therefore to operate a system at 3MHZ, the crystal of
the tuned circuit should have a frequency of 6MHZ.
• CLK (OUT): This signal is used as a system clock for other devices. Its frequency is half the
oscillator frequency
Data bus and Address bus:
• AD0-AD7: These lines are Address/Data lines, which are bidirectional with dual purpose. They are
used as the low-order address bus as well as the data bus. During the first part of the machine cycle

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 (T1), lower 8 bits of memory address or I/O address appear on the bus. During the remaining part of
the machine cycle (T2,T3) these lines are used as a bi-directional data bus.
• A8-A0: These are the upper half of the 16 bit address lines. These lines are exclusively used for the
most significant 8 bits of the 16 bits of the16 bit address bus.
Control and Status Signals:
• ALE (Address Latch Enable): This is a positive going pulse generated every time the 8085 begins
an operation. The ALE=High indicates that the bits on AD7-AD0 are address bits. This signal is
mainly used to latch the low order address from the multiplexed bus and generate a separate set of
eight address lines (A7-A0)
• (Read): This is an active low read control pin. This signal indicates that the selected I/O or
memory device is to be read and data are available on data bus.
(Write): This is an active low write control pin. It indicates that the data on the data on the
data bus are to be are to be written into a selected memory or I/O location
• IO/ : This is a status signal used to differentiate between IO and memory operations. When it is
high, it indicates an I/O operation and when it is low, it indicates a memory operation. This signal
is combined with and signals to generate I/O and memory control signals.
• S1 and S0: These are status signals and they indicate the type of machine cycle in progress during
execution of an instruction.
• READY(Input): Through this pin, the microprocessor will know whether peripheral device is
ready or not for data transfer. If the device is not ready the processor waits. So, this pin helps to
synchronize slow devices to the microprocessor.
Interrupt signals:
TRAP, RST 7.5, RST 6.5, RST5.5 and INTR: These are the interrupt signals which are externally initiated.
• INTR (Interrupt Request): This is used as a general purpose interrupt. It has a lowest priority and it
is the only non-vectored interrupt.
• RST 7.5: It is a restart interrupt pin. It has higher priority than RST 6.5, RST5.5 and INTR. It is a
maskable vectored interrupt.
• RST 6.5 and RST5.5: These two are maskable vectored interrupt with higher priority than INTR.
• TRAP: It is a non-maskable vectored interrupt. It has higher priority.
• (Output): It is an active low interrupt acknowledge pin. This will acknowledge the receival of
interrupt request to the peripheral device.
DMA Signals:
• Hold: This pin is used during the Direct Memory Access. A high on this pin indicates that, a
peripheral like DMA controller is requesting the use of address and data buses.
• HLDA (Output): A high on this p in acknowledges the hold request from peripheral.
• : It is an active low signal. When the signal on this pin goes low, the system is in reset i.e.
the program counter is set to zero, the address & data buses are tristated.

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 • RESETOUT: This signal is used to Reset other devices in microprocessor system.
Serial input/ Output signals:
• SID: Serial input Data is a pin through which serial data are brought into the micro processor
accumulator after the RIM instruction is executed.
• SOD: Serial output Data pin is used by the microprocessor to output data serially to the external
devices. Serial data is sent out of the microprocessor by executing SIM instruction. The most
significant bit of accumulator should have the serial bit and D6 bit of the accumulator must be made
high to enable the serial data transfer.

Stack and Subroutines: Stack is a set of memory locations in the Read/Write memory which is
used for temporary storage of binary information during the execution of a program. It is
implemented in the Last-in-first-out (LIFO) manner. i.e., the data can be written first can be
accessed last, one can put the data on the top of the stack by a special operation known as PUSH.
Data can be read or taken out from the top of the stack by another special operation known as
POP.
Stack is implemented in two ways. In the first case, a set of registers is arranging in a shift
register organization. One can PUSH or POP data from the top register. The whole block of data
moves up or down as a result of push and pop operations respectively. In the second case, A block
of RAM area is allocated to the stack. A special purpose register known as stack pointer (SP)

16
points to the top of the stack. Whenever the stack is empty, it points to the bottom address. If a
PUSH operation is performed, the data are stored at the location pointed to by SP and it is

decremented by one. Similarly if the POP operation is performed, the data are taken out of the
location pointed at by SP and SP is incremented by one. In this case the data do not move but SP
is incremented or decremented as a result of push pop operations respectively.
Application of Stack: Stack provides a powerful data structure which has applications in many
situations. The main advantage of the stack is that,
1. We can store data (PUSH) in it with out destroying previously stored data. This is not true
in the case of other registers and memory locations.
2. stack operations are also very fast
3. The stack may also be used for storing local; variables of subroutine and for the transfer of
parameter addresses to a subroutine. This facilities the implementation of re-entrant
subroutines which is a very important software property.
The disadvantage is, as the stack has no fixed address, it is difficult to debug and document a
program that uses stack.
Stack operation: Operations on stack are performed using the two instructions namely PUSH and
POP. The contents of the stack are moved to certain memory locations after PUSH
instruction. Similarly, the contents of the memory are transferred back to registers by POP
instruction.
For example let us consider a Stack top is 4506 H. This is stored in the 16-bit Stack
pointer register

Let us consider two registers (register pair)

B & C whose contents are 25 & 62.

Reg. B Reg. C

25 62

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After PUSH operation the status of the Stack is as shown below

Let us now consider POP operation.

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Programming Example:

1. Write a program to initialize the stack pointer (SP) and store the contents of the register pair
H-L on stack by using PUSH instruction. Use the contents of the register pair for delay counter
and at the end of the delay retrieve the contents of H-L using POP.

Program:

Memory Label Mnemonics Operand Comment

Location
8000 LXI SP, 4506 H Initialize Stack
pointer
8003 LXI H,2565 H

8006 PUSH H
8007
| DELAY CALL Push the
| contents.
800A POP H

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Subroutine: It I a set of instructions written separately from the main program to execute a
function that occurs repeatedly in the main program.
For example, let us assume that a delay is needed three times in a program. Writing
delay programs for three times in a main program is nothing but repetition. So, we can write a
subroutine program called ‘delay’ and can be called any number of times we need.
Similarly, in 8085 microprocessor we do not find the instructions for multiplication and
division. For this purpose we write separate programs. So, in any main program if these
operations are needed more than once, the entire program will become lengthy and complex.
So, we write subroutine programs MUL & DIV separately from main program and use the
instruction CALL MUL (or) CALL DIV in the main program. This can be done any number of
times. At the end of every subroutine program there must be an instruction called ‘RET’. This
will take the control back to main program.
The 8085 microprocessor has two instructions to implement the subroutines. They are
CALL and RET. The CALL instruction is used in the main program to call a subroutine and
RET instruction is used at the end of the subroutine to return to the main program. When a
subroutine is called, the contents of the Program Counter, which is the address of the
instruction following the CALL instruction is stored on the stack and the program execution is
transferred to the subroutine address. When the RET instruction is executed at the end of the
subroutine, the memory address stored on the stack is retrieved and the sequence of
execution is resumed in the main program.
Diagrammatic representation:
Let us assume that the execution main program started at 8000 H. It continues
until a CALL subroutine instruction at 8020 H. Then the program execution transfers to 8070
H. At the end of the subroutine 807B H. The RET instruction is present. After executing this
RET, it comes back to main program at 8021 H as shown in the following figure.

The same is shown by the assembly language program example.

Program Example:

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Memory Mnemonics Operand Comments
Address

8000 LXJ SP, 8400 H Initialize the Stack pointer at 8400 H

|
|
|
8020 CALL 8070 H Call a subroutine program stored at the
8021 location 8070 H. (It is a three by
8022 Instruction)
8023 Next instruction The address of the next instruction
| | following CALL instruction.
| |
| | End of the main program
802F HLT .

Subroutine Program:

Memor Mnemonics Operand Comments

y
Addres
s
8070 Instructions Beginning of the Subroutine.
|
|
|
|
807B RET End of the program

807C Next Subroutine Instructions of next subroutine if

any

807F RET End of the subroutine.

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 INSTRUCTION CYCLE:
An instruction is a command given to the microprocessor to perform a specific operation on the
given data. Sequence of instructions written for a processor to perform a particular task is called
a program. Program & data are stored in the memory. The microprocessor fetches one
instruction from the memory at a time & executes it. It executes all the instructions of the program
one by one to produce the final result. The necessary steps that a microprocessor carries out to
fetch an instruction & necessary data from the memory & to execute it constitute an instruction
cycle.
In other words, an instruction cycle is defined as the time required completing the
execution of an instruction.
An instruction cycle consists of a fetch cycle and an execute cycle. The time required to fetch an
opcode (fetch cycle) is a fixed slot of time while the time required to execute an instruction
(execute cycle) is variable which depends on the type of instruction to be executed.

Instruction cycle(IC) = Fetch cycle(FC) + Execute cycle(EC)

This is shown diagrammatically below.

FETCH OPERATION:
The first byte of an instruction is its opcode. An instruction may be more than one byte long. The
other bytes are data of operand address. The program counter (PC) keeps the memory address
of the next instruction to be executed. In the beginning of a fetch cycle the content of the program
counter, which is the address of the memory location where opcode is available, is sent to the
memory. The memory places the opcode on the data bus so as to transfer it to the
microprocessor. The entire operation of fetching an opcode takes three clock cycles.
EXECUTE OPERATION:
The opcode fetched from the memory goes to the instruction register (IR). From the instruction
register it goes to the decoder circuitry which decodes the instruction. After the instruction is
decoded, execution begins. If the operand is in general purpose registers execution is
immediately performed.
The time taken for decoding and execution is one clock cycle. If an instruction contains data or
operand and address which are still in the memory, the microprocessor has to perform some
read operations to get the desired data. After receiving the data it performs execute operation. A
read cycle is similar to a fetch cycle. In case of a read cycle the quantity received from the
memory are data or operand address instead of an opcode. In some instructions write operation
is performed. In write cycle data are sent from the microprocessor to the memory or an output
device. Thus we see that in some cases an execute cycle may involve one or more read or write
cycles or both.

MACHINE CYCLE:

Machine cycle is defined as the time required for completing the operation of accessing either
memory or I/O. In the 8085, the machine cycle may consist of three to six T states. The T-state
is defined as one sub-division of the operation performed in one clock period. These sub-
divisions are internal states synchronized with the system clock.

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Timing Diagram for Memory Read Machine Cycle

Timing Diagram for Opcode Fetch Machine Cycle.

26
Timing Diagram for I/O Read Machine Cycle

27
Timing Diagram for Memory Write Machine Cycle

28
Timing Diagram for I/O Write Machine Cycle

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ALGORITHMS

The step by step procedure written in detail without computer commands in a simple language
(normally English) to solve a given problem is known as Algorithm. For this, first the given
problem is divided into small steps in terms of the operations the 8085 can perform (called
modules) without using the instructions. Finally the modules are added to develop the
complete program.The Important characteristics of the algorithms are (i) Algorithms are well
defined.(ii) Algorithms produce a specific result (iii) Every algorithm terminates in a finite
number of steps.
Advantages of Algorithms : i) Algorithms are independent of any computer language. ii)
Algorithms are easy to follow by any one who reads. iii) Useful to debug the program , since
every step has got its own logical sequence. iv) Algorithms can be easily converted into
flowcharts and then into computer programs.

FLOWCHARTS

The most common way of representing the sequence of steps of a program in a pictorial format
is known as flow chart. The First flowchart was made by John Von Newman in 1945.The
flowchart is used for two purposes.One is to help the reader to under stand the logic and
objective of any program and the other is to debug the program easily if the expected result
is not achieved..The below figures shows the commonly used flow chart symbols.

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32
Differences between static and dynamic RAMs:

Static RAM Dynamic RAM

1. This semiconductor memory is 1. This semiconductor memory is

constructed using bipolar constructed using MOS transistors
transistors
2. Information is stored in the form 2. Information is stored in the form of
of voltage levels in flip-flops electrical charges in capacitors
3. These voltage levels do not get 3. Has tendency of leakage
drifted away
4. No refresh logic is needed 4. Refresh logic is necessary since
leakage of electrical charges
5. Power is required even when the 5. Refresh login is inbuilt, so draws
chip is in standby mode less power comparatively.

6. Four time larger in size compared 6. Four times as many bits as a static
to an equivalent dynamic cell RAM chip.

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