c


m A RS-flipflop is the simplest possible memory element.

m t is constructed by feeding the outputs of two NOR gates back to the other NOR gates
input.
m he inputs R and S are referred to as the Reset and Set inputs, respectively.
m o understand the operation of the RS-flipflop (or RS-latch) consider the following
scenarios:
? 


c  he output of the bottom NOR gate is equal to zero, Q'=0.
? Gence both inputs to the top NOR gate are equal to one, thus, Q=1.
? Gence, the input combination S=1 and R=0 leads to the flipflop being set to Q=1.
? 


c  Similar to the arguments above, the outputs become Q=0 and
Q'=1.
? ^e say that the flipflop is reset.
? 


c  Assume the flipflop is set (Q=0 and Q'=1), then the output of the
top NOR gate remains at Q=1 and the bottom NOR gate stays at Q'=0.
? Similarly, when the flipflop is in a reset state (Q=1 and Q'=0), it will remain there
with this input combination.
? herefore, with inputs S=0 and R=0, the flipflop remains in its state.
? 


c  his input combination must be avoided.
m ^e can summarize the operation of the RS-flipflop by the following truth table.

R S Q Q' Comment
0 0 Q Q' Gold state
0 1 1 0 Set
1 0 0 1 Reset
1 1 ? ? Avoid

m Note, the output Q' is simply the inverse of Q.

m An RS flipflop can also be constructed from NAND gates.


  RS Flip-Flop composed of two NOR Gates.

£


m An RS-flipflop is rarely used in actual sequential logic.
m Gowever, it is the fundamental building block for the very useful D-flipflop.
m he D-flipflop has only a single data input.
m hat data input is connected to the S input of an RS-flip flop, while the inverse of D is
connected to the R input.
m his prevents that the input combination ever occurs.
m o allow the flipflop to be in a holding state, a D-flip flop has a second input called
``Enable.''
m he Enable-input is AND-ed with the D-input, such that when Enable=0, the R and S
inputs of the RS-flipflop are 0 and the state is held.
m ^hen the Enable-input is 1, the S input of the RS flipflop equals the D input and R is the
inverse of D.
m Gence, the value of D determines the value of the output Q when Enable is 1.
m ^hen Enable returns to 0, the most recent input D is ``remembered.''


  D Flip-Flop.




m ]emory elements can be constructed by appropriately feeding back the output of gates to
the input.
m he most basic memory element is an RS flip flop which consists of two NOR gates.
m Vy adding two more gates (and an inverter) we can construct a D-flipflop.
m he D-flipflop has an Enable input and a data input.
m ^hen the Enable input is 1, the data input is read into the flipflop.
m ^hen the Enable input is 0, the currently stored value is held regardless of the data input.
m D-flipflops can be used to construct sequential logic circuits such as counters or shift-
registers.

The JK Flip-Flop

o prevent any possibility of a "race" condition occurring when both the S and R
inputs are at logic 1 when the CLK input falls from logic 1 to logic 0, we must
somehow prevent one of those inputs from having an effect on the master latch in the
circuit. At the same time, we still want the flip-flop to be able to change state on each
falling edge of the CLK input, if the input logic signals call for this. herefore, the S or
R input to be disabled depends on the current state of the slave latch outputs.

f the Q output is a logic 1 (the flip-flop is in the "Set" state), the S input can't make
it any more set than it already is. herefore, we can disable the S input without
disabling the flip-flop under these conditions. n the same way, if the Q output is logic
0 (the flip-flop is Reset), the R input can be disabled without causing any harm. f we
can accomplish this without too much trouble, we will have solved the problem of the
"race" condition.
 he circuit below shows the solution. o the RS flip-flop we have added two new
connections from the Q and Q' outputs back to the original input gates. Remember that
a NAND gate may have any number of inputs, so this causes no trouble. o show that
we have done this, we change the designations of the logic inputs and of the flip-flop
itself. he inputs are now designated J (instead of S) and K (instead of R). he entire
circuit is known as a 
.

n most ways, the JK flip-flop behaves just like the RS flip-flop. he Q and Q'
outputs will only change state on the falling edge of the CLK signal, and the J and K
inputs will control the future output state pretty much as before. Gowever, there are
some important differences.

Since one of the two logic inputs is always disabled according to the output state of
the overall flip-flop, the master latch cannot change state back and forth while the CLK
input is at logic 1. nstead, the enabled input can change the state of the master latch

, after which this latch will not change again. his was not true of the RS flip-flop.

f both the J and K inputs are held at logic 1 and the CLK signal continues to
change, the Q and Q' outputs will simply change state with each falling edge of the
CLK signal. (he master latch circuit will change state with each  edge of CLK.)
^e can use this characteristic to advantage in a number of ways. A flip-flop built
specifically to operate this way is typically designated as a  (for  
) flip-flop. he
lone  input is in fact the CLK input for other types of flip-flops.

he JK flip-flop  be edge triggered in this manner. Any level-triggered JK latch

circuit will oscillate rapidly if all three inputs are held at logic 1. his is not very
useful. For the same reason, the  flip-flop must also be edge triggered. For both types,
this is the only way to ensure that the flip-flop will change state only once on any
given clock pulse.
 Vecause the behavior of the JK flip-flop is completely predictable under all
conditions, this is the preferred type of flip-flop for most logic circuit designs. he RS
flip-flop is only used in applications where it can be guaranteed that both R and S
cannot be logic 1 at the same time.

At the same time, there are some additional useful configurations of both latches
and flip-flops. n the next pages, we will look first at the major configurations and note
their properties. hen we will see how multiple flip-flops or latches can be combined
to perform useful functions and operations.

The T Flip-Flop
he  or
"toggle" flip-
flop changes
its output on
each clock Index
edge, giving
an output
Electronics
which is half
the frequency concepts
of the signal
to the  Digital
input. circuits
It is useful for constructing binary counters, frequency dividers, and general binary
addition devices. It can be made from a J-K flip-flop by tying both of its inputs high. Sequential
Operations

Construction of  flip-flop from a

J-K flip-flop.

Flip-Flops

Go Back
 c
GyperPhysics*****Electricity and magnetism




e Detector Circuits

Flip-Flops

Introduction
Timing plays a crucial role, not only in sports like cricket but also in digital electronic
equipments like microprocessors. Timing and Timing diagram plays a vital role in
microprocessors.
^ at is a timing diagram? ^ at role it plays wit respect to microprocessors? Let¶s
discuss about t ese concepts in detail.

^
t is
Timing Di
gr
m?
T e timing diagram is t e diagram w ic provides information about t e various
conditions of signals suc as ig
low, w en a mac ine cycle is being executed.
^it out t e knowledge of timing diagram it is not possible to matc t e perip eral
devices to t e microprocessors. T ese perip eral devices includes memories, ports etc.
Suc devices can only be matc ed wit microprocessors wit t e elp of timing
diagram.

Before dealing wit timing diagram, we ave to make ourselves familiar wit certain
terms.

Instruction cycle:

Assume t at t e microprocessor is executing an instruction. Instruction cycle is not ing

but t e time taken to complete t e execution of t at instruction by t e microprocessor.
T e 8085 instruction cycle consists of 1 to 6 mac ine cycles.

M
c ine Cycle:

Mac ine cycle is not ing but t e time required to complete one operation of accessing
memory, I
. It is also t e time required to complete one operation of acknowledging an
external request. ne mac ine cycle may consist of 3 to 6 T-states.

T-st
te:

T-state is not ing but one subdivision of t e operation performed in one clock period.
T ese subdivisions are internal state of t e microprocessor sync ronized wit system
clock.

Now let us discuss t e timing diagram for various signals t at are associated wit 8085
microprocessor.
Timing di
gr
m of v
rious sign
ls
Address l
tc en
le:

Address latc enable is an active ig signal. (i.e.) t e latc becomes enabled w en t e

signal is ig . It is activated during t e beginning of T1 state of eac mac ine cycle and
it remains active in t e T1state. But in case of bus idle mac ine cycle it is not activated.

D
t
Bus (D0-D7):

^ ile dealing wit data bus, two types of data flow are possible. T e data can be
transferred from memory to microprocessor and vice versa.

T is process occurs during t e T2 and T3 states.

T ere are 2 cycles. ne is Read mac ine cycle and t e ot er is write mac ine cycle. In
read mac ine cycle, t e data will appear during t e later part of T2 state, w ile in ^rite
mac ine cycle t e data will appear on t e beginning of T2 state.

But for reading a data from memory or I
 device, first we need to select t e required
device. After selecting t e device, t e required data to be read or written is taken from
t e selected location and placed on data bus. A certain amount of time is required to
perform t is action. T is time is called ³access time´. But for write cycle t e access time
is 0. T is is because t e data to be written is present on t e registers of microprocessor
and so it can put t e data directly to data bus wit out any time delay.

Lower yte
ddress (A0-A7):

T e lower byte of address is available on t e time multiplexed address
date bus during
t e T1 state of mac ine cycle, except t e bus idle mac ine cycle.

Gig er yte
ddresses (A8-A15):

T e ig er byte addresses (A8-A15) is available for T1, T2 and T3 states of eac

mac ine cycle, except t e bus idle mac ine cycle.

IO/M¶, S0, S1:

From t e previous discussions about 8085 microprocessor, we very well know t at

I
M¶, S0, S1 are t e status signals of t e microprocessor. T ese status signals decide
t e type of mac ine cycle is to be executed. So t ey remain activated from t e
beginning T1 state of a particular mac ine cycle and remains till t e end of t at mac ine
cycle.

RD¶
nd ^R¶:

T ese 2 signals RD¶ and ^R¶ decides t e direction of t e data transfer.

RD¶ is Active: ^ en RD¶ goes active, t e data is transmitted from memory, I
 device or
any ot er perip erals to t e microprocessor.

^R¶ is active: ^ en ^R¶ goes active, t e data is transmitted from microprocessor to

t e memory or any ot er perip eral devices.

Now t ere mig t be a question arising wit in your mind.

Can bot t e signals become active at same time? T e answer for t is question is N.
In 8085 microprocessor eit er RD¶ goes ig or ^R¶ goes ig . Bot cannot take place
at same time.

T e data transfer bot RD¶ and ^R¶ takes place during T2 and T3 states of mac ine
cycle. So t ese signals are activated during t e T2 and T3 states.

In t e next article let us explore t e various types of mac ine cycles t at are used in
timing diagram.

Im
ge Courtesy:

"Microprocessor and Its applications" by Mano aran

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