Low Voltage Analog Circuit Design Techniques:

A Tutorial

IEEE Dallas CAS Workshop 2000 March 27, 2000

Edgar Sánchez-Sinencio http://amsc.tamu.edu/

Texas A&M University

Analog and Mixed-Signal Center

Low Voltage Analog Circuit
Design Techniques: Roadmap
Low voltage (LV) power supply circuit design
techniques are addressed in this tutorial. In
particular:
(i) Introduction;
(ii) Transistor models capable to provide performance
and power consumption tradeoffs;
(iii) Low voltage implementation techniques, such as
floating gates and bulk driven;
(iv) Basic building blocks not involving cascode
structures, and
(v) LV circuit implementations examples.
Analog and Mixed-Signal Center, TAMU
 Motivation
The need for analog circuits in modern mixed-signal VLSI
chips for multimedia, perception, control, instrumentation
medical electronics and telecommunication is very high.

• What are the challenges in designing low voltage circuits ?

- To operate with power supplies smaller than 3.3 volts
- To design circuits with the same performance or better
than circuits designed for larger power supplies
- To perform with technologies smaller than 0.5 micron
-To come with new design alternatives,
Analog and Mixed-Signal Center, TAMU
 ( continues)

• Why are we concerned in designing low voltage circuits ?

- Designers can not use conventional cascode structures, and
other conventional design methodologies.
- Circuits should have the same performance or better than
circuits designed for larger power supplies
- Circuit performance with technologies smaller than 0.5um
must be better than circuits for larger technologies.
-Third-generation communication applications require circuits
( and systems) with improved dynamic range over a much
wider bandwidth.
- New building blocks and system must be designed to satisfy
the needs of portable, lighter and faster equipment

Analog and Mixed-Signal Center, TAMU

Issues about low power supply voltage
Scaling down size technology and
supply voltage does not scale linearly
VTH the “ VTH hat ”

VTH

Mister 5 volts IC Mister 0.8 volts IC

• Threshold and VDSAT do not scale down linearly with power
supply nor with smaller size technologies.

• Let us consider an illustrative example of a cascode and a

simple inverting amplifiers, assume transistors MC and MS carry
the same current IL, VT= 0.75V and VDS(SAT)=0.2V
• Keeping the same output voltage swing for both circuits
involve the tradeoffs shown in the plot of transistor sizes and
GBW vs. Power Supply Voltage
• How to determine how much bias current is needed for
certain application ?

• When a designer operates transistors in saturation,

what does it mean VDS > VDS(SAT) ?

• Can a circuit have their transistors operating in the transition

region ? What transistor model equation can be employed ?
 One Equation-All Regions Transistor Model
• Features of ACM model:
– physics-based model,
– universal and continuous expression for any inversion,
– independent of technology, temperature, geometry and gate voltage,
– same model for analysis, characterization and design.
• Main design equations: (design parameters: I, gm, if)
I 1 + 1 + if I  drain current in transistor
=
f t g m n 2 gm  transconductance in saturation
n  slope factor
mf t
fT = 2( 1 + i f −1) ft  thermal voltage
2pL2
if  inversion level of the transistor defined as
W gm 1
= if = I I s , where I = mnC f W 2

m Coxf t 1 + i f −1
t
L s ox
is the normalization current. 2 L
VDSAT
≅ ( 1 + i f − 1) + 4
ft if << 1  weak inversion,
W
=
gm if >> 1  strong inversion.
L  I 
2 mC oxft  − 1
 ft g m n 
 Normalized Current Transconductance-to-Current Ratio

ID φ t ng m 2
if = =
IS ID 1 + 1 + id
2
ftW
IS ′
= m n Cox φ tgm
2 L 0
I D 10
ID: saturation current

IS: normalization current

n: slope factor -1
10

( ) theory (n=1.35)
( ) simulation
(o o o o o o) experiment

-2
10
10-2 10 -1 10 0 10 1 10 2 103 10 4
i
WI MI SI

Analog and Mixed-Signal Center, TAMU

The intrinsic cutoff frequency Drain-to-source saturation voltage
f o 2( 1 + i f )
fT ≅ −1 VDSsat
≅ ( 1+ if )
−1 + 4
mf t ft
fo = 2
2p L

3 3
10 10
fT VDSsat
fo 2 φt
10

2
10
1
10

0
10
1
10

-1
10

-2 0
10 10 -2 -1 0 1 2 3 4
-2 -1 0 1 2 3 4
10 10 10 10 10 10 10 10 10 10 10 10 10 10
id id

WI MI SI WI MI SI

Analog and Mixed-Signal Center, TAMU

 Correlation Between Area and Frequency Response

CL GBW
WL ≅ 2
C′ox fT

Correlation Between Junction Capacitance (CJ) and Frequency Response

Parasitic capacitance α GBW/fT

CJ CJ′ L DIF GBW
CJ = CJ ′ ⋅ W ⋅ L DIF LDIF ≅ 2
CL C′ox L fT
W
CJ

Analog and Mixed-Signal Center, TAMU

 BIPOLAR MOS

IBIAS=IC IBIAS=I D

DC Circuit +
CL +
VO
CL +
VO
+
VI - -
VI
- -

Transconductance gm 1 gm 1  2 
-to-current-ratio = =  
(gm/ID) IC φt ID φ t  n(1 + 1 + i d ) 

DC Gain VA VA  2 
A vo = − A vo = −  
(Avo) φt φ t  n(1 + 1 + i d ) 

Gain-Bandwidth 1 IC 1 ID  2 
GBW = GBW =  
Product (GBW) 2π CL φ t 2π CL φ t  n(1 + 1 + i d ) 


Intrinsic Cutoff fT ≅
1
fT ≅
1
2( 1 + i d − 1)
Frequency (f T) 2πτ 2πτ
Minimum Output VDSsat
( 1 + i d − 1) + 4
VCEsat
≅ 6 to 8 =
Voltage (VO) φt φt
Low Voltage Analog Circuit
Design Techniques: Roadmap
Low voltage (LV) power supply circuit design techniques are addressed in
this tutorial. In particular:

(i) Introduction;

(ii) Transistor models capable to provide performance and power

consumption tradeoffs;

(iii) Low voltage implementation techniques, such as

floating gates, self-cascode, low voltage
current-mirrors and bulk driven;
(iv) Basic building blocks not involving cascode structures, and

(v) LV circuit implementations examples.

Analog and Mixed-Signal Center, TAMU
 Floating Gate Transistors

The floating gate voltage VF ,assuming that the initial charge QF in the floating gate is zero,,is
described by:

VF = w0V0 + w1V1+ w2V2 + ….. + wnVn

Where wi = Ci/CTOT
CTOT = C0 + C1 + C2 +….+ Cn

Metal Poly II
Poly I CFGD
VG1 CG1
VG1 VG1
VG2 VG2 CG2
VG2
VG3
CGn
VGn VGn
CFGS
S D
CFGB
N Diffusion
(a) Layout (b) Schematic Symbol (c) Equivalent Circuit
 Floating Gate MOS Transistors
CG (control Gate)
Poly - I
Cg
Poly - II
CO = Cgs + Cgb + Cgd
S D
CT= CO + Cg

Assuming Cg >> Cgd,Cgb, an approximate IDS can be obtained:

IDS=Koeff [( VCGS-VT,eff)VDS-CT VDS2/2Cg] ohmic
IDS =Kseff ( VCGS-VT,eff)2 saturation
Where: VT,eff =VTCO - QFG/Cg

Koeff = Kp(Cg/CT)(W/L), Kseff =Kp(Cg/CT)2(W/L),

What is the effect of the FG on the transconductance and the
output conductance, in the saturation region ?

gm = ( 2K2eff IDS)2 = Cg gcm/CT

go = gco + Cgd gm/Cg

Where gcm and gco are the conventional transconductance

and the output conductance of the conventional MOS transistor.

Thus, the FGT has a smaller transconductance

and a larger output conductance than conventional
MOS transistor

Analog and Mixed-Signal Center, TAMU

What is a Self-Cascode Composite Transistor?
D
D

M2 G
m W/L
G
X
W/L
M1 S

S
(a) Self-Cascode Composite NMOS Transistor (b) Equivalent Simple Transistor

In practical cases, for optimal operation the W/L ratio of M2 should be larger
than that of M1, i.e. m>1.
The 2-transistor structure can be treated as a composite transistor, which has
a much larger effective channel length (thus lower output conductance).
The lower transistor M1 is equivalent to a resistor, but this resistor is input dependent..
The effective transconductance of the composite transistor is approximately
equal to the transconctance of M1:gm-eff =gm2/m=gm1
 Equivalent Transistor Parameter
For the composite transistor work in saturation region, we know M2 should
in saturation and M1 is in linear region. Thus, we can write equations for these
two transistors as:
b2  1 
i1 = (VGS − VX − VT )2
i1 = b 1  GS
V − VT − VX V X
2  2 

Solving i1 we can obtain:

1 b 2b 1
i2 = (VGS − VT )2
2 b 2 + b1
b 2b 1
From (3), we have b eq =
b 2 + b1

m 1
If b2 = m ⋅ b1 b eq = b1 = b2
m+1 m+1
b eq = b1
m− >∞
 Comments on VDSAT
Because transistor M1 always operates in linear region while the top
transistor operates in saturation or linear region. Voltage between the source
and drain terminal of M1 is so small that there is no discernable VDSAT
difference in both the composite and simple transistors. Thus,self-cascode
structure can be used in low voltage applications.

VDSAT − eq = VDSAT − M 2 + VDS − M 1 = VDSAT − M 2 + I D 2 RM 1

1
RM 1 =
where W
mCOX (VGS − VT )
L
The operating voltage of a regular cascode circuit is much higher than that of
a single transistor. This characteristic makes regular cascode circuit not suitable
for low voltage applications.
 References
1. C. Galup-Montoro, etc., “Series-Parallel Association of FET’s for
High Gain and High Frequency Applications”, IEEE JSSC, Sept. 1994
2. D. Ceuster, etc., “Improvement of SOI MOS current-mirror
performances using serial-parallel association of transistors”, Electronics
Letters, Feb. 1996
3. P. Furth, H. Om’mani, “A 500-nW Floating-Gate Amplifier with
Programmable Gain”, IEEE 1999
4. I. Fujimori, T. Sugimoto, “A 1.5V, 4.1mW Dual-Channel Audio
Delta-Sigma D/A Converter”, IEEE JSSC, Dec. 1998
5. Personal note from Dr. Ugur Cilingiroglu

6. Yunchu Li, examples and SPICE tables

7. A.I.A. Cunha, M.C. Schneider, and C. Galup-Montoro, “An MOS transistor model
for analog circuit design”, IEEE J. Solid-State Circuits, vol. 33, No. 10, pp 1510-
1519, Oct. 1998
Potential LV Current-Mirrors
Goals: To reduce the input impedance and to increase the output impedance,
while keeping the voltage operation

M2 Iout Iin Vref Iout

Iin
Mc Aact
Vcas
M1 M2
M1 Mm

Iout
Iin Iout
Iin Vref Vref
Mc
M2 Mc
Mm
M1 Mm
M1 Vmirror
 Iout
Iout IB IB Iin Iout
IB IB Iin
Iin M5
Vcas M2 M4
M2 M2 M4 X
M1 M3 M1 M3 M1 M3

Vshift Vdd
Iin Iin IB1 Iin Iout
Iout M3 M4 Iout
ROB
AFB
M1 M2
M1 M2 M1 M2
IB2
How can we obtain a large impedance and low head room
for the tail current used in a differential pair ?

Vdd LV CURRENT-SOURCE

Z
M2 M1 Vx

A R0S
X − + Y I

I R0B
IB
R0S (b)
(a)

A conceptual Schematic of the low voltage current source. (a) Current source representation
(b) Architecture
Analog and Mixed-Signal Center (AMSC) TAMU
 1 + g m1A o /(g o1 + g oB)
R os = (1)
g o 2(1+ Ao g m1 /( g o1 + g ) − A og m 2 / g o 2 )
oB

where g m1 (g m 2 ), g o1(g o2 ) are the transconductance and output conductance of M1 (M 2 ) ,

respectively. Ao is the DC gain of the error amplifier “A” and g oB ( R oB ) is the output

conductance (resistance) of the reference current source I B. Assuming that g m1 = g m 2 and

g o1 = g o 2 , equation (1) can be simplified as:

R os ≈ − R oB (2)

Note that the resistance is negative and is equal to the resistance of the reference source IB.
gm4
R os ≈ − (3)
g o3g o 4

Analog and Mixed-Signal Center (AMSC) TAMU

 Vdd

Z
M2 M1

Y
Io
R 0S
M4 Vb
Vdd

IB ID
Z
M2 M1

−
A
+ Y
M3
X

I
V
IB R0B

R0S
Current Ref. Error Amplifier A
(a) Vss
Full implementation of the LV current source.
Analog and Mixed-Signal Center (AMSC) TAMU
Measured output current of the simple (curve A) and LV (Curve B) current source.

Analog and Mixed-Signal Center (AMSC) TAMU

 Bulk-Driven MOS Transistor
Characteristics
• ID vs. VBS or VGS of bulk-driven and conventional gate-driven MOS
transistors
8mA

6mA
1.5V Drain Current
ID
4mA
Bulk-Source
VGS VBS Driven

2mA
Gate-Source
Driven

0mA
-3V -1.5V 0V 1.5V 3V
Gate-Source or Bulk-Source Voltage
 Overhead of Bulk-Driven MOS Transistors

Ib1 Ib2 Ib1 Ib2

Vx Vout Vy Vout

M1 M2
M1 M2
Vin Vb Vb Vin Vin

Vdd Vdd
Vdsat,Ib1 Vdsat,Ib1
SRVX, Swing range
Swing range of Vy
of Vx
Vdsat,M1 (a) VGS,M2 (b)
-Vss -Vss
SRVY=Vsup -Vdsat,Ib1 -VGS,M2
SRVX=Vsup-Vdsat,Ib1-Vdsat,M1 = Vsup-Vdsat,Ib1-Vdsat,M2-VT
The bulk-driven amplifier is more suitable for low voltage operation. Please
notice that the maximum allowable voltage at Vx is VDIODE.
 Advantages of Bulk-Driven MOS
Transistors
• The depletion characteristic allows zero, negative, and even small
positive values of bias voltage to achieve the desired dc current. This
can lead to larger input common mode voltage range and voltage
swing that could not otherwise be achieved at low power supply
voltages. ( Please refer the following example in this section and bulk-
driven differential pair discussed in following sections )
• We can use the conventional gate to modulate the bulk-driven MOS
transistor.

• Example
Assume for the low voltage amplifiers, power supply voltage is
Vsup = Vdd+|Vss|<V DIODE+Vdsat ,
where VDIODE is the forward Si diode cut-in voltage.
The voltage swing of Vx ( Figure a, the amplifier with bulk-driven MOS
FETs ) has only 2Vdsat’s decrease over Vsup. In such a low voltage, the
conventional gate-driven amplifier ( Figure b ) fails to operate or may be
greatly limited in voltage swing.
 Disadvantages of Bulk-Driven MOS
Transistors
• The transconductance of a bulk-driven MOS FET is substantially
smaller than a conventional gate-driven MOS transistor. This may
result in lower GBW and worse frequency response, but better
linearity and smaller power supply requirements.
• For a conventional gate-driven MOSFET, the frequency response
capacity is described by its transitional frequency, fT,
gm
fT , gate − driven =
2p C gs
• For the bulk-driven MOSFET, fT is given by
g mb h gm
fT ,bulk − driven = =
2p (Cbs + Cbsub ) 2p (Cbs + Cbsub )

where h is the ratio of g mb to g m and typically has a value in the range

of 0.2 to 0.4.
Disadvantages of Bulk-Driven MOS Transistors
( cont’d )
• For typical saturated strong inversion MOSFET operation, the
following approximation stands,
h
f T ,bulk − driven ≈ f T , gate − driven
3.8

• Another disadvantage of bulk-driven MOSFETs is that the polarity of

the bulk-driven MOSFETs is process related. For an P well CMOS
process, we only have N channel bulk-driven MOSFETs available, and
for N well CMOS process, only P channel MOSFETs. This limits its
application. We can not use bulk-driven MOS transistors in some
circuit structures which requires both N and P MOSFETs.
Disadvantages of Bulk-Driven MOS Transistors
( cont’d )
• MOS transistors can be laid out in the same well, thus their
characteristics will match better. Bulk driven transistors are in
differential wells, it is inconvenient to design some circuits which
require tight matching between transistors. For bulk-driven MOSFETs,
it is not easy to utilize some layout techniques such as interdigitized
and common centroid layout to make good matching.

• Potentials to turn on the parasitic BJT transistors which may result in

latch-up problem

• The equivalent noise of a bulk-driven MOS amplifier is larger than a

conventional gate-driven MOS amplifier.
 Example of OTAs using different approaches:
Conventional, Current Divider-Source Degeneration
(CD-SD), Floating Gate, and Bulk Driven

GM VOUT = GMROUTVIN
VIN
VDD
IOUT
ROUT = 8.3 Mohms
1.2 AMI Technology M7 M8

Vdd=-Vss= 1.35V M9 M10

RBIAS
VOFFSET ISS

IBIAS VSS
Vout

VBIAS Vi- M1 M2 Vi+

M3 M4
M5 M6

VSS
EXPERIMENTAL TEST SETUP
DESIGN A - REFERENCE OTA
 DESIGN A - REFERENCE OTA

Input Ch1 160mVpp @ 1 Hz

Output Ch2 18mVpp THD ~ -28dBm ~ 3.9% @160mVpp, 1Hz
 DESIGN B - CURRENT DIVISION OTA and
Source Degeneration

VDD

M9 M4 M3 M11

M10
M12

ISS M14 M15

VSS

MM1 M1 M2 MM2
Vi- Vout

M16 Vi+

VDD
ISS

M8 M6 M17 M18 M5 M7

VSS
 DESIGN B - CURRENT DIVISION and SD OTA

Input Ch1 214mVpp @ 1 Hz

Output Ch2 16mVpp THD ~ -30dBm ~ 3.2% @214mVpp, 1Hz
DESIGN C - FLOATING GATE OTA, plus SD and CD

VDD

M8 M7
M9 M10
ISS
VSS Vb
MM1 M1 M2 MM2

Vout

Vi- Vi+

M5 M3 M4 M6

VSS
 DESIGN C - FLOATING GATE OTA

Input Ch1 214mVpp @ 1 Hz

THD ~ -34dBm ~ 2% @214mVpp, 1Hz
Output Ch2 15.2mVpp
DESIGN D - BULK DRIVEN OTA, PLUS CD AND SD

VDD

M8 M7
M9 M10
ISS
VSS
VG
MM1 M1 M2 MM2

Vout

Vi- Vi+

M5 M3 M4 M6

VSS
 DESIGN D - BULK DRIVEN OTA

Input Ch1 214mVpp @ 1 Hz

Output Ch2 15.2mVpp THD ~ -39dBm ~ 1.1% @214mVpp, 1Hz
SIMULATION VS EXPERIMENTAL RESULTS
1.2 micron CMOS Technology

SIMULATED RESULTS EXPERIMENTAL RESULTS

PAR \ DES A B C D A B C D
GM (nA/V) 11.6 11.55 11.51 11.24 10.5 9.3 8.7 8.8
∆ϕ @ 1Hz 0.1 0.098 0.047 0.025 <1 <1 <1 <1
(°)
Offset (mV) 0.07 0.027 -0.086 0.045 -1.8 -1.9 -1.5 0.647
THD (%) 1@162 1@240 1@330 1@900 3.9@160 5.6@242 3.2@330 5.9@900
mVpp mVpp mVpp mVpp mVpp mVpp mVpp mVpp
THD (%) @ - - - - 3.9 3.2 2 1.1
214mVpp
IBIAS(nA) 2 100 200 500 4 120 230 560
VDD= |VSS| 1.35 1.35 1.35 1.35 1.35 1.35 1.35 1.35
(V)
BIAS (V) N/A N/A -1.35 -1.35 N/A N/A -1.35 -1.35
 Rail-to-Rail Op Amps
• There are two basic configurations for Op Amp applications:
(a) inverting configuration, and,
(b) non-inverting configuration.

R2

Vin Vout Vout

R1 Vin
Vout
Vin

R1 R2

(a) Inverting Configuration (b) Non-Inverting (c) Voltage Follower

Configuration ( a special case of non-
inverting configuration )

Analog and Mixed-Signal Center,TAMU

 Why Rail-to-Rail Differential Input Stage?
• The input and output swings of inverting and non-inverting
configurations
Configuration Input common mode Output voltage swing
voltage swing
Inverting ≈0 Rail-to-rail
Non-inverting R1/(R1+R2) * Vsup Rail-to-rail
Voltage follower Rail-to-rail Rail-to-rail

• From the table, we see that for inverting configuration, rail-to-rail input
common mode range is not needed. But for non-inverting configuration,
some input common mode voltage swing is required, especially for a
voltage follower which usually works as an output buffer, we need a rail-
to-rail input common mode voltage range! To make an Op Amp work
under any circumstance, a differential input with rail-to-rail common
mode range is needed.

Analog and Mixed-Signal Center,TAMU

 How to Obtain a Rail-to-Rail Input
Common Mode Range?
• We know that usually the input stage of an op amp consists of a
differential pair. There are two types of differential pairs.

To the next
stage

Vi+ Vi-
Vi+ Vi-

Ib1
To the next
stage

(a) P-type differential input (b) N-type differential input

stage stage
 • First, let us observe how a differential pair works with different input
common mode voltage
– P-type input differential pair
Vdsat VGS VCMR ( Common Mode Range )

Vdd Itail
Vdsat,Ib
gm
Ib VGS,M1,2
Vi+
M1 M2 Vi-

VCMR Input common

mode voltage range
To the next Input Common
stage Mode Voltage
-Vss
-Vss Vdd Vicm
Where VGS=Vdsat+VT
 – N-type differential input stage

Vdsat VGS VCMR ( Common Mode Range )

Vdd Itail
To the next
stage gm

VCMR

Vi- Input common

Vi+
VGS mode voltage range
Ib Input Common
Vdsat Mode Voltage
-Vss
-Vss Vdd
 Again, how to Obtain a Rail-to-Rail Input
Common Mode Range?
• Why not connect these two pairs in parallel and try to get a full rail-to-
rail range?
Mb3
Vdsat VGS VCMR Mb4

Vdd
There should be an IP
Ib

subsequent stages
Summation and
overlap between
VCMR,N

Current
VCMR,P and VCMR,N , Vi+ Vi-
so the minimum
power supply M1 M3 M4 M2
VCMR,P

voltage requirement
is IN
( 4Vdsat+VTN+VTP ) Mb2
Mb1
-Vss
P Pair N Pair Simple N-P complementary input stage
Almost all of the rail-to-rail input stages are doing
VSUP ≥ 4Vdsat+VTN+VTP in this way by some variations! But how well
does it work?
 Observations on transconductance performance
for the entire region.-

• Transconductance vs. Vicm 1 W 1 W

• If K = KPN ( ) N = KPP ( ) P
2 L 2 L
gm and
Gm, the sum of
IN =IP=ITAIL
Region II gmN and gmP then gmN=gmP=gm= 2 KITAIL .
Region I
Region III Region I. When Vicm is close to the negative rail, only P-
channel pair operates.The N channel pair is off because
its VGS is less than VT. The total transconductance of the
differential pair is given by gmT= gmP=gm.

gmN gmP
Region II. When Vicm is in the middle range, both of the P
and N pairs operate. The total transconductance is given
-Vss by gmT = gmN+gmP=2gm.
Vdd
Common Mode Voltage
Region III. When Vicm is close to the positive rail, only N-
The total transconductance of the input channel pair operates. The total transconductance is
stage varies from gm to 2gm, the given by gmT = gmN=gm.
variation is 100% !
 How does the CMRR varies with the input common-mode signal ?

6 90

CMRR(dB)
CMRR
4 80
Vio(mV)

2 70

0 60
Vio

-1.0 -0.5 0 0.5 1.0 VI,CM(V)

 Rail-to-Rail Techniques: Summary and Comparison
Case Principle ∆ gm Slew Rate CMRR Advantage Limitations
1 I N + I P = const [1][2][6 N/A for weak Constant 56dB@10Hz, Small gm Only work well in weak inversion, can
] inversion 52dB@100KHz, variation ( 6% ) in not used in high speed application
40% if in strong measured in [2] weak inversion
inversion operation
2 IN + IP = const [3] -12% +6% ( 2 times 80 dB / 53 dB Depends on quadratic characteristics of
simulated in this variation ( measured in [3] ) MOSFETs, which is not exactly
[16] presentation ) followed for short channel transistors in
sub-micron processes
3 4 times I N or IP when +15% systematic gm 2 times variation 70dB / 43 dB Somewhat simple 1) Same with case 2, but we can
only one pair operates variation ( measured in [4] ) change 4 to other numbers to have
[3][4][6] smaller gm variation for short
channel transistors
2) Systematic gm deviation of 15%
even for ideal MOSFETs with
quadratic characteristics
4 Current switch, backup +20% systematic gm Constant N/A Constant slew rate Systematic gm deviation of 20% even
pairs [5] variation for ideal MOSFETs with quadratic
characteristics
5 6-pair structure, back +20% systematic gm Constant N/A Constant slew rate Same with Case 4
pairs [7] variation ( analytical
),
± 10% ( measured in
[7] )
6 Max/min selection [8][9] 7% ( simulated [9] ) Constant N/A Somewhat complex
5% ( strong
inversion, measured
[8] )
20% ( weak
inversion, measured
[8] )
7 Electronic zener [10] 8% ( measured ) 80 dB / 43 dB Same with Case 2
( measured in [10] )
8 Level shift [11] ± 4% after tuning ≥ 80 dB ( DC ) Simple Gm variation sensitive to VT variation
13% before tuning ( measured in [11] ) and power supply voltage change
( measured )
 Io+ VB Io- VB
Io+ Io-

Vi- C2 C2'
Vi+ Vi+ Vi-
M1 M2 ViFG- C '
ViFG+
C1 1
IB IB
(a) Floating Gate DP (b)

Io+ Io-
VB
Vi-
Vi+
M1 M2
IB
(c) Bulk Driven DP
Another Potential Solutions for Rail-to-Rail Amplifiers
One more Rail-to-Rail Op Amp Technique

By using dynamic level shift, the rail-to-rail

Amplifier can be obtained.

M1
V1 M2 V3
vSHIFT vSHIFT
vI+ vI-
vSHIFT vSHIFT
V2 M4 V4
M3
IL1 IL2 R10 R11

V1 Q1 V3 Q VB2
Q2

To next stage
10
RL1 RL2
vI+ vI- Q11

RL3 RL4
Q3 Q8 Q9
V2 Q4 V4

IL3 IL4 R8 R9

N-P complementary input stage Current summation

with dynamic level shift
1.0
V1~V4 and IL1 IL2
0.8 VSHIFT (V) V1 Q1 Q2 V3 Q10
RL1 R
V1 and V3 vI+
L2
vI-
0.6 VI,CM RL3 RL4
V2 Q3 Q4 V4 Q8
0.4 V2 and V4 IL3 IL4

0.2
VSHIFT VI,CM (V)
0.2 0.4 0.6 0.8 1.0
 ML1 ML4 M9 Vdd
ML2 ML3 M11
IL M1 M10 M12

To next stage
RL1 M2 RL2
Level-Shift Current

vI+ vI-
Generator

vI+ vI- RL3 RL4

M4 M6 M8
ML5 M3

ML6 ML7 M5 M7
ML8
-Vss
N-P complementary input stage Current summation
with dynamic level shift
 References
[1] J. H. Huijsing, and D. Linebarger, “Low voltage operational amplifier with rail-to-
rail input and output stages,” IEEE Journal of Solid-State Circuits, vol. SC-20, no.
6, pp. 1144-1150, December 1985
[2] W.-C. S. Wu, W. J. Helms, J. A. Kuhn, and B. E. Byrkett, “Digital-compatible
high-performance operational amplifier with rail-to-rail input and output ranges,”
IEEE Journal of Solid-State Circuits, vol. 29 , no. 1, pp. 63-66, January 1994
[3] R. Hogervorst, R. J. Wiegerink, P. A. L. de Jong, J. Fonderie, R. F. Wassenaar, and
J. H. Huijsing, “CMOS low-voltage operational amplifiers with constant-gm rail-
IEEE Proc. ISCAS 1992, pp. 2876-2879
[4] R. Hogervost, J. P. Tero, R. G. H. Eschauzier and J. H. Huijsing, “A compact
power-efficient 3-V CMOS rail-to-rail input/output operational amplifier for VLSI
cell libraries,” IEEE Journal of Solid-State Circuits, vol. 29, no. 12, pp. 1505-
1513, December 1994
[5] R. Hogervorst, S. M. Safai, and J. H. Huijsing, “A programmable 3-V CMOS rail-
to-rail opamp with gain boosting for driving heavy loads,” IEEE Proc. ISCAS
1995, pp. 1544-1547
[6] J. H. Huijsing, R. Hogervorst, and K.-J. de Langen, “Low-power low-voltage
VLSI operational amplifier cells,” IEEE Trans. Circuits and Systems-I, vol. 42. no.
11, pp. 841-852, November 1995
 References ( cont’d )
[7] W. Redman-White, “A high bandwidth constant gm, and slew-rate rail-to-rail
CMOS input circuit and its application to analog cell for low voltage VLSI
systems,” IEEE Journal of Solid-State Circuits, vol. 32, no. 5, pp. 701-712, May
1997
[8] C. Hwang, A. Motamed, and M. Ismail, “LV opamp with programmable rail-to-
rail constant-gm,” IEEE Proc. ISCAS 1997, pp. 1988-1959
[9] C. Hwang, A. Motamed, and M. Ismail, “Universal constant-gm input-stage
architecture for low-voltage op amps,” IEEE Trans. Circuits and Systems-I, vol.
42. no. 11, pp. 886-895, November 1995
[10] R. Hogervost, J. P. Tero, and J. H. Huijsing, “Compact CMOS constant-gm rail-to-
rail input stage with gm-control by an electronic zener diode,” IEEE Journal of
Solid-State Circuits, vol. 31, no. 7, pp. 1035-1040, July 1996
[11] M. Wang, T. L. Mayhugh, Jr., S. H. K. Embabi, and E. Sánchez-Sinencio,
“Constant-gm rail-to-rail CMOS op-amp input stage with overlapped transition
IEEE Journal of Solid-State Circuits, vol. 34, no. 2, pp. 148-156,
February 1999
[12] G. Ferri and W. Sansen, “A rail-to-rail constant-gm low-voltage CMOS
operational transconductance amplifier,” IEEE Journal of Solid-State Circuits, vol.
32, no. 10, pp. 1563-1567, October 1997
 References ( cont’d )
[13] S. Sakurai and M. Ismail, “Robust design of rail-to-rail CMOS operational amplifiers for a
IEEE Journal of Solid-State Circuits, vol. 31, no. 2, pp. 146-
156, February 1996
[14] J. H. Botma, R. F. Wassenaar, and R. J. Wiegerink, “Simple rail-to-rail low-voltage constant
transconductance CMOS input stage in weak inversion,” Electronics Letters, vol. 29, no. 12,
pp. 1145-1147, June 1993
[15] V. I. Prodanov and M. M. Green, “Simple rail-to-rail constant transconductance input stage
operating in strong inversion,” IEEE 39 th Midwest Symposium on Circuits and Systems, vol
2, pp. 957-960, August 1996
[16] J. H. Botma, R. F. Wassenaar, and R. J. Wiegerink, “A low voltage CMOS op amp with a
rail-to-rail constant-gm input stage and a class AB rail-to-rail output stage,” IEEE Proc.
ISCAS 1993, vol. 2, pp. 1314-1317, May 1993
[17] J. F. Duque-Carrillo, J. M. Valverde, and R. Perez-Aloe, “Constant-gm rail-to-rail common-
IEEE Journal of Solid-State
Circuits, vol. 28, no. 6, pp. 661-666, June 1993
[18] A. L. Coban and P. E. Allen, “A low-voltage CMOS op amp with rail-to-rail constant-gm
input stage and high-gain output stage,” IEEE Proc. ISCAS 1995, vol. 2, pp. 1548-1551,
April-May 1995
[19] J.F.Duque-Carrillo et al, “ 1-V Rail-to-Rail Operational Amplifiers in Standard CMOS
IEEE Journal of Solid-State Circuits, vol. 35, no. 1, pp. 33-44, January 2000
Voltage Multistage Transconductance Amplifier Topologies
For LV Power Supply.

• Good voltage gain can be obtained using cascode stages. But these stages
are not amenable for LV power supply.

• Under LV conditions, high voltage can be obtained using cascade amplifiers.

That is growing horizontally, rather than vertically.

• Direct Cascade of simple (inverting) stages gives the required voltage gain
without control of poles and zeroes.

• Dynamic behavior for optimal performance requires feedback (and

feedforward) circuits.

Analog & Mixed-Signal Center (AMSC)

 First Approach: Direct Cascade

I b1 Ib 2 I b1 M2
Vin V0 Vi V0 Vi Vx
Vx
M1 M2 M1 CP Ib 2
g m1 CL CP
C P g m2

Symbolic Representation (a) (b)

Two Possible Implementations

V (s ) + g m1g m 2 / C p C L
H (s ) = 0 ≅
Vin (s )  C L C p  C pC L 2
1 + s + + s
 g 02 g01  g01g 02

The poles are located at

g 01 g
ωp = , ω p = 02
1 Cp 2 CL
g g
H ( o) = m1 m2
g01g 02

Analog & Mixed-Signal Center (AMSC)

 How do you bring one pole close to the origin?
-Use feedback
C m1

Vin V0 Neglect Cp (i.e., C p<<Cm1)

g m1 CL
C p g m2

V0 (s ) g m1(g m2 − sC m1) / C LC m1
H (s ) = =
Vin (s ) s 2 + s (g 01(C L + C m1 ) / C LC p + g m 2 / C L + g02 / C L )+ g 01g 02 / C LC m1

The poles are approximately located at :

 g  g  g  1
ωp
2
≅ (g m2 + g 02 ) / C L and ω p1 ≅  01  02 =  01 
 Cm1  gm2  C m1  A V02
The good news is that :
ω p << ω p Good for stability
1 2
H(o) = g m1g m2 / g01g 02 Large DC voltage gain

The bad news is a zero at the RHP

g m2
ωz =
1 Cm1

Analog & Mixed-Signal Center (AMSC)

Now we will use a feedforward circuit to cancel the zero at the RHP.

This will impact the complexity and performance of the design.

Recall that before applying the feedforward we had:

V0 (s ) g m1(g m2 − sC m1) / C LC m1
H (s ) = =
Vin (s ) s 2 + s (g 01(C L + C m1 ) / C LC p + g m 2 / C L + g02 / C L )+ g 01g 02 / C LC m1

C m1
Now the corresponding H(s) becomes:
Vin V0

g m2 CL − g m1g m2
g m1 H (s ) =
s 2C m1C L + sC m1g m 2 + g01g 02
g mf g mf = g m1
No zero

This can be extended to higher-order systems, let us consider first a

third-order system.

Analog & Mixed-Signal Center (AMSC)

 Nested Gm-C Compensation Amplifier.

C m1
C m2
V0
Vi
g m1 g m2 g m3 CL

g mf 2

g mf 1
Three-stage amplifier topology with NGCC

V0 (s ) g m1g m2g m3+ sg m1(g mf 2 − g m 2 )C m2 + (g mf 1 − g m1 )C m1C m2

H (s ) = =
Vi (s ) g 01g 02g 03 + sg m2g m3C m1 + s 2 (g m3 + g mf 2 − g m2 )C m1C m2 + s3C LC m1C m 2

By making g mf1 = g m1 and g mf2 = g m2 ,

V (s ) − g m1g m2g m3
H (s ) = 0 =
Vi (s ) g 01g 02g 03 + sg m2g m3C m1 + s 2g m3C m1C m 2 + s 3C LC m1C m2

Analog & Mixed-Signal Center (AMSC)

This H(s) can be written as
- A0
H(s) =
 A 0   s s 2 
 1+ s  1+ +
 f1   f 2 f 2f 3 


g g g g
A 0 = m1 m3 m 2 and f1 = GB = m1
g 01g03 g 02 C m1
g g g g
f 2 = m2 , f 2f3 = m2 m3 ; f i = mi
Cm2 C m2 C L C mi

Note that the dominant pole is located at

g m1
f C m1 g01g 02g 03  g  1
P1 = 1 = = =  01 
A 0 g m1g m2g m3 g m2g m3C m1  C m1  A V0 2 A V03
g 01g 02g03

Analog & Mixed-Signal Center (AMSC)

 Multipath Nested Miller Compensation Technology
Potential Feedforward Schemes: An Amplifier Topologies Re-Visit.

C m1
C m2
Vi 1 2 3 Cm3 V0
(a) Multipath nested miller compensation topology.
FF
g m1 g m2 g m3 − g m4

g mf

C m1
C m2
Vi 1 2 3 Cm3 V0
(b) An abstract model for the amplifier proposed by
g m1 g m2 g m3 − g m4 Castello, et.al.

g mf

C m1
Vi V0 (c ) The amplifier with multipath miller zero
cancellation.
g m1 g m2

g mf Analog & Mixed-Signal Center (AMSC)

 Let Us Now Compare Several Four-Order Topologies

− A0
H (s ) =
(1 + a1s + a 2s 2 + a3s3 )
C m1  s 
 1+ 
C m2  P 
 1
Vi C m3 V0 GB
P1 =
CL A0
g m1 gm2 g m3 g m4
1 1 1
a1 = , a2 = , a3 =
f2 f 2 f3 f 2f 3f 4
g mf 3
1 C C 1 C mi
= m2 m3 , =
f 2 f 3 g m2 g m3 f i g mi
g mf 2

g mf1
Four stage amplifier topology with NGCC (Fan You et al)
f1 < f 2 < f 3 ≤ f 4 , f1 = GB
f2
f4 >
1 − f2 / f3

• Power Comsumption
 n− 1 α f  C mi g
P = (VDD − Vss )I n 1 + ∑ i i  , αi = , α i f i = mi
 i=1 f n  CL CL
I n and f n are current and frequency normalization factors, respectively.
 Comparison of Several Topologies.

g g
V0 (s ) 1 − b1s − b 2s 2 − b3s 3 ki = mi , i = 1,3 and f i = mi
= − A0 , g oi C mi
Vi (s ) 2 3
(1 + s / P1)(1 + a1s + a 2s + a 3s )

Where
f GB
A 0 = k1k 2k 3k 4 , P1 = 1 =
A 0 A0

Comparison of Polynomial Coefficients for Four Stage NMC and NGCC Amplifier.

Design
Ph(s) a1 a2 a3
(g m 4 C m 2 − g m 2 C m 3 ) (g m 4 − g m 2 − g m 3 )C m 2 C m 3 Cm 2Cm3CL
NMC g m 2g m 3g m 4 g m 2 g m 3g m 4 Complex
g m 2g m 4
Cm2 Cm 2Cm3 Cm 2Cm3CL
NGCC gm2 gm 2gm3 g m 2 g m 3g m 4 Simple

Z(s) b1 b2 b3
Cm3 Cm 2Cm3 C m1C m 2 C m 3
NMC gm 4 gm3gm 4 g m 2 g m 3g m 4

NGCC 0 0 0

Analog & Mixed-Signal Center (AMSC)

 Nested Gm-C Compensation (NGCC) Nth-Order
C m1

C m2
Vi C mn V0

g m1 g m2 g mn g mn + 1

g mfn Level n

g mf 2 Level 2

g mf 1 Level 1
Conceptual multistage amplifier topology with NGCC.

C m1
Vi V0
g m1 A (s )

g mf 1
Abstract model.

Analog & Mixed-Signal Center (AMSC)

 How to Implement a Positive Gm?

Vdd
C m1
Vi V0 g m2
M12 M13
G m1 G m2 M 22

G mf 1 Vout
Vb1
M14
g mf 1
(a) Representation
Vb 2
Vi Mf 1
M11
M 21
G m1 ⇒ M11 − M14 , g mM11 = g m1 g m1 Vss
G m 2 ⇒ M 21 − M 22 , g mM22 = g m2 (b) Transistor Level
G mf 1 ⇒ Mf 1

• If G m2 > G mf1 , M22 current > Mf1 current , then add

M21 to provide additional current.
• If G m2 > G mf1 , Remove M21 and add a PMOS transisto r
in parallel to M22.

Analog & Mixed-Signal Center (AMSC)

 Design Example of a Four-Stage Amplifier

Vdd

g m4

V+ C m2 Cm3 Vout
V−
C m1

Vb 2 gmf 2
Vb1 gmf 3
Vb 3
M3 M 4 M5

gmf1
g m1 g m2 g m3
Vss

Four stage operational amplifier with NGCC topology

Analog & Mixed-Signal Center (AMSC)

 Measured Performance of the 4-Stage NGCC Op Amp.

Power Consumptio n 0.68mW 1.40mW

DC Gain ≈ 100dB ≈ 100dB
Gain Bandwidth 610kHz 1.0MHz
Phase Margin 60o 58o
Input Offset 5.2mV 5.2mV
Slew Rate 2.5V/m S 5.0V
Power Supply ± 1.0V ± 1.0V
Load Condition 10kΩ // 20 pF 10kΩ //20pF
Area 0.22mm 2 0.22mm 2

Analog & Mixed-Signal Center (AMSC)

What is the effect of f4 /GB?

How far should one push f4?

Ts*GB Phase Margin

8 80
___ phase
7
----- Ts
6 60

4 40

2 20

0 0
1 2 3 4 5 6 7 8
f4/GB

The phase margin and normalized settling time (TsGB) of an

NGCC amplifier vs. f4/GB.

• Trade-off between phase margin versus setting time.

Analog & Mixed-Signal Center (AMSC)

How do the Two Topologies Compare for Power Consumption?

7.5 * NMC
7 +
NGCC
*
Normalized Power
6.5

6 *
+
5.5
*
5
+
*
4.5 +
+ *
4 + *+
*+ *+
3.5 * *
3
0.5 1 1.5 2 2.5 3
Ts*GB

The normalized power consumption of the NGCC and the NMC amplifiers as
a function of the normalized settling time.

Analog & Mixed-Signal Center (AMSC)

More Experimental Results.

Analog & Mixed-Signal Center (AMSC)

 References
S. Pernici, “A CMOS Low-Distortion Fully Differential Power Amplifier with Double Nested
Miller Compensation,” IEEE J. Solid-State Circuits, Vol. 28, No. 7, pp. 758-763, July 1993.

F. You, S.H.K. Embabi and E. Sánchez-Sinencio, “Multistage Amplifier Topologies with

Nested Gm-C Compensation,” IEEE J. of Solid-State Circuits, Vol. 32, No. 12, pp. 2000-2011,
December 1997.

K.N. Leung, P.K. T. Mok, W.-H. Ki, and J. K. O. Sin, “ Three-Stage Large Capacitive Load
Amplifier with Damping Factor-Control Frequency Compensation, “IEEE J. of Solid-State
Circuits, Vol. 35, No. 2, pp. 221-230, February 2000

S. Yan and E. Sánchez-Sinencio, Low Voltage Analog Circuit Design Techniques: A

Tutorial, IEICE Trans. Fundamentals, Vol. E83-A, No. 2 February 2000
E. Sánchez-Sinencio and Andreas G. Andreou, Eds. “ Low-Voltage/Low-Power Integrated
Circuits and Systems “, IEEE Press, Piscataway, NJ 1999
A. Rodriguez-Vazquez and E. Sánchez-Sinencio, Eds., Special Issue on Low-Voltage and
Low-Power Analog and Mixed-Signal Circuits and Systems, IEEE Trans. on Circuits and
Systems I, vol. 42, No. 11, November 1995

Analog & Mixed-Signal Center (AMSC)

 Conclusions

• Low power supply and smaller

size technologies require
new analog circuit techniques
• Power Consumption and area
are critical specifications in
portable equipment, clever
design methodologies are
needed.

Joe Edgar
Analog and Mixed-Signal Center, TAMU