VHDL Lab Manual

VHDL Lab Manual Dated: 19/05/2011
FPGA DESIGN FLOW
Programmable Logic Design Flow
Design Specifications
Design Entry
Functional
Simulation RTL Model
(Zero Delay)
Target Device
Libraries (Vender
Synthesis
T Specific)
Gate level Gate level
E description using
S Simulation
target library cells Design Constraints
T
Area / Speed
B
E Gate level Model
N
C Timing Mapping +
H Simulation Translation Target Device
(Gate + Gate level model to Libraries (Vender
Interconnect device architecture Specific)
Delays)
Place and Route
Placing the design in Design Constraints
device while optimizing Area / Speed
it for speed and area
Programming file
generation
Libraries Bit Stream
(Simprims
and
Unisims) Download onto
FPGA/ CPLD
Prepared By:
Parag Parandkar Asst. Prof. ECE Dept., CDSE, Indore (M.P.)
parag.vlsi@gmail.com
FPGA Design Flow for Xilinx

The Design flow followed by Xilinx devices is as shown as under:
Xilinx FPGAs are reprogrammable and when combined with an HDL design
flow can greatly reduce the design and verification cycle.
Prepared By:
Broadly the stages can be categorized as:

1. Design Entry may have two alternatives:
a) Performing HDL coding for synthesis as the target.( Xilinx HDL Editor).
b) Using Cores(Xilinx Core Generator).
2. Functional Simulation of synthesizable HDL code (MTI ModelSim).
3. Design Synthesis ( Xilinx project navigator).
4. Design Implementation (Xilinx Design Manager).
The stages are linked as follows:
VERILOG HDL/Verilog
Code Design Entry
Functional Simulation
Synthesis
Post Synthesis Simulation
Implementation
Timing Simulation
Program onto FPGA
Design Entry
The first stage of Xilinx design flow is a design entry process. A design must be
specified by using either a schematic editor or HDL text-based tool.
Functional Simulation
Upon the finish of the design entry stage, the functional simulation of the design
is being performed, which is used to verify functionality of the design assuming no
delays, whatsoever. This assumes no target technology selection at this stage and hence
assumes zero delay in simulation.
Prepared By:
Complex designs must be intensively simulated, at different simulation points,

during the design flow. Simulation verifies the operation of the design before it is
actually implemented as hardware. One of the most prevalent methods for simulation is
testbenching. Testbenches (VERILOG HDL) or text fixtures (Verilog) are used to specify
circuit stimuli and responses.
Roughly, simulation can be divided as functional and timing simulation. Primarily, the
functional simulation verifies that the design’s specifications are correctly understood and
coded. Timing information, produced during the device implementation stage, is not
available during the functional simulation. Functional simulation can be used after
synthesis, too.
Comparison between the pre- and post-synthesis simulations’ results checks the results of
the HDL compiler’s work and the HDL code’s correctness.
Timing simulation operates with the real delays (results of device implementation) and is
used for verification of implemented design. Timing data are given in an .sdf file
(Standard Delay Format).
Xilinx supports functional and timing simulations at different points of the design flow:
Ø Register Transfer Level (RTL) simulation.
Ø Post-synthesis functional simulation (Pre-NGDBuild).
Ø Post-implementation back-annotated timing simulation.
Design Synthesis
After this process, the synthesis is performed. Here for the first time in the design
flow the target technology (choice of a particular FPGA device family) is being
performed. This target technology selection will remain the same, henceforth in the
design flow, upto the final implementation stage, where finally generated Bit stream file
gets downloaded onto that FPGA.
The output of the synthesis process is creation of gate level netlist. This refers to
the EDIF implementation netlist of the FPGA design. Besides the EDIF implementation
netlist, the XNF (Xilinx netlist format) netlist can be used as well.
Although the XNF is now becoming rather obsolete. The EDIF netlist is used as
an input file to the Xilinx Implementation tool and specifies how the core will be
implemented.
The Electronic Design Interchange Format (EDIF) is a format used to exchange design
data between different CAD systems. In the world of FPGA design, it is used for
interchange of data between different EDA (Electronic Design Automation) software
tools. EDIF files are used for FPGA implementation only. They are the result of design
synthesis and can be generated from different design entry EDA tools: schematic or HDL
design tools. EDIF files are inputs to the Xilinx implementation tools during the
translation step (NGDBuild).
Design Implementation
Design Implementation includes the following steps:
i) Translate
ii) Map
iii) Place and Route
Prepared By:
In the Translate step, which is the first step in the implementation process, EDIF
netlist must be further converted into Native Generic Database file (NGD), by means of a
program called NGDBuild. The NGD file resulting from an NGDBuild run contains the
logical description of the design that can be mapped into a targeted Xilinx FPGA device
family. It is important to stress that NGDBuild merges all available EDIF netlists from
the working directory. This is actually the step where the black-box netlist becomes
merged with the rest of FPGA design.
In the next stage, the Map stage, the NGD file is an input into a MAP program
that maps logical design to a Xilinx FPGA. The output of the MAP program is an NCD
(Native Circuit Description) file. The NCD is a physical representation of the design
mapped to the components of internal FPGA architecture.
The mapped design is ready to be placed and routed. The PAR program does this
job. The input to PAR is a mapped (not routed) NCD file, while the output is a fully
routed NCD file.
Review reports are generated by the Implement Design process, such as the Map
Report or Place & Route Report, and change any of the following to improve your
design:
Ø Process properties
Ø Constraints
Ø Source files
Synthesis and again implementation of the design is being made until design
requirements are met.
Timing verification of the design can be made at different points in the design
flow as follows:
i) Run static timing analysis at the following points in the design flow:
Ø After Map.
Ø After Place and Route.
ii) Running Timing Simulations at the following points in the design flow:
Ø After Map (for a partial timing analysis of CLB and IOB delays).
Ø After Place and Route (for full timing analysis of block and net
delays).
Program onto FPGA

Programming on the Xilinx device can be made as follows:
Ø Creation of a programming file (BIT) to program FPGA.
Ø Generate a PROM, ACE, JTAG file for debugging or to download to
the device.
Ø Use iMPACT to program the device through programming cable.
Xilinx FPGA, as an SRAM-based programmable PLD, must be configured with
the configuration bitstream. The configuration bitstream is generated from the fully
routed NCD file, by means of a BitGen program. The output of BitGen is a binary file
with the .BIT extension that can be formatted for different PROM devices.
Prepared By:
EXPERIEMENT NO. 1
Simulation using all the modeling styles and Synthesis of all the
logic gates using VHDL
AIM:
Perform Zero Delay Simulation of all the logic gates
written in behavioral, dataflow and structural modeling style in VHDL using a
Test bench. Then, Synthesize each one of them on two different EDA tools.
Electronics Design Automation Tools used:

i) FPGA Advantage 3.1 (includes Model Sim simulation tool and Leonardo
Spectrum Synthesis Tool)
ii) Xilinx Project Navigator 8.1 (Includes all the steps in the design flow from
Simulation to Implementation to download onto FPGA).
Block Diagram:
A And, Nand,
Or, Nor, C
Xor, Xnor
B
Truth table:
And Gate: Or Gate:
A B Y A B Y
0 0 0 0 0 0
0 1 0 0 1 1
1 0 0 1 0 1
1 1 1 1 1 1
Nand Gate: Nor Gate:

A B Y A B Y
0 0 1 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0
Prepared By:
1 1 0
Xor Gate: Xnor Gate:

A B Y A B Y
0 0 0 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 1
Boolean Equation:
And Gate: Y = (A.B) Or Gate: Y = (A + B)

Nand Gate: Y = (A.B)’ Nor Gate: Y = (A+B)’
Xor Gate: Y = A.B’ + A’.B Xnor Gate: Y = A.B + A’.B’
VHDL Code (In different modeling styles):

And Gate (In Dataflow, behavioral Modeling):
library ieee;
use ieee.std_logic_1164.all;
entity andg is
port (a,b : in std_logic;
c : out std_logic
);
end andg;
architecture andg_df of andg is -- simple dataflow modeling

begin
c <= a and b;
end andg_df;
architecture andg_beh of andg is -- behavioral modeling using simple process

begin
process(a,b)
begin
c <= a and b;
end process;
end andg_beh;
Or gate(Dataflow, behavioral modeling):
library ieee;
entity org is
Prepared By:
c : out std_logic
);
end org;
architecture org_df of org is -- dataflow modeling using when …. else

begin
c <= '0' when a = '0' and b = '0' else
'1' when a = '0' and b = '1' else
'1' when a = '1' and b = '0' else
'1' when a = '1' and b = '1' else
'Z';
end org_df;
architecture org_beh of org is -- behavioral modeling using if …. else

begin
process(a,b)
begin
if (a = '0' and b = '0') then
c <= '0';
elsif (a = '0' and b = '1') then
c <= '1';
c <= '1';
c <= '1';
end if;
end process;
end org_beh;
Nand Gate (In Dataflow, behavioral Modeling):

library ieee;
entity nandg is
c : out std_logic
);
end nandg;
architecture nandg_df of Nandg is -- dataflow modeling using with …… select

signal sel : std_logic_vector(1 downto 0);
begin
sel <= a & b;
with sel select
c <= '1' when "00",
'1' when "01",
'1' when "10",
'0' when "11",
'Z' when others;
end nandg_df;
Prepared By:
architecture nandg_beh of nandg is -- behavioral modeling using case … end case

begin
process(a,b)
variable v : std_logic_vector(1 downto 0);
begin
v := a & b;
case v is
when "00" => c <= '1';
when "01" => c <= '1';
when "10" => c <= '1';
when "11" => c <= '0';
when others => c <= 'Z';
end case;
end process;
end nandg_beh;
Nor Gate (In Dataflow, behavioral Modeling):

library ieee;
entity norg is
c : out std_logic
);
end norg;
architecture norg_df of norg is -- dataflow modeling using with …… select

begin
sel <= a & b;
with sel select
c <= '1' when "00",
'0' when "01",
'0' when "10",
'0' when "11",
'Z' when others;
end norg_df;
architecture norg_beh of norg is -- behavioral modeling using case … end case

begin
process(a,b)
begin
v := a & b;
case v is
when "00" => c <= '1';
when "01" => c <= '0';
when "10" => c <= '0';
when "11" => c <= '0';
Prepared By:
when others => c <= 'Z';

end case;
end process;
end norg_beh;
Xor gate(Dataflow, behavioral modeling):
library ieee;
entity xorg is
c : out std_logic
);
end xorg;
architecture xorg_df of xorg is -- simple dataflow modeling

begin
c <= (a and (not b)) or ((not a) and b);
end xorg_df;
architecture xorg_df1 of xorg is -- dataflow modeling using when …. else

begin
c <= '0' when a = '0' and b = '0' else
'1' when a = '0' and b = '1' else
'1' when a = '1' and b = '0' else
'1' when a = '1' and b = '1' else
'Z';
end xorg_df1;
architecture xorg_beh of xorg is -- behavioral modeling using if …. else

begin
process (a,b)
begin
if (a = '0' and b = '0') then
c <= '0';
c <= '1';
c <= '1';
c <= '0';
end if;
end process;
end xorg_beh;
Xnor Gate (In Dataflow, behavioral Modeling):

library ieee;
entity Xnorg is
Prepared By:

c : out std_logic
);
end Xnorg;
architecture Xnorg_df of Xnorg is -- dataflow modeling using with …… select

begin
sel <= a & b;
with sel select
c <= ‘1’ when “00”,
‘0’ when “01”,
‘0’ when “10”,
‘1’ when “11”,
‘Z’ when others;
end Xnorg_df;
architecture Xnorg_beh of Xnorg is -- behavioral modeling using case … end case

begin
process(a,b)
begin
v := a & b;
case v is
when “00” => c <= ‘1’;
when “01” => c <= ‘0’;
when “10” => c <= ‘0’;
when “11” => c <= ‘1’;
when others => c <= ‘Z’;
end case;
end process;
end Xnorg_beh;
Test Bench (Applicable to all the logic gates):

library ieee;
entity nandg_tst is -- test bench for a nand gate.

end nandg_tst;
architecture nandg_tst_a of nandg_tst is

component Nandg
c : out std_logic
);
end component;
signal a_i ,b_i, c_i : std_logic;
begin
Prepared By:
nandg_i : nandg port map ( a => a_i,

b => b_i,
c => c_i
);
process
begin
a_i <= '0';
b_i <= '0';
wait for 100 ns;
a_i <= '0';
b_i <= '1';
wait for 100 ns;
a_i <= '1';
b_i <= '0';
wait for 100 ns;
a_i <= '1';
b_i <= '1';
wait for 100 ns;
end process;
end nandg_tst_a;
Simulation Waveform:
Nand Gate:
Nor Gate:
And Gate:
Or Gate:
Xor Gate:
Xnor Gate:
Synthesis (Xor gate):
EDA Tool Name: Fpga Advantage 3.1 – Leonardo spectrum

Nand Gate:
EDA Tool Name: Xilinx Project Navigator – 8.1
Synthesis Report (Xilinx project Navigator):

Prepared By:
EXPERIEMENT NO. 2
Simulation using all the modeling styles and Synthesis of 1-bit half
adder and 1-bit Full adder using VHDL
AIM:
Perform Zero Delay Simulation of 1-bit half adder and 1-bit Full adder written in
behavioral, dataflow and structural modeling style in VHDL using a Test bench. Then,
Synthesize each one of them on two different EDA tools.

Block Diagram:
1-bit Half Adder:
A Half Adder Sum

(1-bit)
B Carry
1-bit Full Adder:
A Full Adder Sum

B (1-bit) Cout
Cin
Truth table:
Half Adder:
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Prepared By:
Full Adder:
A B Cin Sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Boolean Equation:
Half Adder:
Sum = A B
Carry = A.B
Full Adder:
Sum = A B Cin
Cout = A.B + A.Cin + B.Cin
VHDL Code:
Half Adder (Using dataflow, Behavioral Modeling):
library ieee;
entity ha_1b is
port ( a, b : in std_logic;
sum, carry : out std_logic
);
end ha_1b;
architecture ha_1b_df of ha_1b is -- dataflow modeling using with select

signal s : std_logic_vector(1 downto 0);
begin
s <= a & b;
with s select
sum <= '0' when "00",
'1' when "01",
'1' when "10",
'0' when "11",
'Z' when others;
with s select
carry <= '0' when "00",
Prepared By:
'0' when "01",

'0' when "10",
'1' when "11",
'0' when others;
end ha_1b_df;
architecture ha_1b_df1 of ha_1b is -- simple dataflow modeling using Boolean equation

begin
sum <= a xor b;
carry <= a and b;
end ha_1b_df1;
architecture ha_1b_beh of ha_1b is -- behavioral modeling using if …. else

begin
process (a,b)
begin
if (a = '0' and b = '0') then
sum <= '0';
carry <= '0';
sum <= '1';
carry <= '0';
sum <= '1';
carry <= '0';
sum <= '0';
carry <= '1';
end if;
end process;
end ha_1b_beh;
Full Adder (Using dataflow, Behavioral Modeling, Structural Modeling):
library ieee;
entity fa_1b is
port ( a, b, cin : in std_logic;
sum, cout : out std_logic
);
end fa_1b;
architecture fa_1b_df1 of fa_1b is -- simple dataflow modeling using Boolean equation

begin
sum <= a xor b xor cin;
cout <= (a and b) or (a and cin) or (b and cin);
end fa_1b_df1;
architecture fa_1b_beh of fa_1b is -- behavioral modeling using case … end case
Prepared By:
begin
process (a,b)
begin
v := a & b & cin;
case v is
when "000" =>
sum <= '0';
cout <= '0';
when "001" =>
sum <= '1';
cout <= '0';
when "010" =>
sum <= '1';
cout <= '0';
when "011" =>
sum <= '0';
cout <= '1';
when "100" =>
sum <= '1';
cout <= '0';
when "101" =>
sum <= '0';
cout <= '1';
when "110" =>
sum <= '0';
cout <= '1';
when "111" =>
sum <= '1';
cout <= '1';
when others =>
sum <= 'Z';
cout <= 'Z';
end case;
end process;
end fa_1b_beh;
architecture fa_1b_str of fa_1b is

component ha_1b
sum, carry: out std_logic
);
end component;
component org
c : out std_logic
);
end component;
signal s1,s2,s3 : std_logic;
Prepared By:
begin
ha_1b_i1 : ha_1b port map ( a => a ,
b => b ,
sum => s1 ,
carry => s2
);
ha_1b_i2 : ha_1b port map ( a => s1 ,

b => cin ,
sum => sum ,
carry => s3
);
Org_i : org port map ( a => s3,

b => s2,
c => cout
);
end fa_1b_str;
architecture fa_1b_mixed of fa_1b is

component ha_1b
sum, carry: out std_logic
);
end component;
signal s1,s2,s3 : std_logic;
begin
ha_1b_i : ha_1b port map ( a => a , --structural modeling

b => b ,
sum => s1 ,
carry => s2
);
process (s1,cin) -- behavioral modeling

begin
sum <= s1 xor cin;
s3 <= s1 and cin;
end process;
cout <= s2 or s3; -- dataflow modeling

end fa_1b_mixed;
VHDL Test Bench:
Half Adder:
library ieee;
Prepared By:
entity ha_1b_tst is -- test bench for a 1-bit Half adder.

end ha_1b_tst;
architecture ha_1b_tst_a of ha_1b_tst is

component ha_1b
port (a, b : in std_logic;
sum, carry : out std_logic
);
end component;
signal a_i ,b_i, sum_i,carry_i : std_logic;

begin
nandg_i : ha_1b port map ( a => a_i,
b => b_i,
sum => sum_i,
carry => carry_i
);
process
begin
a_i <= '0';
b_i <= '0';
wait for 100 ns;
a_i <= '0';
b_i <= '1';
wait for 100 ns;
a_i <= '1';
b_i <= '0';
wait for 100 ns;
a_i <= '1';
b_i <= '1';
wait for 100 ns;
end process;
end ha_1b_tst_a;
Full Adder:
library ieee;
entity fa_1b_tst is -- test bench for a 1-bit Full adder

end fa_1b_tst;
architecture fa_1b_tst_a of fa_1b_tst is

component fa_1b
port ( a, b, cin : in std_logic;
sum, cout : out std_logic
);
Prepared By:
end component;
signal a_i ,b_i, cin_i, sum_i,carry_i : std_logic;
begin
fa_1b_i : fa_1b port map ( a => a_i,

b => b_i,
cin => cin_i,
sum => sum_i,
cout => carry_i
);
process
begin
a_i <= '0';
b_i <= '0';
cin_i <= '0';
wait for 100 ns;
a_i <= '0';
b_i <= '0';
cin_i <= '1';
wait for 100 ns;
a_i <= '0';
b_i <= '1';
cin_i <= '0';
wait for 100 ns;
a_i <= '0';
b_i <= '1';
cin_i <= '1';
wait for 100 ns;
a_i <= '1';
b_i <= '0';
cin_i <= '0';
wait for 100 ns;
a_i <= '1';
b_i <= '0';
cin_i <= '1';
wait for 100 ns;
a_i <= '1';
b_i <= '1';
cin_i <= '0';
wait for 100 ns;
a_i <= '1';
b_i <= '1';
cin_i <= '1';
wait for 100 ns;
end process;
end fa_1b_tst_a;
Prepared By:
Half Adder:
Full Adder:
Synthesis:
Half Adder:
Full Adder:
Synthesis Report (Xilinx Project Navigator):
Full Adder:
Prepared By:
EXPERIEMENT NO. 3
Simulation using all the modeling styles and Synthesis of 2:1

Multiplexer and 4:1 Multiplexer using VHDL
Aim:
Perform Zero Delay Simulation of 2:1 Multiplexer and 4:1 Multiplexer written in
behavioral, dataflow and structural modeling style in VHDL using a Test bench. Then,
Synthesize each one of them on two different EDA tools.

Block Diagram:
2:1 Multiplexer:
A
2:1
Y
B Multiplexer
4:1 Multiplexer:
A
4:1
B Multiplexer Y
C
D
S1 S0
Prepared By:
Truth table:
2:1 Multiplexer:
S A B Y
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
4:1 Multiplexer:
A B Y
0 0 A
0 1 B
1 0 C
1 1 D
Boolean Equation:
2:1 Multiplexer:
Y = A.S’ + B.S
4:1 Multiplexer:
Y = A.S1’.S0’ + B.S1’.S0 + C.S1.S0’ + D.S1.S0
VHDL Code:
2:1 Multiplexer ( in dataflow and behavioral modeling style) :
library ieee;
entity mux21 is
port ( a,b,s : in std_logic;
y : out std_logic
);
end mux21;
architecture mux21_df of mux21 is -- simple dataflow modeling using Boolean

equation
Prepared By:
begin
y <= (((not s) and a) or (s and b));
end mux21_df;
architecture mux21_beh of mux21 is -- behavioral modeling using case … end case

begin
process (a,b,s)
begin
case s is
when '0' =>
y <= a;
when '1' =>
y <= b;
when others =>
y <= 'Z';
end case;
end process;
end mux21_beh;
architecture mux21_df of mux21 is -- simple dataflow modeling using Boolean

begin -- equation
y <= a when s = '0' else
b;
end mux21_df;
configuration mux21_c of mux21 is

for mux21_beh
end for;
end mux21_c;
4:1 Multiplexer( in behavioral, dataflow and structural modeling styles):
library ieee;
entity mux41 is
port ( a,b,c,d,s1,s0 : in std_logic;
y : out std_logic
);
end mux41;
architecture mux41_beh of mux41 is -- simple behavioral modeling using Boolean

equation
begin
process (a,b,c,d,s1,s0)
begin
Prepared By:
y <= ((not s1) and (not s1) and a) or ((not s1) and s0 and b) or (s1 and (not s0)
and c) or (s1 and s0 and d);
end process;
end mux41_beh;
architecture mux41_beh1 of mux41 is -- behavioral modeling using if …elsif …end if;

begin
process (a,b,c,d,s1,s0)
begin
if (s1 = '0' and s0 = '0') then
y <= a;
elsif (s1 = '0' and s0 = '1') then
y <= b;
y <= c;
y <= d;
else
y<= 'Z';
end if;
end process;
end mux41_beh1;
architecture mux41_df of mux41 is -- dataflow modeling using with … select

signal s : std_logic_vector (1 downto 0);
begin
s <= s1 & s0;
with s select
y <= a when "00",
b when "01",
c when "10",
d when "11",
'Z' when others;
end mux41_df;
architecture mux41_df1 of mux41 is -- dataflow modeling using when ….. else

signal s : std_logic_vector (1 downto 0);
begin
s <= s1 & s0;
y <= a when s = "00" else
b when s = "01" else
c when s = "10" else
d when s = "11" else
'Z';
end mux41_df1;
Prepared By:
architecture mux41_str of mux41 is

component mux21
port ( a,b,s : in std_logic;
y : out std_logic
);
end component;
signal con1, con2 : std_logic;
begin
mux21_i1 : mux21 port map ( a => a ,

b => b ,
s => s1 ,
y => con1
);
mux21_i2 : mux21 port map ( a => c ,

b => d ,
s => s1 ,
y => con2
);
mux21_i3 : mux21 port map ( a => con1 ,

b => con2 ,
s => s0 ,
y => y
);
end mux41_str;
VHDL Test Bench:

2:1 Multiplexer:
library ieee;
entity mux21_tst is
end mux21_tst;
architecture mux21_tst_a of mux21_tst is

component mux21
port (a,b,s : in std_logic;
y : out std_logic
);
End component;
signal a,b,s,y : std_logic;
begin
Prepared By:
mux21_i : mux21 port map ( a => a,

b => b,
s => s,
y => y
);
process
begin
a <= '0';
b <= '1';
s <= '0';
wait for 100 ns;
s <= '1';
wait for 100 ns;
end process;
end mux21_tst_a;
4: 1 Multiplexer:
library ieee;
entity mux41_tst is
end mux41_tst;
architecture mux41_tst_a of mux41_tst is

component mux41
port ( a,b,c,d,s1,s0 : in std_logic;
y : out std_logic
);
end component;
signal a,b,c,d,s1,s0,y : std_logic;
begin
mux41_tst_i : mux41 port map ( a, b, c, d, s1, s0, y ); -- positional association
process
begin
a <= '0';
b <= '1';
c <= '1';
d <= '0';
s1 <= '0';
s0 <= '0';
wait for 100 ns;
s1 <= '0';
s0 <= '1';
wait for 100 ns;
Prepared By:
s1 <= '1';
s0 <= '0';
wait for 100 ns;
s1 <= '1';
s0 <= '1';
wait for 100 ns;
end process;
end mux41_tst_a;
Synthesis:
2 :1 Multiplexer:
4 :1 Multiplexer:
Prepared By:
EXPERIEMENT NO. 4
Simulation and Synthesis of 1:4 Demultiplexer using VHDL
Aim:
Perform Zero Delay Simulation 1:4 Demultiplexer in VHDL using a Test bench. Then,
Synthesize on two different EDA tools.

Block Diagram:
1:4
A Demultiplexer Y
S
Truth Table:
Input Select Output

A 00 Y(0)
B 01 Y(1)
C 10 Y(2)
D 11 Y(3)
Boolean Equation:
Y(3) = A.S.(1)’.S(0)’
Y(2) = B.S.(1)’.S(0)
Y(1) = C.S.(1).S(0)’
Y(0) = D.S.(1).S(0)
Prepared By:
VHDL Code:
library ieee;
entity demux14 is
port ( a : in std_logic;
s : in std_logic_vector(1 downto 0);
y : out std_logic_vector(3 downto 0)
);
end demux14;
architecture demux14_df of demux14 is -- dataflow modeling using when …. else

begin
y <= ( a & '0' & '0' & '0') when s = "00" else
('0' & a & '0' & '0') when s = "01" else
('0' & '0' & a & '0') when s = "10" else
('0' & '0' & '0' & a ) when s = "11" else
"0000";
end demux14_df;
architecture demux14_beh of demux14 is -- behavioral modeling using case ….. end case
begin
process(a,s)
begin
case s is
when "00" => y <= ( a & '0' & '0' & '0');
when "01" => y <= ('0' & a & '0' & '0');
when "10" => y <= ('0' & '0' & a & '0');
when "11" => y <= ('0' & '0' & '0' & a );
when others => y <= "0000";
end case;
end process;
end demux14_beh;
VHDL test bench:
library ieee;
entity demux14_tst is
end demux14_tst;
architecture demux14_tst_a of demux14_tst is

component demux14
port ( a : in std_logic;
s : in std_logic_vector(1 downto 0);
Prepared By:
);
end component;
signal a : std_logic;
signal s : std_logic_vector(1 downto 0);
signal y : std_logic_vector(3 downto 0);
begin
demux14_tst_i : demux14 port map (a,s,y); -- positional association
process
begin
a <= '1';
s <= "00";
wait for 100 ns;
s <= "01";
wait for 100 ns;
s <= "10";
wait for 100 ns;
s <= "11";
wait for 100 ns;
end process;
end demux14_tst_a;
Synthesis:
Prepared By:
EXPERIEMENT NO. 5
Simulation and Synthesis of 2:4 Decoder using VHDL
Aim:
Perform Zero Delay Simulation 2:4 Decoder in VHDL using a Test bench. Then,

Block Diagram:
2:4
A Decoder Y
Truth Table:
A Y
00 0001
01 0010
10 0100
11 1000
Boolean Equation:
Y(0) = A(1)’. A(0)’

Y(1) = A(1)’.A(0)
Y(2) = A(1).A(0)’
Y(3) = A(1). A(0)
Prepared By:
VHDL Code:
library ieee;
entity decod24 is
port ( a : in std_logic_vector(1 downto 0);
);
end decod24;
architecture decod24_beh of decod24 is -- behavioral modeling using case … end case

begin
process(a)
begin
case a is
when "00" => y <= "0001";
when "01" => y <= "0010";
when "10" => y <= "0100";
when "11" => y <= "1000";
when others => y <= "0000";
end case;
end process;
end decod24_beh;
VHDL Test Bench:
library ieee;
entity decod24_tst is
end decod24_tst;
architecture decod24_tst_a of decod24_tst is

component decod24
port ( a : in std_logic_vector(1 downto 0);
);
end component;
signal a1 : std_logic_vector(1 downto 0);
signal y1 : std_logic_vector(3 downto 0);
begin
decod24_tst_i : decod24 port map (a1,y1);
process
Prepared By:
begin
a1 <= "00";
wait for 100 ns;
a1 <= "01";
wait for 100 ns;
a1 <= "10";
wait for 100 ns;
a1 <= "11";
wait for 100 ns;
end process;
end decod24_tst_a;
Synthesis:
Prepared By:
EXPERIEMENT NO. 6
Simulation and Synthesis of 4:2 Encoder using VHDL
Aim:
Perform Zero Delay Simulation 4:2 Encoder in VHDL using a Test bench. Then,

Block Diagram:
A 4:2 Y
Encoder
Truth Table:
A Y
1000 00
0100 01
0010 10
0001 11
Boolean Equation:
Y(1) = A(1) + A(0)
Y(0) = A(2) + A(0)
VHDL Code:
library ieee;
entity encod42 is
port (a : in std_logic_vector(3 downto 0);
Prepared By:

);
end encod42;
architecture encod42_df of encod42 is

begin
with a select
y <= "00" when "0001",
"01" when "0010",
"10" when "0100",
"11" when "1000",
"00" when others;
end encod42_df;
VHDL Test Bench:

library ieee;
entity encod42_tst is
end encod42_tst;
architecture encod42_tst_a of encod42_tst is

component encod42
);
end component;
signal a1 : std_logic_vector(3 downto 0);
signal y1 : std_logic_vector(1 downto 0);
begin
encod42_i : encod42 port map (a1,y1);
process
begin
a1 <= "0001";
wait for 100 ns;
a1 <= "0010";
wait for 100 ns;
a1 <= "0100";
wait for 100 ns;
a1 <= "1000";
wait for 100 ns;
end process;
end encod42_tst_a;
Prepared By:
Synthesis:
Prepared By:
EXPERIEMENT NO. 7
Simulation and Synthesis of 4:2 Priority Encoder using VHDL
Aim:
Perform Zero Delay Simulation 4:2 Priority Encoder in VHDL using a Test bench.
Then, Synthesize on two different EDA tools.

Block Diagram:
4:2 Y
A Priority
Encoder
Truth Table:
A(3) A(2) A(1) A(0) Y(1) Y(0)

0 0 0 1 0 0
0 0 1 X 0 1
0 1 X X 1 0
1 X X X 1 1
A(3) A(2) A(1) A(0) Y(1) Y(0)

0 0 0 1 0 0
0 0 1 0 0 1
0 0 1 1 0 1
0 1 0 0 1 0
0 1 0 1 1 0
0 1 1 0 1 0
0 1 1 1 1 0
1 0 0 0 1 0
1 0 0 1 1 1
Prepared By:
1 0 1 0 1 1
1 0 1 1 1 1
1 1 0 0 1 1
1 1 0 1 1 1
1 1 1 0 1 1
1 1 1 1 1 1
Boolean Equation:
Y(1) = A(3) + A(2)
Y (0) = A(2)’.A(1) + A(3).A(2) + A(3).A(0)
VHDL Code:
library ieee;
entity pri_encod42 is
y : out std_logic_vector(1 downto 0);
valid : out std_logic
);
end pri_encod42;
architecture pri_encod42_beh of pri_encod42 is

begin
process(a)
begin
if (a(3) = '1') then
y <= "11";
valid <= '1';
elsif (a(2) = '1') then
y <= "10";
valid <= '1';
y <= "01";
valid <= '1';
y <= "00";
valid <= '1';
else
y <= "XX";
valid <= '0';
end if;
end process;
end pri_encod42_beh;
Prepared By:
VHDL Test Bench:

library ieee;
entity pri_encod42_tst is
end pri_encod42_tst;
architecture pri_encod42_tst_a of pri_encod42 is

component pri_encod42
);
end component;
signal a : std_logic_vector(3 downto 0);
signal y : std_logic_vector3 downto 0);
begin
pri_encod42_i : pri_encod42 port map (a,y);
process
begin
a <= “0000”
wait for 100 ns;
a <= “0001”;
wait for 100 ns;
a <= “0010”;
wait for 100 ns;
a <= “0011”;
wait for 100 ns;
a <= “0100”;
wait for 100 ns;
a <= “0101”;
wait for 100 ns;
a <= “0110”;
wait for 100 ns;
a <= “0111”;
wait for 100 ns;
a <= “1000”;
wait for 100 ns;
a <= “1000”;
wait for 100 ns;
a <= “1001”;
wait for 100 ns;
a <= “1010”;
wait for 100 ns;
a <= “1011”;
wait for 100 ns;
a <= “1100”;
Prepared By:
wait for 100 ns;

a <= “1101”;
wait for 100 ns;
a <= “1110”;
wait for 100 ns;
a <= “1111”;
wait for 100 ns;
end process;
end pri_encod42_tst_a;
Synthesis:
Prepared By:
EXPERIEMENT NO. 8
Simulation and Synthesis of magnitude comparator 1-bit using

VHDL
Aim:
Perform Zero Delay Simulation of magnitude comparator 1-bit in VHDL using a Test
bench. Then, Synthesize on two different EDA tools.

Block Diagram:
AgtB
A Magnitude
B Comparator AltB
1-bit AeqB
Truth Table:
A B AgtB AltB AeqB

0 0 0 0 1
0 1 0 1 0
1 0 1 0 0
1 1 0 0 1
Boolean Equation:
AgtB = A.B’
AltB = A’.B
AeqB = A’.B’ + A.B
VHDL Code:
library ieee;
Prepared By:
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity magcomp1 is
agtb, aeqb, altb : out boolean
);
end magcomp1;
architecture magcomp1_df of magcomp1 is

begin
agtb <= a > b;
altb <= a < b;
aeqb <= (a = b);
end magcomp1_df;
VHDL Test Bench:

library ieee;
entity magcomp1_tst is
end magcomp1_tst;
architecture magcomp1_tst_a of magcomp1_tst is

component magcomp1
agtb, aeqb, altb : out boolean
);
end component;
signal a,b : std_logic;
signal agtb, aeqb, altb : boolean;
begin
magcomp1_i : magcomp1 port map (a,b, agtb, aeqb, altb);
process
begin
a <= '0';
b <= '0';
wait for 100 ns;
a <= '0';
b <= '1';
wait for 100 ns;
a <= '1';
b <= '0';
wait for 100 ns;
a <= '1';
b <= '1';
Prepared By:
wait for 100 ns;

end process;
end magcomp1_tst_a;
Synthesis:
Prepared By:
EXPERIEMENT NO. 9
Simulation and Synthesis of D latch and D flip flop using VHDL
Aim:
Perform Zero Delay Simulation of d latch and d flip flop in VHDL using a Test bench.
Then, Synthesize on two different EDA tools.

VHDL Code:
D-latch:
library ieee;
entity dlatch is
port (d,en,reset : in std_logic;
q : out std_logic
);
end dlatch;
architecture dlatch_beh of dlatch is

signal s : std_logic;
begin
process(d,en,reset)
begin
if (reset = ‘1’) then
s <=’0’;
elsif (en = ‘1’) then
s <= d;
else
s <= s;
end if;
q <= s;
end process;
end dlatch_beh;
architecture dlatch_beh1 of dlatch is
Prepared By:
begin
process(d,en,reset)
variable s : std_logic;
begin
s :=’0’;
s := d;
else
s := s;
end if;
q <= s;
end process;
end dlatch_beh1;
architecture dlatch_beh2 of dlatch is

begin
process (d,en,reset)
begin
q <= ’0’;
q <= d;
end if;
end process;
end dlatch_beh2;
D-flip flop with asynchronous and synchronous reset:
library ieee;
entity dff is
port (d,clk,reset : in std_logic;
q : out std_logic
);
end dff;
architecture dff_asyncrst_a of dff is

begin
process(clk,reset)
begin
if (reset = '1') then
q <= '0';
elsif( clk'event and clk = '1') then
q <= d;
Prepared By:
end if;
end process;
end dff_asyncrst_a;
architecture dff_syncrst_a of dff is

begin
process(clk)
begin
if( clk'event and clk = '1') then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end dff_syncrst_a;
VHDL Test Bench:
Test Bench of D-latch:

library ieee;
entity dlatch_tst is
end dlatch_tst;
architecture dlatch_tst_a of dlatch_tst is

component dlatch
port (d,en,reset : in std_logic;
q : out std_logic
);
end component;
signal d,en,reset,q : std_logic;
begin
dlatch_i : dlatch port map (d,en,reset,q);
process
begin
reset <= '1';
en <= '0';
d <= '0';
wait for 200 ns;
reset <= '0';
en <= '1';
d <= '1';
Prepared By:
wait for 50 ns;

d <= '0';
wait for 30 ns;
d <= '1';
wait for 10 ns;
d <= '0';
wait for 10 ns;
en <= '0';
wait for 100 ns;
en <= '1';
d <= '1';
wait for 50 ns;
end process;
end dlatch_tst_a;
Test Bench of D flip flop asynchronous/synchronous reset:
library ieee;
entity dff_tst is
end dff_tst;
architecture dff_tst_a of dff_tst is

component dff
port (d,clk,reset : in std_logic;
q : out std_logic
);
end component;
signal d,reset,q : std_logic;
signal clk : std_logic := ‘1’;
begin
dff_i : dff port map ( d,clk,reset,q);
clk <= not clk after 50 ns;
process
begin
reset <= ‘1’;
d <= ‘0’;
wait for 200 ns;
reset <= ‘0’;
d <= ‘1’;
wait for 100 ns;
d <= ‘0’;
Prepared By:
wait for 100 ns;

d <= ‘1’;
wait for 100 ns;
d <= ‘0’;
end process;
end dff_tst_a;
Synthesis:
Prepared By:
EXPERIEMENT NO. 10
Simulation and Synthesis of JK, T Flip Flop using VHDL
Aim:
Perform Zero Delay Simulation of JK, T, Flip flop in VHDL using a Test bench. Then,

VHDL Code:
JK-flip flop:
library ieee;
entity JKff is
port (j,k,clk,reset : in std_logic;
q : out std_logic
);
end JKff;
architecture JKff_beh of JKff is

begin
process(clk,reset)
begin
s <= '0';
elsif (clk'event and clk = '1' ) then
if ( j = '0' and k = '0') then
s <= s;
elsif ( j = '0' and k = '1') then
s <= '0';
s <= '1';
s <= not s;
Prepared By:
end if;
end if;
end process;
end JKff_beh;
T-flip flop:
library ieee;
entity tff is
port (t,clk,reset : in std_logic;
q : out std_logic
);
end tff;
architecture tff_beh of tff is

begin
process(clk,reset)
begin
s <= '0';
elsif (clk'event and clk = '1' ) then
if ( t = '1') then
s <= not s;
else
s <= s;
end if;
q <= s;
end if;
end process;
end tff_beh;
VHDL Test Bench:
Test Bench of JK flip flop:
library ieee;
entity JKff_tst is
end JKff_tst;
architecture JKff_tst_a of JKff_tst is

component JKff
Prepared By:
port (j,k,clk,reset : in std_logic;

q : out std_logic
);
end component;
signal j,k,reset,q : std_logic;
signal clk : std_logic := '1';
begin
JKff_i : JKff port map (j,k,clk,reset,q);
process
begin
reset <= '1';
j <= '0';
k <= '0';
wait for 200 ns;
reset <= '0';
j <= '0';
k <= '1';
wait for 100 ns;
j <= '1';
k <= '0';
wait for 100 ns;
j <= '1';
k <= '1';
wait for 100 ns;
end process;
end jkff_tst_a;
Test Bench of T flip flop:
library ieee;
entity tff_tst is
end tff_tst;
architecture tff_tst_a of tff_tst is

component tff
port (t,clk,reset : in std_logic;
q : out std_logic
);
end component;
signal t,reset,q : std_logic;
signal clk : std_logic := '1';
Prepared By:
begin
tff_i : tff port map ( t,clk,reset,q);
process
begin
reset <= '1';
t <= '0';
wait for 200 ns;
reset <= '0';
t <= '1';
wait for 100 ns;
t <= '0';
wait for 100 ns;
t <= '1';
wait for 100 ns;
t <= '0';
end process;
end tff_tst_a;
Synthesis:
Prepared By:

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VHDL Lab Manual Dated: 19/05/2011

FPGA DESIGN FLOW

Programmable Logic Design Flow

FPGA Design Flow for Xilinx

Broadly the stages can be categorized as:

The stages are linked as follows:

Post Synthesis Simulation

Program onto FPGA

Complex designs must be intensively simulated, at different simulation points,

Program onto FPGA

Electronics Design Automation Tools used:

Nand Gate: Nor Gate:

Xor Gate: Xnor Gate:

And Gate: Y = (A.B) Or Gate: Y = (A + B)

VHDL Code (In different modeling styles):

architecture andg_df of andg is -- simple dataflow modeling

architecture andg_beh of andg is -- behavioral modeling using simple process

Or gate(Dataflow, behavioral modeling):

architecture org_df of org is -- dataflow modeling using when …. else

architecture org_beh of org is -- behavioral modeling using if …. else

Nand Gate (In Dataflow, behavioral Modeling):

architecture nandg_df of Nandg is -- dataflow modeling using with …… select

architecture nandg_beh of nandg is -- behavioral modeling using case … end case

Nor Gate (In Dataflow, behavioral Modeling):

architecture norg_df of norg is -- dataflow modeling using with …… select

architecture norg_beh of norg is -- behavioral modeling using case … end case

when others => c <= 'Z';

architecture xorg_df of xorg is -- simple dataflow modeling

architecture xorg_df1 of xorg is -- dataflow modeling using when …. else

architecture xorg_beh of xorg is -- behavioral modeling using if …. else

Xnor Gate (In Dataflow, behavioral Modeling):

port (a,b : in std_logic;

architecture Xnorg_df of Xnorg is -- dataflow modeling using with …… select

architecture Xnorg_beh of Xnorg is -- behavioral modeling using case … end case

Test Bench (Applicable to all the logic gates):

entity nandg_tst is -- test bench for a nand gate.

architecture nandg_tst_a of nandg_tst is

signal a_i ,b_i, c_i : std_logic;

nandg_i : nandg port map ( a => a_i,

Synthesis (Xor gate):

EDA Tool Name: Fpga Advantage 3.1 – Leonardo spectrum

EDA Tool Name: Xilinx Project Navigator – 8.1

Synthesis Report (Xilinx project Navigator):

Electronics Design Automation Tools used:

A Half Adder Sum

1-bit Full Adder:

A Full Adder Sum

architecture ha_1b_df of ha_1b is -- dataflow modeling using with select

'0' when "01",

architecture ha_1b_df1 of ha_1b is -- simple dataflow modeling using Boolean equation

architecture ha_1b_beh of ha_1b is -- behavioral modeling using if …. else

Full Adder (Using dataflow, Behavioral Modeling, Structural Modeling):

architecture fa_1b_df1 of fa_1b is -- simple dataflow modeling using Boolean equation

architecture fa_1b_beh of fa_1b is -- behavioral modeling using case … end case

architecture fa_1b_str of fa_1b is

signal s1,s2,s3 : std_logic;

ha_1b_i2 : ha_1b port map ( a => s1 ,

Org_i : org port map ( a => s3,

architecture fa_1b_mixed of fa_1b is

ha_1b_i : ha_1b port map ( a => a , --structural modeling

process (s1,cin) -- behavioral modeling

cout <= s2 or s3; -- dataflow modeling

VHDL Test Bench:

entity ha_1b_tst is -- test bench for a 1-bit Half adder.