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02001-001
VD GND VDD
APPLICATIONS Figure 1.
Battery-powered instruments
Hand-held scopemeters
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Ultrasound equipment
Rev. C
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AD9218
TABLE OF CONTENTS
Features .............................................................................................. 1 Using the AD9218 ENCODE Input......................................... 18
Applications....................................................................................... 1 Digital Outputs ........................................................................... 18
Functional Block Diagram .............................................................. 1 Analog Input ............................................................................... 18
General Description ......................................................................... 1 Voltage Reference ....................................................................... 19
Product Highlights ........................................................................... 1 Timing ......................................................................................... 19
Revision History ............................................................................... 2 User Select Options.................................................................... 19
Specifications..................................................................................... 3 Application Information ........................................................... 19
DC Specifications ......................................................................... 3 AD9218/AD9288 Customer PCB BOM...................................... 20
Digital Specifications ................................................................... 4 Evaluation Board ............................................................................ 21
AC Specifications.......................................................................... 5 Power Connector........................................................................ 21
Switching Specifications .............................................................. 6 Analog Inputs ............................................................................. 21
Timing Diagrams.......................................................................... 6 Voltage Reference ....................................................................... 21
Absolute Maximum Ratings............................................................ 8 Clocking....................................................................................... 21
Explanation of Test Levels ........................................................... 8 Data Outputs............................................................................... 21
ESD Caution.................................................................................. 8 Data Format/Gain ...................................................................... 21
Pin Configuration and Function Descriptions............................. 9 Timing ......................................................................................... 21
Terminology .................................................................................... 10 Troubleshooting.......................................................................... 21
Equivalent Circuits ......................................................................... 12 Outline Dimensions ....................................................................... 25
Typical Performance Characteristics ........................................... 13 Ordering Guide .......................................................................... 25
Theory of Operation ...................................................................... 18
REVISION HISTORY
12/06—Rev. B to Rev. C
Updated Format..................................................................Universal
Changes to DC Specifications......................................................... 3
1/04—Rev. A. to Rev. B
Updated format...................................................................Universal
Changes to General Description .................................................... 1
Changes to DC Specifications......................................................... 3
Changes to Switching Specifications.............................................. 6
Added AD9218/AD9288 Customer PCB BOM section ........... 20
Added Evaluation Board section .................................................. 21
7/03—Rev. 0 to Rev. A
Updated Ordering Guide................................................................. 6
Changes to Terminology section ................................................... .8
Changes to Figure 17b.................................................................... 19
Updated Outline Dimensions ....................................................... 24
Rev. C | Page 2 of 28
AD9218
SPECIFICATIONS
DC SPECIFICATIONS
VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.
Table 1.
Test AD9218BST-40/-65 AD9218BST-80/-105
Parameter Temp Level Min Typ Max Min Typ Max Unit
RESOLUTION 10 10 Bits
ACCURACY
No Missing Codes 1 Full VI Guaranteed, not tested Guaranteed, not tested
Offset Error 2 25°C I –18 2 18 –18 2 18 LSB
Gain Error2 25°C I –2 3 8 –2 3.5 8 % FS
Differential Nonlinearity 25°C I –1 ±0.3/±0.6 1/1.3 –1 ±0.5/±0.8 1.2/1.7 LSB
(DNL)
Full VI ±0.8 ±0.6/±0.9 LSB
Integral Nonlinearity 25°C I –1/–1.6 ±0.3/±1 1/1.6 –1.35/–2.7 ±0.75/±2 +1.35/2.7 LSB
(INL)
Full VI ±1 ±1/±2.3 LSB
TEMPERATURE DRIFT
Offset Error Full V 10 4 ppm/°C
Gain Error2 Full V 80 100 ppm/°C
Reference Full V 40 40 ppm/°C
REFERENCE
Internal Reference Voltage 25°C I 1.18 1.24 1.28 1.18 1.24 1.28 V
(REFOUT)
Input Resistance (REFINA, Full VI 9 11 13 9 11 13 kΩ
REFINB)
ANALOG INPUTS
Differential Input Voltage Full V 1 or 2 1 V
Range (AIN, AIN) 3
Common-Mode Voltage3 Full V VD/3 VD/3 V
Input Resistance Full VI 8 10 14 8 10 14 kΩ
Input Capacitance 25°C V 3 3 pF
POWER SUPPLY
VD Full IV 2.7 3 3.6 2.7 3 3.6 V
VDD Full IV 2.7 3 3.6 2.7 3 3.6 V
Supply Currents
IVD (VD = 3.0 V) 4 Full VI 108/117 113/130 172/183 175/188 mA
IVDD (VDD = 3.0 V)4 25°C V 7/11 13/17 mA
Power Dissipation DC 5 Full VI 325/350 340/390 515/550 525/565 mW
IVD Power-Down Current 6 Full VI 20 22 mA
Power Supply Rejection 25°C I ±1 ±1 mV/V
Ratio
1
No missing codes across industrial temperature range guaranteed for 40 MSPS, 65 MSPS, and 80 MSPS grades. No missing codes at room temperature guaranteed for
105 MSPS grade.
2
Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.25 V external reference) 65 grade in 2 V p-p range, 40, 80, 105 grades in 1 V p-p range.
3
(AIN –AIN) = ±0.5 V in 1 V range (full scale), (AIN – AIN) = ±1 V in 2 V range (full scale). The analog inputs self-bias to VD/3. This common-mode voltage can be overdriven
externally by a low impedance source by ±300 mV (differential drive, gain = 1) or ±150 mV (differential drive, gain = 2).
4
AC power dissipation measured with rated encode and a 10.3 MHz analog input @ 0.5 dBFS, CLOAD = 5 pF.
5
DC power dissipation measured with rated encode and a dc analog input (outputs static, IVDD = 0).
6
In power-down state, IVDD = ±10 μA typical (all grades).
Rev. C | Page 3 of 28
AD9218
DIGITAL SPECIFICATIONS
VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.
Table 2.
Test AD9218BST-40/-65 AD9218BST-80/-105
Parameter Temp Level Min Typ Max Min Typ Max Unit
DIGITAL INPUTS
Encode Input Common
Full V VD/2 VD/2 V
Mode
Encode 1 Voltage Full VI 2 2 V
Encode 0 Voltage Full VI 0.8 0.8 V
Encode Input Resistance Full VI 1.8 2.0 2.3 1.8 2.0 2.3 kΩ
Logic 1 Voltage—S1, S2, Full VI 2 2 V
DFS
Logic 0 Voltage—S1, S2, Full VI 0.8 0.8 V
DFS
Logic 1 Current—S1 Full VI –50 ±0 50 –50 ±0 50 μA
Logic 0 Current—S1 Full VI –400 –230 –50 –400 –230 –50 μA
Logic 1 Current—S2 Full VI 50 230 400 50 230 400 μA
Logic 0 Current—S2 Full VI –50 ±0 50 –50 ±0 50 μA
Logic 1 Current—DFS Full VI 30 100 200 30 100 200 μA
Logic 0 Current—DFS Full VI –400 –230 –50 –400 –230 –50 μA
Input Capacitance—S1, 25°C V 2 2 pF
S2, Encode Inputs
Input Capacitance DFS 25°C V 4.5 4.5 pF
DIGITAL OUTPUTS
Logic 1 Voltage Full VI 2.45 2.45 V
Logic 0 Voltage Full VI 0.05 0.05 V
Output Coding Twos complement or offset binary Twos complement or offset binary
Rev. C | Page 4 of 28
AD9218
AC SPECIFICATIONS
VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.
Table 3.
Test AD9218BST-40/-65 AD9218BST-80/-105
Parameter Temp Level Min Typ Max Min Typ Max Unit
DYNAMIC PERFORMANCE 1
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
fIN = 10.3 MHz 25°C I 58/55 59/57 57/53 58/55 dB
fIN = Nyquist 2 25°C I –/54 59/56 55/52 57/54 dB
Signal-to-Noise and Distortion (SINAD)
(With Harmonics)
fIN = 10.3 MHz 25°C I 58/54 59/56 56/52 58/53 dB
fIN = Nyquist2 25°C I –/53 59/55 55/51 57/53 dB
Effective Number of Bits
fIN = 10.3 MHz 25°C I 9.4/8.8 9.6/9.1 9.1/8.4 9.4/8.6 Bits
fIN = Nyquist2 25°C I –/8.6 9.6/8.9 9/8.3 9.3/8.6 Bits
Second Harmonic Distortion
fIN = 10.3 MHz 25°C I –72/–66 –89/–77 –69/–60 –77/–68 dBc
fIN = Nyquist2 25°C I –/–63 –89/–72 –65/–57 –76/–66 dBc
Third Harmonic Distortion
fIN = 10.3 MHz 25°C I –68/–62 –79/–68 –62/–57 –71/–63 dBc
fIN = Nyquist2 25°C I –/–60 –78/–64 –63/–57 –73/–69 dBc
Spurious Free Dynamic Range (SFDR)
fIN = 10.3 MHz 25°C I –68/–62 –79/–67 –62/–57 –69/–62 dBc
fIN = Nyquist2 25°C I –/–60 –78/–64 –63/–57 –70/–63 dBc
Two-Tone Intermodulation Distortion (IMD)
fIN1 = 10 MHz, fIN2 = 11 MHz at –7 dBFS 25°C V –74/–73 dBc
fIN1 = 30 MHz, fIN2 = 31 MHz at –7 dBFS 25°C V –73/–73 –77/–67 dBc
Analog Bandwidth, Full Power 25°C V 300 300 MHz
Crosstalk 25°C V –75 –75 dBc
1
AC specifications based on an analog input voltage of –0.5 dBFS at 10.3 MHz, unless otherwise noted. AC specifications for 40, 80, 105 grades are tested in 1 V p-p
range and driven differentially. AC specifications for 65 grade are tested in 2 V p-p range and driven differentially.
2
The 65, 80, and 105 grades are tested close to Nyquist for that grade: 31 MHz, 39 MHz, and 51 MHz for the 65, 80, and 105 grades, respectively.
Rev. C | Page 5 of 28
AD9218
SWITCHING SPECIFICATIONS
VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.
Table 4.
Test AD9218BST-40/-65 AD9218BST-80/-105
Parameter Temp Level Min Typ Max Min Typ Max Unit
ENCODE INPUT PARAMETERS
Maximum Encode Rate Full VI 40/65 80/105 MSPS
Minimum Encode Rate Full IV 20/20 20/20 MSPS
Encode Pulse Width High (tEH) Full IV 7/6 5/3.8 ns
Encode Pulse Width Low (tEL) Full IV 7/6 5/3.8 ns
Aperture Delay (tA) 25°C V 2 2 ns
Aperture Uncertainty (Jitter) 25°C V 3 3 ps rms
DIGITAL OUTPUT PARAMETERS
Output Valid Time (tV) 1 Full VI 2.5 2.5 ns
Output Propagation Delay (tPD)1 Full VI 4.5 7 4.5 6 ns
Output Rise Time (tR) 25°C V 1 1.0 ns
Output Fall Time (tF) 25°C V 1.2 1.2 ns
Out-of-Range Recovery Time 25°C V 5 5 ns
Transient Response Time 25°C V 5 5 ns
Recovery Time from Power-Down 25°C V 10 10 Cycles
Pipeline Delay Full IV 5 5 Cycles
1
tV and tPD are measured from the 1.5 level of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during test is not to exceed
an ac load of 5 pF or a dc current of ±40 μA. Rise and fall times are measured from 10% to 90%.
TIMING DIAGRAMS
SAMPLE SAMPLE SAMPLE
SAMPLE N N+1 N+5 N+6
AINA
AINB
ENCODE A
ENCODE B
tPD tV
Rev. C | Page 6 of 28
AD9218
SAMPLE SAMPLE SAMPLE
N+1 N+2 SAMPLE
N N+7 SAMPLE
N+8
AINA
AINB
ENCODE A
tPD tV
ENCODE B
02001-003
D9B TO D0B DATA N – 9 DATA N – 7 DATA N – 5 DATA N – 3 DATA N – 1 DATA N + 1
Figure 3. Normal Operation with Two Clock Sources (S1 = 1, S2 = 0) Channel Timing
ENCODE A
tPD tV
ENCODE B
D9B TO D0B DATA N – 11 DATA N – 9 DATA N – 7 DATA N – 5 DATA N – 3 DATA N – 1 DATA N + 1 02001-004
Figure 4. Data Align with Two Clock Sources (S1 = 1, S2 = 1) Channel Timing
Rev. C | Page 7 of 28
AD9218
ESD CAUTION
Rev. C | Page 8 of 28
AD9218
44 D9A (MSB)
47 ENCA
45 GND
43 D8A
42 D7A
41 D6A
40 D5A
39 D4A
38 D3A
37 D2A
46 VDD
48 VD
GND 1 36 D1A
AINA 2 35 D0A
AINA 3 34 GND
DFS/GAIN 4 33 VDD
REFINA 5 32 GND
AD9218
REFOUT 6 31 VD
TOP VIEW
REFINB 7 (Not to Scale) 30 VD
S1 8 29 GND
S2 9 28 VDD
AINB 10 27 GND
AINB 11 26 D0B
GND 12 25 D1B
VD 13
ENCB 14
VDD 15
GND 16
(MSB) D9B 17
D8B 18
D7B 19
D6B 20
D5B 21
D4B 22
D3B 23
D2B 24
02001-005
Figure 5. Pin Configuration
Rev. C | Page 9 of 28
AD9218
TERMINOLOGY
Analog Bandwidth Full-Scale Input Power
The analog input frequency at which the spectral power of the Expressed in dbm. Computed using the following equation:
fundamental frequency (as determined by the FFT analysis) is ⎛ V Full − Scale 2 rms ⎞
⎜ ⎟
reduced by 3 dB. ⎜ Z INPUT ⎟
PowerFull − Scale = 10 log⎜ ⎟
Aperture Delay ⎜ 0.001 ⎟
⎜ ⎟
The delay between the 50% point of the rising edge of the ⎝ ⎠
ENCODE command and the instant at which the analog input Gain Error
is sampled. Gain error is the difference between the measured and the ideal
Aperture Uncertainty (Jitter) full-scale input voltage range of the ADC.
The sample-to-sample variation in aperture delay. Harmonic Distortion, Second
Crosstalk The ratio of the rms signal amplitude to the rms value of the
Coupling onto one channel being driven by a low level signal second harmonic component, reported in dBc.
(–40 dBFS) when the adjacent interfering channel is driven by a Harmonic Distortion, Third
full-scale signal. The ratio of the rms signal amplitude to the rms value of the
Differential Analog Input Resistance, third harmonic component, reported in dBc.
Differential Analog Input Capacitance, Integral Nonlinearity
Differential Analog Input Impedance The deviation of the transfer function from a reference line
The real and complex impedances measured at each analog measured in fractions of 1 LSB using a “best straight line”
input port. The resistance is measured statically and the determined by a least-square curve fit.
capacitance and differential input impedances are measured
Minimum Conversion Rate
with a network analyzer.
The encode rate at which the SNR of the lowest analog signal
Differential Analog Input Voltage Range frequency drops by no more than 3 dB below the guaranteed limit.
The peak-to-peak differential voltage that must be applied to
Maximum Conversion Rate
the converter to generate a full-scale response. Peak differential
The encode rate at which parametric testing is performed.
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is 180 Output Propagation Delay
degrees out of phase. Peak-to-peak differential is computed by The delay between the 50% level crossing of ENCODE A or
rotating the input phase 180 degrees and again taking the peak ENCODE B and the 50% level crossing of the respective
measurement. The difference is then computed between both channel’s output data bit.
peak measurements. Noise (for Any Range Within the ADC)
Differential Nonlinearity
⎛ FS − SNRdBc − SignaldBFS ⎞
The deviation of any code width from an ideal 1 LSB step. VNOISE = Z × 0.001× 10⎜ dBm ⎟
⎝ 10 ⎠
Effective Number of Bits (ENOB)
The effective number of bits is calculated from the measured where Z is the input impedance, FS is the full scale of the device
SNR based on the equation for the frequency in question, SNR is the value for the particular
SNR MEASURED − 1.76 dB
input level, and Signal is the signal level within the ADC
ENOB = reported in dB below full scale. This value includes both
6.02
thermal and quantization noise.
ENCODE Pulse Width/Duty Cycle Power Supply Rejection Ratio
Pulse width high is the minimum amount of time that the The ratio of a change in input offset voltage to a change in
ENCODE pulse should be left in Logic 1 state to achieve rated power supply voltage.
performance; pulse width low is the minimum time ENCODE
pulse should be left in low state. See timing implications of
changing tENCH in text. At a given clock rate, these specifications
define an acceptable ENCODE duty cycle.
Rev. C | Page 10 of 28
AD9218
Signal-to-Noise and Distortion (SINAD) Two-Tone SFDR
The ratio of the rms signal amplitude (set 1 dB below full scale) The ratio of the rms value of either input tone to the rms value
to the rms value of the sum of all other spectral components, of the peak spurious component. The peak spurious component
including harmonics but excluding dc. may or may not be an IMD product. Reported in dBc (that is,
Signal-to-Noise Ratio (without Harmonics) degrades as signal level is lowered) or in dBFS (always related
The ratio of the rms signal amplitude (set at 1 dB below full back to converter full scale).
scale) to the rms value of the sum of all other spectral Worst Other Spur
components, excluding the first five harmonics and dc. The ratio of the rms signal amplitude to the rms value of the
Spurious-Free Dynamic Range (SFDR) worst spurious component (excluding the second and third
The ratio of the rms signal amplitude to the rms value of the harmonics) reported in dBc.
peak spurious spectral component. The peak spurious component Transient Response Time
may or may not be a harmonic. Reported in dBc (that is, Transient response is defined as the time it takes for the ADC to
degrades as signal level is lowered) or dBFS (always related back reacquire the analog input after a transient from 10% above
to converter full scale). negative full scale to 10% below positive full scale.
Two-Tone Intermodulation Distortion Rejection Out-of-Range Recovery Time
The ratio of the rms value of either input tone to the rms value Out-of-range recovery time is the time it takes for the ADC to
of the worst third-order intermodulation product; reported in dBc. reacquire the analog input after a transient from 10% above
positive full scale to 10% above negative full scale or from 10%
below negative full scale to 10% below positive full scale.
Rev. C | Page 11 of 28
AD9218
EQUIVALENT CIRCUITS
VD VD
30kΩ 30kΩ
15kΩ 10kΩ
15kΩ
02001-B-006
02001-010
Figure 6. Analog Input Stage Figure 10. Reference Inputs
VD VD
2.6kΩ
600kΩ
ENCODE S2
10kΩ
02001-011
2.6kΩ
02001-007
VD VD
10kΩ
OUT S1
02001-012
02001-008
VD
VDD
15kΩ
40kΩ
DX DFS/GAIN
15kΩ
02001-009
02001-013
VREF
Rev. C | Page 12 of 28
AD9218
(dB)
–50 –50
–60 –60
–70 –70
–80 –80
–90 –90
02001-017
02001-014
–100 –100
0 52.5 0 20
Figure 14. FFT: FS = 105 MSPS, AIN = 50.1 MHz @ –0.5 dBFS, Differential, Figure 17. FFT: FS = 40 MSPS, AIN = 19.75 MHz @ –0.5 dBFS, Differential,
1 V p-p Input Range 1 V p-p Input Range
0 0
ENCODE = 80MSPS ENCODE = 105MSPS
–10 –10
AIN = 39MHz AT –0.5dBFS AIN = 70MHz AT –0.5dBFS
–20 SNR = 56.1dB SNR = 51.9dB
–20
SINAD = 55.5dB SINAD = 51.8dB
–30 H2 = –71.8dB –30 H2 = –70.5dB
H3 = –66.2dB H3 = –76.3dB
–40 –40
(dB)
(dB)
–50 –50
–60 –60
–70 –70
–80 –80
–90 –90
02001-015
02001-018
–100 –100
0 40 0 40
Figure 15. FFT: FS = 80 MSPS, AIN = 39 MHz @ –0.5 dBFS, Differential, Figure 18. FFT: FS = 105 MSPS AIN = 70 MHz @ –0.5 dBFS, Differential,
1 V p-p Input Range 1 V p-p Input Range
0 0
ENCODE = 65MSPS ENCODE = 65MSPS
–10 –10
AIN = 30.3MHz AT –0.5dBFS AIN = 15MHz AT –0.5dBFS
SNR = 56.1dB –20 SNR = 56.4dB
–20
SINAD = 55.9dB SINAD = 55.9dB
–30 SFDR = 72dB –30 H2 = –73.9dB
H2 = –83.2dB H3 = –71.7dB
–40 H3 = –79dB –40
(dB)
(dB)
–50 –50
–60 –60
–70 –70
–80 –80
–90 –90
02001-019
02001-016
–100 –100
0 32.5 0 32.5
Figure 16. FFT: FS = 65 MSPS, AIN = 30.3 MHz @ –0.5 dBFS, Differential, Figure 19. FFT: FS = 65 MSPS, AIN = 15 MHz @ – 0.5 dBFS; with AD8138 Driving
2 V p-p Input Range ADC Inputs, 1 V p-p Input Range
Rev. C | Page 13 of 28
AD9218
0 0
ENCODE = 31MSPS ENCODE = 31MSPS
–10 –10
AIN = 8MHz AT –0.5dBFS AIN = 8MHz AT –0.5dBFS
–20 SNR = 59.23dB –20 SNR = 59dB
SINAD = 59.1dB SINAD = 58.8dB
–30 H2 = –87dB –30 H2 = –78.7dB
H3 = –81dB H3 = –72.9dB
–40 –40
(dB)
(dB)
–50 –50
–60 –60
–70 –70
–80 –80
–90 –90
02001-020
02001-023
–100 –100
0 15.5 0 15.5
Figure 20. FFT: FS = 31 MSPS, AIN = 8 MHz @ –0.5 dBFS, Differential, Figure 23. FFT: FS = 31 MSPS, AIN = 8 MHz @ –0.5 dBFS, Differential, with
1 V p-p Input Range AD8138 Driving ADC Inputs,1 V p-p Input Range
80
75 0
SECOND
THIRD ENCODE = 105MSPS
70 –10
AIN1 = 30.1MHz AT –7dBFS
–20 AIN2 = 31.1MHz AT –7dBFS
65
SFDR = –67dBFS
60 –30
SFDR
(dB)
55 –40
(dB)
50 –50
45 –60
40 –70
35 –80
30 –90
02001-024
02001-021
Figure 21. Harmonic Distortion (Second and Third) and Figure 24. Two-Tone Intermodulation Distortion
SFDR vs. AIN Frequency (1 V p-p, FS = 105 MSPS) (30.1 MHz and 31.1 MHz; 1 V p-p, FS = 105 MSPS)
80
THIRD
75 0
70 ENCODE = 80MSPS
SECOND –10
AIN1 = 29.3MHz AT –7dBFS
65 –20 AIN2 = 30.3MHz AT –7dBFS
SFDR = –77dBFS
60 –30
SFDR
(dB)
55 –40
(dB)
50 –50
45 –60
40 –70
35 –80
30 –90
02001-022
02001-025
Figure 22. Harmonic Distortion (Second and Third) and Figure 25. Two-Tone Intermodulation Distortion
SFDR vs. AIN Frequency (1 V p-p, FS = 80 MSPS) (29.3 MHz and 30.3 MHz; 1 V p-p, FS = 80 MSPS)
Rev. C | Page 14 of 28
AD9218
90
H2 1V
0
1V DIFFERENTIAL DRIVE
80
H3 1V –10 ENCODE = 65MSPS
AIN1 = 28.1MHz AT –7dBFS
70 –20 AIN2 = 29.1MHz AT –7dBFS
SFDR = –72.9dBFS
SFDR 1V –30
60
H2 2V –40
(dB)
50
(dB)
–50
40 H3 2V
–60
SFDR 2V
30
–70
20 –80
2V SINGLE-ENDED DRIVE
–90
10
02001-029
02001-026
0 20 40 60 80 100 120 140 160 180
–100
AIN FREQUENCY (MHz) 0 32.5
Figure 26. Harmonic Distortion (Second and Third) and Figure 29. Two-Tone Intermodulation Distortion
SFDR vs. AIN Frequency (FS = 65 MSPS) (28 MHz, 29 MHz; 1 V p-p, FS = 65 MSPS)
90
0
85 ENCODE = 40MSPS
–10
SECOND AIN1 = 10MHz AT –7dBFS
80 –20 AIN2 = 11MHz AT –7dBFS
THIRD SFDR = 74dBc
SFDR –30
75
–40
(dB)
70
(dB)
–50
65
–60
60 –70
55 –80
–90
50
02001-030
02001-027
10 20 30 40 50 60 70 –100
AIN FREQUENCY (MHz) 0 20
Figure 27. Harmonic Distortion (Second and Third) and Figure 30. Two-Tone Intermodulation Distortion
SFDR vs. AIN Frequency (1 V p-p, FS = 40 MSPS) (10 MHz, 11 MHz; 1 V p-p, FS = 40 MSPS)
75 80
SFDR
70 75
SFDR
70
65
65
(dB)
(dB)
60
60
SINAD SNR
55
55
50 SINAD
50
45 45
02001-028
02001-031
0 20 40 60 80 100 120 0 10 20 30 40 50 60 70 80
ENCODE RATE (MSPS) ENCODE RATE (MHz)
Figure 28. SINAD and SFDR vs. Encode Rate (AIN = 10.3 MHz, 105 MSPS Figure 31. SINAD and SFDR vs. Encode Rate (AIN = 10.3 MHz, 65 MSPS Grade)
Grade) AIN = –0.5 dBFS Differential, 1 V p-p Analog Input Range ) AIN = –0.5 dBFS Differential, 1 V p-p Analog Input Range
Rev. C | Page 15 of 28
AD9218
75 75
70 SFDR
SFDR 70
65
65
60
55 60
(dB)
(dB)
SINAD
50 55
45
SINAD 50
40
45
35
30 40
02001-035
02001-032
0 1 2 3 4 5 6 7 8 0 2 4 6 8 10 12 14
45
180
40 4.0
IVD – 105 GAIN –105
35
160
30 3.5
IVDD (mA)
–65/–105 IV DD
(mA)
(%)
140 25
IVD – 65 20 3.0
GAIN –65
120
15
10 2.5
100
5
80 0 2.0
02001-033
02001-036
0 20 40 60 80 100 120 140 –40 –20 0 20 40 60 80
Figure 33. IVD and IVDD vs. Encode Rate (AIN = 10.3 MHz, @ –0.5 dBFS), Figure 36. Gain Error vs. Temperature, AIN = 10.3 MHz, –65 MSPS Grade,
–65 MSPS/–105 MSPS Grade CI = 5 pF –105 MSPS Grade, 1 V p-p
1.131 68
66
1.129
SFDR –65
64 SFDR –105
1.127
62
1.125 SNR –65
(dB)
60
(V)
1.121
56
SNR –105
1.119 54
SINAD –105
52
02001-037
02001-034
Figure 34. VREF Output Voltage vs. Temperature (ILOAD = 300 μA) Figure 37. SNR, SINAD, SFDR vs. Temperature, AIN = 10.3 MHz,
–65 MSPS Grade, –105 MSPS Grade, 1 V p-p
Rev. C | Page 16 of 28
AD9218
1.50 90
SFDR – dBFS
1.45 80
1.40 70
1.35
60
1.30 SFDR – dBc
50
(dB)
(V)
1.25
40
1.20
70dB REF LINE
30
1.15
20
1.10
1.00 0
02001-040
02001-038
–1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 –60 –50 –40 –30 –20 –10 0
Figure 38. VREF vs. ILOAD Figure 40. SFDR vs. AIN Input Level, 10.3 MHz AIN @ 80 MSPS
2.0 1.0
0.8
1.5
0.6
1.0
0.4
0.5 0.2
(LSB)
(LSB)
0 0
–0.2
–0.5
–0.4
–1.0
–0.6
–1.5 –0.8
–2.0 –1.0
02001-041
02001-039
0 1024 0 1024
CODES CODES
Figure 39. Typical INL Plot, 10.3 MHz AIN @ 80 MSPS Figure 41. Typical DNL Plot, 10.3 MHz AIN @ 80 MSPS
Rev. C | Page 17 of 28
AD9218
THEORY OF OPERATION
The AD9218 ADC architecture is a bit-per-stage pipeline-type ANALOG INPUT
converter utilizing switch capacitor techniques. These stages The analog input to the AD9218 is a differential buffer. For best
determine the 7 MSBs and drive a 3-bit flash. Each stage
dynamic performance, impedance at AIN and AIN should match.
provides sufficient overlap and error correction, allowing
Special care was taken in the design of the analog input section
optimization of comparator accuracy. The input buffers are
of the AD9218 to prevent damage and data corruption when
differential, and both sets of inputs are internally biased. This
the input is overdriven. The nominal input range is 1.024 V p-p.
allows the most flexible use of ac-coupled or dc-coupled and
Optimum performance is obtained when the part is driven
differential or single-ended input modes. The output staging
differentially where common-mode noise is minimized and
block aligns the data, carries out the error correction, and feeds
even-order harmonics are reduced. Figure 42 shows an example
the data to output buffers. The set of output buffers are powered
of the AD9218 being driven differentially via a wideband RF
from a separate supply, allowing adjustment of the output
transformer for ac-coupled applications. As shown in Figure 43,
voltage swing. There is no discernible difference in performance
applications that require dc-coupled differential drives can be
between the two channels.
accommodated using the AD8138 differential output op amp.
USING THE AD9218 ENCODE INPUT AIN
Any high speed ADC is extremely sensitive to the quality of the 50Ω 25Ω
ANALOG 0.1µF
sampling clock provided by the user. A track-and-hold circuit is SIGNAL AD9218
essentially a mixer. Any noise, distortion, or timing jitter on the SOURCE
25Ω
1:1
clock is combined with the desired signal at the analog-to-
02001-042
AIN
digital output. For that reason, considerable care has been taken
in the design of the ENCODE input of the AD9218, and the Figure 42. Using a Wideband Transformer to Drive the AD9218
user is advised to give commensurate thought to the clock
source. The ENCODE input is fully TTL/CMOS compatible. 500Ω AD9218
DIGITAL OUTPUTS 50Ω
500Ω 25Ω
ANALOG AIN
The digital outputs are TTL/CMOS compatible for lower power SIGNAL
SOURCE AVDD AD8138 15pF
consumption. During power-down, the output buffers transition to VOCM
AIN
a high impedance state. A data format selection option supports 10kΩ
25Ω
0.1µF 500Ω
either twos complement (set high) or offset binary output (set
5kΩ 525Ω
low) formats.
02001-043
Figure 43. Using the AD8138 to Drive the AD9218
Rev. C | Page 18 of 28
AD9218
VOLTAGE REFERENCE APPLICATION INFORMATION
A stable and accurate 1.25 V voltage reference is built into the The wide analog bandwidth of the AD9218 makes it very
AD9218 (VREF OUT). Typically, the internal reference is used attractive for a variety of high performance receiver and
by strapping Pin 5 (REFINA) and Pin 7 (REFINB) to Pin 6 encoder applications. Figure 44 shows the dual ADC in a
(REFOUT). The input range for each channel can be adjusted typical low cost I and Q demodulator implementation for cable,
independently by varying the reference voltage inputs applied to satellite, or wireless LAN modem receivers. The excellent
the AD9218. No appreciable degradation in performance dynamic performance of the ADC at higher analog input
occurs when the reference is adjusted ±5%. The full-scale range frequencies and encode rates lets users employ direct IF
of the ADC tracks reference voltage, which changes linearly sampling techniques. IF sampling eliminates or simplifies analog
(a 5% change in VREF results in a 5% change in full scale). mixer and filter stages to reduce total system cost and power.
TIMING AD9218
after the rising edge of the encode command (see Figure 2 IF IN 90°
through Figure 4). The length of the output data lines and loads
placed on them should be minimized to reduce transients I
ADC
BPF
within the AD9218. These transients can detract from the
dynamic performance of the converter.
02001-044
The minimum guaranteed conversion rate is 20 MSPS. At clock VCO VCO
rates below 20 MSPS, dynamic performance degrades.
Figure 44. Typical I/Q Demodulation Scheme
USER SELECT OPTIONS
Two pins are available for a combination of operational modes,
enabling the user to power down both channels, excluding the
reference, or just the B channel. Both modes place the output
buffers in a high impedance state. Recovery from a power-down
state is accomplished in 10 clock cycles following power-on.
The other option allows the user to skew the B channel output
data by one-half a clock cycle. In other words, if two clocks are
fed to the AD9218 and are 180 degrees out of phase, enabling
the data align allows Channel B output data to be available at
the rising edge of Clock A. If the same encode clock is provided
to both channels and the data align pin is enabled, output data
from Channel B is 180 degrees out of phase with respect to
Channel A. If the same encode clock is provided to both
channels and the data align pin is disabled, both outputs are
delivered on the same rising edge of the clock.
Rev. C | Page 19 of 28
AD9218
Rev. C | Page 20 of 28
AD9218
EVALUATION BOARD
The AD9218/AD9288 customer evaluation board offers an easy DATA OUTPUTS
way to test the AD9218 or the AD9288. The compatible pinout The data outputs are latched on board by two 10-bit latches
of the two parts facilitates the use of one PCB for testing either and drive an 8-lead connector, which is compatible with the dual-
part. The PCB requires power supplies, a clock source, and a channel FIFO board that is available from Analog Devices, Inc.
filtered analog source for most ADC testing required. This board, together with ADC analyzer software, can greatly
POWER CONNECTOR simplify ADC testing.
Power is supplied to the board via a detachable 12-lead power DATA FORMAT/GAIN
strip. The minimum 3 V supplies required to run the board are The DFS/GAIN pin can be biased for desired operation at the
VD, VDL, and VDD. To allow the use of the optional amplifier DFS jumper located at the S1, S2 jumpers.
path, ±5 V supplies are required.
TIMING
ANALOG INPUTS Timing on each channel can be controlled, if needed, on the
Each channel has an independent analog path that uses a PCB. Clock signals at the latches or the data ready signals that
wideband transformer to drive the ADC differentially from a go to the output 80-lead connector can be inverted if required.
single-ended sine source at the input SMAs. The transformer Jumpers also allow for biasing of Pin S1 and Pin S2 for power-
paths can be bypassed to allow the use of a dc-coupled path down and timing alignment control.
using two AD8138 op amps with a simple board modification.
TROUBLESHOOTING
The analog input should be band-pass filtered to remove any
harmonics in the input signal and to minimize aliasing. If the board does not seem to be working correctly, try the
following:
VOLTAGE REFERENCE
• Verify power at the IC pins.
The AD9218 has an internal 1.25 V voltage reference; an
• Check that all jumpers are in the correct position for the
external reference for each channel can be employed instead
desired mode of operation.
by connecting two external voltage references at the power
• Verify that VREF is at 1.23 V.
connector and setting jumpers at E18 and E19. The evaluation
board is shipped configured for internal reference mode. • Try running encode clock and analog inputs at low speeds
(20 MSPS/1 MHz) and monitor the LCX821 outputs, DAC
CLOCKING outputs, and ADC outputs for toggling.
Each channel can be clocked by a common clock input at SMA The AD9218 evaluation board is provided as a design example
inputs ENCODE A and ENCODE B. The channels can also be for customers of Analog Devices. Analog Devices makes no
clocked independently by a simple board modification. The warranties, express, statutory, or implied, regarding
clock input should be a low jitter sine source for maximum merchantability or fitness for a particular purpose.
performance.
Rev. C | Page 21 of 28
ENCXB ENCB
R53
**DUT CLOCK SELEC TABLE** 0Ω **DUT CLOCK SELEC TABLE**
AD9218
**TO BE DIRECT OR BUFFERED** U6 GND **TO BE DIRECT OR BUFFERED**
U5
SN74VCX86 TIEB VDL R50
C25 0Ω SN74VCX86
ENCXA ENCA 0.1µF ENCODE B
R42 C42 R52
1 1A VCC 14 VDL J2 0.1µF ENCXB 8 3Y GND 7 GND R12
0Ω E13 E12 1kΩ 0Ω
TIEA VDL 2 1B 4B 13 9 3A 2Y 6 DRB
ENCODE A R51 R54 E35 E36 E34
C40 R43 R10 R46 VDL E16
J3 R39 3 1Y 4A 12 51Ω 1kΩ VDL 10 3B 2B 5
0.1µF 1kΩ 0Ω 0Ω 1kΩ
GND R49 R48 VDL
4 2A 4Y 11 DRA GND GND GND 11 4Y 2A 4 R13
E14 1kΩ 0Ω 1kΩ
R11 R41 E3 E4 E15 GND
50Ω 1kΩ VDL 5 2B 3B 10 GND 12 4A 1Y 3 CLKLATB
R44 R47 VDL E37 E38
GND GND GND ENCXA 6 2Y 3A 9 13 4B 1B 2
1kΩ 1kΩ
GND R55 VDL
GND 7 GND 3Y 8 CLKLATA VDL 14 VCC 1A 1
GND 1kΩ
R9 GND
VDD
0Ω C41
0.1µF
C8
0.1µF
GND
GND
C11 R33
VD
0.1µF 0Ω
AMPOUTA C7
C10 0.1µF
ENCA
GND
D9A (MSB)
D8A
D7A
D6A
D5A
D4A
D3A
D2A
GND 0.1µF
GND
R1 R4
R3 0Ω C9
50Ω C14 36Ω
J4 0.1µF 0.1µF
VD 48
VDD 46
D9A 44
D8A 43
D7A 42
D6A 41
D5A 40
D4A 39
D3A 38
D2A 37
GND 45
GND
ENC A 47
AIN A GND
GND E25 GND 1 GND D1A 36 D1A
GND AMPINA
C31 VD 2 GND
0.1µF AIN A D0A 35 D0A C4
1 6 R2 E2 E30 0.1µF
GND R5 3 AIN A GND 34 GND
2 5 36Ω 0Ω
E1 4 DFS/GAIN VDD 33 VDD C3
GND REFOUT E27 E20 0.1µF
3 4 VREFA E18 5 REFIN A GND 32 GND
T2 R6 GND
AMPOUTAB 25Ω GND E17 6 REFOUT AD9218 VD 31 VD
GND GND E19 7 REFIN B U1 VD 30
R SINGLE-ENDED VD E29 E24
E22 8 S1 GND 29 GND
VD E28 E23
E26 9 S2 VDD 28 VDD
Rev. C | Page 22 of 28
R SINGLE-ENDED 10 AIN B GND 27 GND
C1
VD
ENCB
VDD
GND
D9B
D7B
D6B
D5B
D4B
D3B
D2B
3 4
GND
T1 ENCA ENCB
GND R8
AMPINB GND 0Ω
C5 R20
D8 B
D7 B
D5 B
D4 B
D3 B
D2 B
D6B
C13 J5
GND
AIN B R14
R7 50Ω R40
50Ω AMPOUTB GND GND 0Ω
GND TIEB
C6
0.1µF GND GND GND
GND C15 R35
0.1µF 0Ω
VDD
C27 C24
0.1µF 0.1µF
–5V +5V VD VDD VDL VREFA VREFB
REF INA REFIN B
1 VDL 1 VREFB 1 GND
C37 C38 + C16 + C17 + C18 + C19 + C26 +
2 VDD 2 VREFA 2 –5V 10µF 10µF 10µF 10µF H3
+ 10µF 10µF 10µF
MTHOLE6
3 GND 3 GND 3 +5V GND H1
MTHOLE6
4 VD 4 GND 4 GND
P5 VD H2
MTHOLE6
P1 P4 P11 P6 VDD H4
GND MTHOLE6
P7 VDL
02001-045
GND
GND
U8 U10
C20
Rev. C | Page 23 of 28
CTS20 U3 CTS20 P2
0.1µF
VALUE = 50 74LCX821 VALUE = 50 HEADER40
AMPINB GND
D0B 1 1 20 20 D0N GND 1 OE VCC 24 VDL D0Y 1 1 20 20 D0Q 40 40 39 39 GND
C36 16 16 15 15 D0Q
R24 R30
50Ω 15pF 50Ω 14 14 13 13 GND
12 12 11 11 GND
10 10 9 9 GND
AMPOUTB AMPOUTBB 8 8 7 7 GND
6 6 5 5 GND
4 4 3 3 GND
2 2 1 1 GND
02001-046
NC = NO CONNECT GND
AD9218
AD9218
02001-047
02001-050
Figure 47. Top Silkscreen Figure 50. Split Power Plane
02001-048
02001-051
Figure 48. Top Routing Figure 51. Bottom Routing
02001-049
02001-052
Rev. C | Page 24 of 28
AD9218
OUTLINE DIMENSIONS
9.20
0.75 9.00 SQ
1.60
0.60 MAX 8.80
0.45 48 37
1 36
PIN 1
7.20
1.45 TOP VIEW 7.00 SQ
0.20 (PINS DOWN) 6.80
1.40
0.09
1.35
7°
3.5° 12 25
0.15 0° 13 24
0.05 SEATING 0.08
PLANE VIEW A 0.50
0.27
COPLANARITY
BSC 0.22
LEAD PITCH 0.17
VIEW A
ROTATED 90° CCW
051706-A
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9218BST-40 –40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218BST-RL40 –40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218BSTZ-40 1 –40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218BSTZ-RL401 –40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218BST-65 –40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218BST-RL65 –40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218BSTZ-651 –40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218BSTZ-RL651 –40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218BST-80 –40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218BST-RL80 –40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218BSTZ-801 –40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218BSTZ-RL801 –40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218BST-105 –40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218BST-RL105 –40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218BSTZ-1051 –40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218BSTZ-RL1051 −40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218-65PCB Evaluation Board (Supports -40/-65 Grade)
AD9218-105PCB Evaluation Board (Supports -80/-105 Grade)
1
Z = Pb-free part.
Rev. C | Page 25 of 28
AD9218
NOTES
Rev. C | Page 26 of 28
AD9218
NOTES
Rev. C | Page 27 of 28
AD9218
NOTES
Rev. C | Page 28 of 28