The ITRS Roadmap – A Preview

Gate Oxides – Physics and Technology

Reading: Chapter 7

Note that we are operating at 50% of dielectric breakdown (~10MV/cm), and are
working with thicknesses that we definitely expect to allow tunneling
EE231 – Vivek Subramanian Slide 6-1 EE231 – Vivek Subramanian Slide 6-2

Conduction in insulators (specifically, SiO2) • Low fields: Tunneling Currents

• Three mechanisms: – No FN tunneling, i.e., no “thinning” of oxide
– Direct tunneling – requires a fairly thin oxide for significant current (<3nm) – Mainly direct tunneling
– Fowler-Nordheim tunneling – electrical “thinning” of oxide allows tunneling • Traps can increase current
– Dielectric breakdown – physical damage forms conductive path through oxide • Wave function shape will result in some very small current even in
thicker oxides
Fowler − Nordheim
• Thin oxides (<2nm) have substantial direct tunneling due to non-
J = KE Ox
2
e − B / EOx zero wavefunction across barrier
Cathode Anode ≈ He − B / EOx direct J

determined by ϕ b • Intermediate fields: tunneling Direct FN

3.2 eV
– FN tunneling
poly Si B ~ 270MV/cm for SiO 2
SiO2 Si
8π 2mOx ϕ b3 / 2 T Ox
B=
3hq • High fields:
FN 4V
V

q 3 mn – Breakdown tunneling
K=
8πhmOxϕ b

EE231 – Vivek Subramanian Slide 6-3 EE231 – Vivek Subramanian Slide 6-4

1
 Breakdown Quantification
Dielectric Reliability
• Methods of characterizing breakdown
• Why do we care? – Dielectric Strength
• Ramp voltage till dielectric breaks down. Measure multiple
– Breakdown – creates conductive path between gate and channel. devices to identify intrinsic breakdown vs. defects
FET functionality fails • Indicates peak field that can be applied
– Damage – trapping, etc., causes VT shifts, degrading circuit • 10MV/cm for SiO2, 1MV/cm for Si, ~1-5MV/cm for most
performance high-K dielectrics
• Typically operate at 30% - 50% of breakdown strength – limit
• Applications of reliability phenomena: on oxide thickness scaling for a given technology node.
Oxide defect
– SONOS Memories log J

– Antifuses (FPGAs, Memories, etc.)

Intrinsic breakdown
• We need to develop models for dielectric reliability to aid
quantitative analysis and design.
V

EE231 – Vivek Subramanian Slide 6-5 EE231 – Vivek Subramanian Slide 6-6

Breakdown Quantification Statistical Analyses

• Methods of characterizing breakdown
– Time-dependent dielectric breakdown (tddb)
• Apply constant voltage (typically >50% of VBD) or constant current.
• Breakdown occurs when voltage across dielectric drops (constant
current) or current suddenly increases (constant voltage).
• Indicative of lifetime of oxide under normal operation; better
indicator than VBD.
• Can integrate to find charge to breakdown (QBD).
• Use statistics of several devices to find “intrinsic” tddb
• Breakdown tends to be heavily affected by defects.
– Multiple devices must be measured to confirm accuracy of data
– Statistics provide information about dielectric quality and defects
Type of plots:
1) Cumulative distribution (Qbd vs. %)
2) Weibull plot (expands tail to make defects and early
breakdown more visible)
f is % failure

breakdown
voltage
slow rise is due to trapping

time
EE231 – Vivek Subramanian Slide 6-7 EE231 – Vivek Subramanian Slide 6-8

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 Qualitative models of oxide breakdown Effects at the anode
• Hole generation and trapping model • Both models dictate that bond-breaking / impact ionization at the
– Impact ionization at anode produces holes, that are back-injected towards anode is a critical process. We can see this empirically.
cathode and trapped in oxide.
1) Electron is injected to anode

3) Holes are trapped, increasing 2) Impact ionization

tunneling current until breakdown forms hot hole
We can inject from the gate to the substrate or
• Anode physical damage model vice versa
– Recombation of energetic electrons at anode causes physical damage to High mechanical stress at gate interface makes
oxide. bonds weaker, causing asymmetry in QBD

Energy release causes

damage, which propagates
Gate
back to the anode Substrate

EE231 – Vivek Subramanian Slide 6-9 EE231 – Vivek Subramanian Slide 6-10

Effect of Field / Energy The hole generation / trapping model

• Both models dictate that the energy at the anode is critically important. • Concept:
We can see this empirically. • Electrons are injected from cathode
• Recombination at anode causes impact ionization
• Hot hole is injected towards cathode
• Hole is trapped in oxide, increasing leakage and causing oxide wearout
In
c over time
re
as
in
g ele
ctr
on I hole ∝ I g e −80 / EOx
en
er
gy I hole
efficiency = ∝ e −80 / EOx
Ig

EE231 – Vivek Subramanian Slide 6-11 EE231 – Vivek Subramanian Slide 6-12

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 Dependence on electric field
Effect of hole trapping
High field 1
TBD ∝
• As seen in the previous section, VT shift can be either positive or
J ⋅η
negative
• The trap generation has numerous consequences on reliability: electron tunneling ∝ e 270 / E ⋅ e80 / E ∝ e 350 / E
– Nit generation J ∝ e −270 / EOx
log T BD
– Oxide damage 350 MV/cm
– SILC (Stress induced leakage current) Hole generation
η∝e −80 / E Ox

– Breakdown
1
damage, electron traps EOx
15 V

n+ defect Advantage: We can now do

p
no breakdown: critical amount of accelerated testing by using a
charge- hole fluence, also critical amount higher field and extrapolating
trapping of trap density (#/cm3) lifetime

EE231 – Vivek Subramanian Slide 6-13 EE231 – Vivek Subramanian Slide 6-14

Model Comparison Questions

• Hole generation model predicts an exponential dependence on 1/E
• Physical damage model would be better fit by an exponential • How do you expect reliability to scale as we scale oxide
dependence on E
−γEOx / kT thickness? Think in terms of the effect of:
BDT ∝e
• Both models work reasonably well – Direct vs. FN tunneling
– 1/E works better at high fields
– E works better at low fields
Log τBD – Interfacial stress
1/E model

– ITRS Voltage projections

E model

EE231 – Vivek Subramanian Slide 6-15 EE231 – Vivek Subramanian Slide 6-16

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 Modeling defect-induced breakdown Oxide Leakage: An upcoming brick wall
• We would really like a model that explained the “early” breakdown
events (the previous models only explain the intrinsic breakdown
behavior.
• We model this by assuming that all early breakdown is caused by
defects, which result in an effective “thinning” of the oxide.

XOx

GTeff / VOx
Xeff
TBD = τ 0 e G / EOx = τ 0 e
Oxide area = A cm2 ,
Defect density = D cm-2
probability that an oxide contains no defect: e-AD
probability of containing 1+ defects is 1-e-AD~AD

EE231 – Vivek Subramanian Slide 6-17 EE231 – Vivek Subramanian Slide 6-18

Gate Stack Scaling Limits The Defending Champion

Material properties
• non-crystalline insulator
• very high energy gap

SiO 2 • easy to grow on Si

• easy to integrate in a process
• Interface states can be
electrically neutralized (H2-anneal)
• stable and insensitive
to following process-steps
• excellent scaling capabilities
• no real candidates for replacement (?)
• etc...
The extraordinary properties of SiO2
are the basis of the success of MOS-technology
however there is a limit

EE231 – Vivek Subramanian Slide 6-19 EE231 – Vivek Subramanian Slide 6-20

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 State-of-the-art (SiON) Dielectrics
• OI-SiN (Tsujikawa et al., VLSI 2002) High-K dielectrics
• EOT = 0.9nm, Tphys. = 1.4nm, Jg = 100A/cm2

Ideal film structure:

SiN with a few atomic
layers
of SiO2 at SiN/Si interface

• Improved SiN (Matsushita et al., VLSI 2004)

• EOT = 0.73nm, Jg = 88 A/cm2, gm = 92% SiO2 (96% extra nitridation)

EE231 – Vivek Subramanian Slide 6-21 EE231 – Vivek Subramanian Slide 6-22

High-K dielectrics
– an overview
Issues with High-K gate dielectrics
• High-K dielectrics have two
advantages: • Process Integration
– They enable use of thicker films – An interfacial high-K/SiO2 intermediate compound is usually
for the same EOT, resulting in formed due to oxygen diffusion to the Si interface. This
lower leakage dramatically reduces EOT.

– They typically have better K/VBD

ratios than SiO2, allowing the use – Materials often become crystalline at elevated temperatures,
of smaller EOTs for a given VDD. resulting in increased leakage. This constrains thermal budget

• Disadvantages:
– Complex process integration • Performance Issues
– Mobility is usually degraded due to high Dit
– Usually have smaller bandgap,
which results in increased low-field
leakage – Reliability / uniformity is still a major question mark.

EE231 – Vivek Subramanian Slide 6-23 EE231 – Vivek Subramanian Slide 6-24

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 The Challengers
High-k: Material Requirements
Al2O3 8-11.5 NdAlO3 22.5
AlxSiyOz PrAlO3 25 • Barrier height and permittivity
(Ba,Sr)TiO3 200-300 Si3N4 7
• Thermodynamics and stability
BeAl2O4 8.3-9.43 SmAlO3 19
CeO2 16.6-26 SrTiO3 150-250 – Maintain capacitance after thermal process
CeHfO4 10-20 Ta2O5 25-45 • Dielectric film morphology
4
CoTiO3/Si3N4 Ta2O5-TiO2 – Amorphous versus crystalline

Conduction-band offset (eV)

SiO2
EuAlO3 22.5 TiO2 86-95 RTCVD poly
• Interface quality 3
Si3N4
HfO2 26-30 TiO2/Si3N4
– Dit and EOT contribution, growth 2 ZrO2
Hf silicate 11 Y2O3 8-11.6 Al2O3 HfO2 ZrO2
La2O3 20.8 YxSiyOz • Gate material compatibility Y2O3
1 Ta2O5
LaAlO3 23.8-27 ZrO2 22.2-28 • Deposition method BaZrO3
LaScO3 30 Zr-Al-O • …
0
0 10 20 30 40
La2SiO5 Zr silicate 11-12.6
k-value
MgAl2O4 8.3-9.4 (Zr,Sn)TiO4 40-60

EE231 – Vivek Subramanian Slide 6-25 EE231 – Vivek Subramanian Slide 6-26

Hf-based dielectrics PVD Technique “Hf-metal_sputter + RPO”

Starting Surface
HfO2 17-25 crystallizes at low temperatures Si sub. Hf-metal_sputter: pure Hf-metal (from pure
target) can be deposited onto any starting
Hf silicate ~11 phase separation at high temp. Hf Hf Hf Hf surface uniformly and in high density.

nitrided Hf silicate ~ 9-11 increased temp. stability CO (controlled oxidation): the Hf-metal
Hf-metal should be oxidized uniformly and preferentially
Hf-Al-O 9-25 wide range of k-values possible
Si sub. at low temperatures and selective to Si.
charge in the layer (due to Al?)
Hf-metal_sputter
Considered for DRAM

Oxidation Rate (a.u.)

stacked/capped layers combine optimum properties O* O*
O* O* O* O* 1.8
compatibility with poly-Si 1.6 Hf HfO2
HfO2 1.4
Interface 1.2 Si interface
„ Hf-based materials have received most attention Si sub. 1.0 Si-sub.
over the last years (Controlled Oxidation)
T1 T2 T3 ① T1 ② T2 ③ T3
Treatment Temperature CO time

EE231 – Vivek Subramanian Slide 6-27 EE231 – Vivek Subramanian Slide 6-28

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 High-k Stacks: Leakage Current Reduction
CVD Techniques
„ leakage current reduction
10+1 Si
O
of several orders of
ALCVD-HfO2
2 tr e
nd
magnitude obtained with
1 high-k materials
Metal Organic CVD Atomic Layer Deposition
enhanced high k scalability

Si
10-1 „
HfCl4

ON
TDMAS** for metal gates compared

tre
Jg at Vfb-1V (A/cm2)
10-2 to poly gates

nd
N2 purge metal poly-Si
+ gate gate
n 10-3
+
o 10-4
H2 O
TDEAH* O2 metal
gate
poly-Si
gate
10-5
* Tetrakis(diethylamido)Hafnium • based on well-separated saturating gas
**Tetrakis(dimethylamido)Silicon solid surface reactions 10-6
PVD-HfO2
• volatile precursors introduced separately 0.5 1.0 1.5 2.0
EOT(nm)

EE231 – Vivek Subramanian Slide 6-29 EE231 – Vivek Subramanian Slide 6-30

Impact on mobility: ~20% lower

High-k Stacks: Issues (with polySi)
500
Key Focus Areas 450
universal
electron
implanted poly-Si(A) HfO2 poly-Si
Lot#: HK02205 Wafer#: D23 Lot#: HK02089 Wafer#: D03 400 mobility 1.7 nm SiON
350 + 5 cy HfO2
pMOSFET nMOSFET NFIX

µeff (cm2/Vs)
-4
10 ¾ Reduce + 10 cy HfO2
300
ID
ID
1.5nm SiON 1.5nm SiON hysteresis/VT 250
SiON
10
-6
instability - 200 NIT
charge trapping 150
Current (A)

Vd = -0.02 V Vd = +0.02 V
-8 10x1_D1T 10x1_D1T 100
10
50
¾ Improve gm,
0
10
-10 ueff performance 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

(esp. nMOS) Eeff(MV/cm) RS =70Ω

-12 IG Remote charge scattering (and phonons) can be reduced by:

10 IG
¾ Control VT
⇒ high-k engineering (decrease Q); e.g. HfSiON
and Cinv (esp.
-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 -0.5 0.0 0.5 1.0 1.5 2.0
⇒ interface engineering (increase r); e.g. engineered SiON
Gate Voltage (V) Gate Voltage (V) pMOS)
⇒ screening of RCS; e.g. with metal gate (see later)

EE231 – Vivek Subramanian Slide 6-31 EE231 – Vivek Subramanian Slide 6-32

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 Gate Electrodes Gate Electrode Materials

EE231 – Vivek Subramanian Slide 6-33 EE231 – Vivek Subramanian Slide 6-34

Metal gates: Other Requirements

Metal Gates: Work function Requirements
• Compatibility
Single – Low resistivity
Single Metal/FUSI Dual
Metal/FUSI + tuning Metal/FUSI – Appropriate workfunction
4.1eV (n+poly) NMOS • Or tunable workfunction
– Good interface with gate dielectric
mid-gap mid-gap + 0.2eV Band-edge
• Manufacturability
NMOS
NMOS – Easy to deposit – CVD process available
4.65eV (mid-gap)
PMOS
PMOS – Easy to etch and clean-up
• Integration
– Stable with thermal budget
5.2eV (p+poly) PMOS
– Amorphous – crystalline (nano crystals)
Planar SOI Low standby High
Multiple gate power performance • No phase change in Tbudget
– Process scheme
EE231 – Vivek Subramanian Slide 6-35 EE231 – Vivek Subramanian Slide 6-36

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 Metal Gate Integration – Dual WF Workfunction Engineering
• Deposit and etch of the N and P type metal separately. Implant Activation Ni deposition
– The first metal etch has to be very selective and non-damaging towards e.g. As, P, B, etc. Anneal
the dielectric. (May be skipped) Ni
– Or the dielectric has to be re-grown [SiON] or re-deposited [high-k]
selectively.

Poly-Si
• Sequential deposition of N and P type metal – modification of one of
(or a-Si)
the two gate electrodes.
– The right materials and modification
process has to be found given both
an N and P type electrode. 1023
Ni
– Alloying RTP silicidation Dopant concentration

Concentration (at/cm3)
1022 Si

Counts (A.U.)
Dopant segregation As 8E15
1021
to surface
NiSi Low solubility 1020
of dopants in NiSi
• Deposition of single metal or FUSI and modification to meet N and As 2E15
Dopants snowplowed,
PMOS by implantation, chemical reaction segregation to oxide
1019
0 25 50 75 100 125 150
Depth (nm)
interface

EE231 – Vivek Subramanian Slide 6-37 EE231 – Vivek Subramanian Slide 6-38
J.Kittl, internal data

Workfunction Engineering Conventional materials considered

5.2 • Pure metals
5.1 NiSi NiPt PtSi – Selected pure metals are promising especially for pMOS.
5 (group III) • Pt, Ir, Ru (PMOS like – expensive – difficult to etch)
Workfunction (eV)

4.9 NiSi
• Ti (4.56eV) and Mo (4.72eV) on Si3N4 (Q.Lu, VLSI 2000)
4.8 (undoped) • Ta/AlN (4.9eV) and Hf/AlN (4.4eV) (C.Park, VLSI 2003)
4.7 • Pure metal – φM adjusting
4.6 – Modification by implantation or silicidation (see before)
4.5 PtSi • (110) Mo / N implantation (4.53 – 4.94eV) (Q.Lu, VLSI 2001)
NiSi
4.4 (group V) (on High-k) • Metal nitrides
4.3 – Makes the metals more stable (silicon incorporation gives additional stability)
4.2 • TiN (4.8eV),TaSiN (4.19 – 4.27eV) on HfO2 (S.Samavedam, VLSI 2002)
4.1 • HfN (4.65eV) (H.Yu, VLSI 2003)
• Alloying / Interdiffusion
• WF tuning possible on SiOx dielectrics – Linked to the possible implementation scheme for CMOS
• No significant separation with dopants for FUSI/high-k • Ni and Ti (I.Polischuk, IEEE EDL, April 2002)
• Could be Fermi Level Pinning • RuTa (4.2 – 5.2eV) (V.Misra, IEDM 2002)

EE231 – Vivek Subramanian Slide 6-39 EE231 – Vivek Subramanian Slide 6-40
A,Lauwers, internal data

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 Impact of dielectric – e.g. Ru
• φm(Ru) on SiO2 and HfO2
MOCVD Ru results after FGA
-1.25 1.25
MOCVD Ru/HfO2 Measured Ru/SiO2
ΦM~ 5.2 eV
Measured Ru/HfO2

-1.00 1.00
FLATBAND VOLTAGE ( V )

-0.75 0.75

-0.50 0.50
MOCVD Ru/SiO2
ΦM~ 4.2 eV

-0.25 0.25
0 2 4 6 8 10 12 14 16 18 20
EOT ( nm )

„ Large difference φm(SiO2) ↔ φm(HfO2)

EE231 – Vivek Subramanian Slide 6-41

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