3 SPACE VECTOR MODULATION FOR FOUR-LEG VOLTAGE

SOURCE INVERTERS

3.1 FOUR-LEG VOLTAGE SOURCE INVERTER

The schematic diagram of a four-leg inverter is shown in Fig. 3.1. This topology is

known to produce balanced output voltages even under unbalanced load conditions[10].

Due to the additional leg, a four-leg inverter can assume sixteen topologies which is twice

the number of topologies a conventional three-leg inverter can assume[11]. These

topologies are shown in Fig. 3.2. The topologies are similar to the three-leg inverter with

the fourth leg being connected either to the negative rail (Fig. 3.2(a)) or to the positive rail

(Fig. 3.2(b)). Each of these topologies is referred to as a switching state. Thus a four-leg

inverter can produce sixteen switching states.

La Ia
Vg a
f b
c

n
Lf

Fig. 3.1. Topology of a four-leg voltage source inverter.

27
p p p

a b a a b
c b c c
f f f
n n n
pnnn ppnn nppn
p p p

a a b a b
b c c c
f f f
n n n
nppn nnpn pnpn

p p

a a b
b c c
f f
n n
pppn nnnn

Fig. 3.2(a). Topologies of a four-leg voltage source inverter.

28
p p p

a b a a
c b c b c
f f f
n n n
pnnp ppnp npnp
p p p

a a b a
b c c b
f f c f
n n n
nppp nnpp pnpp
p p

a a
b b
c c f
f

n n
pppp nnnp

Fig. 3.2(b). Topologies of a four-leg voltage source inverter.

29
3.2 VOLTAGE SPACE VECTORS

Space vector modulation for a four-leg voltage source inverter is based on the

representation of the phase voltage space vectors in the α , β ,γ plane. Considering for

example the first topology of Fig. 3.2(a) which is repeated in Fig. 3.3 for the sake of

convenience, we see that the phase voltages Vaf, Vbf, Vcf are given by

Vaf = Vg
Vbf = 0 ….. (3.1)
Vcf = 0 γ
β
p

a
Vg
b
c f Vγ
Vβ

n α
Vα
(a) (b)

Fig. 3.3(a) Topology 1 (pnnn) of a four-leg voltage source inverter.

(b) Representation of topology 1 in α , β ,γ space.

The transformed voltages in the α , β ,γ space can be obtained using the transformation

 1 1 
1 - - 
V α  V af  2 2
 
    2  3 3 ….. (3.2)
V β  = T V bf  , T= 0 -
V  V  3  2 2 
 
 γ   cf  1 1 1 
2
 2 2 

30
 Thus, topology of Fig. 3.3 could be represented by the vector ‘pnnn’ as shown in

Fig. 3.3(b) and in Fig 3.4(a). A similar procedure could be adopted for all the topologies of

Fig. 3.2. This would generate sixteen vectors. These are known as switching state vectors

(SSVs). These SSV’s are shown in Fig. 3.4. in the space of transformed phase voltages

{Vaf, Vbf, Vcf}, where α , β plane is the plane in which Vaf + Vbf + Vcf = 0, and γ is the

axis of the zero sequence component. The tips of these vectors when projected onto the

α , β plane would form a regular hexagon as shown in Fig. 3.4(b).

Vγ = Vg pppn
ppnn

Vγ = 2 Vg/3 nppn

npnn pnpn
γ
Vγ = Vg/3 pnnn

nnpn β
Vγ = 0 pppp
nnnn
α

ppnp
Vγ = -Vg/3 nppp

npnp pnpp

Vγ = -2 Vg/3 pnnp
nnpp
Vγ = -Vg
nnnp

Fig. 3.4(a). Switching state vectors of a four-leg inverter.

V3(npnx) V2(ppnx)

2
3 1
pppx 2Vg/3
V4(nppx) V1(pnnx)
nnnx
4 6

5 x ∈ (p,n)

V5(nnpx) V6(pnpx)

Fig. 3.4(b). Projection of the sixteen vector into α , β plane.

31
3.3 SPACE VECTOR MODULATION

The required phase voltages at the output of the inverter could be represented by an

equivalent vector, rotating in a 3-D vector space (unlike the three-leg VSI where the

required output line voltages are represented by a vector rotating in the 2-D space). Space

vector modulation for four-leg inverter, as in a three-leg inverter involves identification of

adjacent switching state vectors, calculation of their duty-cycles and sequencing of these

vectors. The first two steps are described in detail in [10,13] are reviewed here for the

sake of completeness.

3.3.1 IDENTIFICATION OF ADJACENT VECTORS

Identification of adjacent vectors is a two step process. At first, the vector space of

Fig. 3.4(a) is divided into six triangular prisms (P1-P6). At any given instant the required

output voltage vector is present in one of these six prisms as can be seen in Fig. 3.5, where

the reference vector happens to be in prism1. The flowchart used to determine the prism

information at any given instant is shown in Fig. 3.6, where Vα , Vβ are obtained from

(3.2), and is essentially the same as sector identification for the three-leg inverter.

32
 pppn

ppnn

pnnn
pppp
nnnn

V ref γ
ppnp

α
pnnp
nnnp −β

Fig. 3.5. Reference vector in prism1.

+ V α Vβ
-

+ Vβ - + -
Vβ

| Vα | ≥ 3 | Vβ | | Vα | ≥ 3 | Vβ | | Vα | ≥ 3 | Vβ | | Vα | ≥ 3 | Vβ |

y n y n y n y n
Prism1 Prism2 Prism4 Prism5 Prism3 Prism2 Prism6 Prism5

Fig. 3.6. Flowchart used to determine prism information.

Once the prism information is determined the next step is to identify the

tetrahedron in which the reference vector is present. To do this each prism is further

subdivided into four tetrahedrons - thus leading to a total of 24 tetrahedrons. Each

tetrahedron is formed by three non-zero switching state vectors [11,13] as shown in Fig.

3.7 for prism1(P1). Table 3.1 shows how these tetrahedrons could be identified based on

the sign of required phase voltages at the output of the inverter. Thus the three adjacent

active vectors are determined.

33
 Table 3.1: Identification of tetrahedrons

Prism Tetrahedron Active Vectors Condition

P1 T1 ppnp, pnnp, pnnn Va>0, Vb<0, Vc<0
T2 pnnn, ppnn, ppnp Va>0, Vb>0, Vc<0
T13 nnnp, pnnp, ppnp Va<0, Vb<0, Vc<0
T14 pppn, ppnn, pnnn Va>0, Vb>0, Vc>0
P2 T3 npnn, ppnn, ppnp Va>0, Vb>0, Vc<0
T4 ppnp, npnp, npnn Va<0, Vb>0, Vc<0
T15 nnnp, npnp, ppnp Va<0, Vb<0, Vc<0
T16 pppn, ppnn.,npnn Va>0, Vb>0, Vc>0
P3 T5 nppp, npnp, npnn Va<0, Vb>0, Vc<0
T6 npnn, nppn, nppp Va<0, Vb>0, Vc>0
T17 nnnp, npnp, nppp Va<0, Vb<0, Vc<0
T18 pppn, npnn, nppn Va>0, Vb>0, Vc>0
P4 T7 nnpn, nppn, nppp Va<0, Vb>0, Vc>0
T8 nppp, nnpp, nnpn Va<0, Vb<0, Vc>0
T19 nnnp, nnpp, nppp Va<0, Vb<0, Vc<0
T20 pppn, nppn, nnpn Va>0, Vb>0, Vc>0
P5 T9 pnpp, nnpp, nnpn Va<0, Vb<0, Vc>0
T10 nnpn, pnpn, pnpp Va>0, Vb<0, Vc>0
T21 nnnp, pnpp, nnpp Va<0, Vb<0, Vc<0
T22 pppn, nnpn, pnpn Va>0, Vb>0, Vc>0
P6 T11 pnnn, pnpn, pnpp Va>0, Vb<0, Vc>0
T12 pnpn, pnpn, pnnn Va>0, Vb<0, Vc<0
T23 nnnp, pnnp, pnpp Va<0, Vb<0, Vc<0
T24 ppnp, pnnn,pnpn Va>0, Vb>0, Vc>0

34
 [+ + +]
pppn

[++0]
ppnn

[+00]
pnnn pnnn
pppp V 0X
nnnn
V ref
V ref
V ref
[00-] ppnp
ppnp

[0--] pnnp
pnnp

[---]
nnnp

(a) (b)

Fig.3.7(a) Prism (P1) consisting of four tetrahedrons (T1,T2,T13,T14)

(b) Reference vector in tetrahedron1(T1).

3.3.2 Duty Cycle Calculation

Once the active vectors are determined, their duty-cycles are calculated based on

projections. This is illustrated for the case when the reference vector is in tetrahedron1(T1)

in Fig. 3.8, where the duty-cycles d1, d2, d3 for the active vectors ‘ppnp’, ‘pnnp’, ‘pnnn’

are obtained based on projections and the duty-cycle for the zero vector is obtained from

d0 = 1-d1-d2-d3 ..… (3.3)

pnnn
d3
V 0X
V ref d1

ppnp
d2
pnnp

Fig.3.8. Duty cycles for the active vectors.

35
 Under balanced load conditions the reference vector takes up a circular trajectory

in the α , β plane with the γ component being equal to zero. Under this condition the

reference vector traverses only twelve tetrahedrons (T1-T12) and the time it spends in each

tetrahedron is equal. This is indicated by the stair-case waveform in Fig. 3.9(a) where the

length of all the stairs is equal, indicating that the time spent by the reference vector in

each tetrahedron is the same. Fig. 3.9(b) shows the time spent by the reference vector in

each prism. It can be noted that since the reference vector traverses through two

tetrahedrons of a given prism consecutively; the sum of two consecutive stairs in Fig.

3.9(a) would give rise to one stair in Fig. 3.9(b).

Under small unbalance, the trajectory of the reference vector becomes elliptic, with

a varying γ component [10]. Under this condition the time spent by the reference vector in

each of these twelve tetrahedrons is not a constant as can be seen from Fig. 3.10(a). Fig.

3.10(b) shows the traversal of prisms under this condition.

Under balanced or small unbalanced operating conditions the reference vector

remains in only twelve tetrahedrons(T1-T12). However, during transients or during

extreme unbalance the reference vector could traverse tetrahedrons beyond twelve ( T13-

T24).

36
 Tetrahedrons
Tetrahedrons
T12

T1

Time
Time
(a)

P6
Prisms
Prisms

P1

Time
Time

(b)

Fig. 3.9. Traversal of tetrahedrons and prisms for a balanced load.

37
 Tetrahedrons
Tetrahedrons
T12

T1

Time
Time
(a)

P6
Prisms
Prisms

P1

Time
Time
(b)

Fig.3.10. Traversal of tetrahedrons and prisms for an unbalanced load.

38
3.3.3 Sequencing of Vectors

Once the active vectors are determined and the duty cycles calculated, the degrees

of freedom we have in the choice of a given modulation algorithm are

(1) The choice of the zero vector -

whether we would like to use nnnn or pppp or both,

(2) Sequencing of the vectors,

(3) Splitting of the duty cycles of the vectors without introducing additional

commutations.

Three such SVM algorithms are considered, namely:

1) The symmetric sequence - Scheme1

2) The highest current not switched sequence - Scheme2

3) The alternating zero vector sequence - Scheme3

The schemes analyzed here are similar to the ones found in literature for a three-

leg inverter operating under balanced load conditions as described in the previous chapter.

Scheme1 corresponding to SVM2, scheme2 corresponding to symmetric SVM4, and

scheme3 corresponding to SVM3. The scheme corresponding to SVM1 is not analyzed

here because it did not have any advantage under hard-switched conditions when

campared to the other schemes.

Each of these modulation schemes has been analyzed and its relative performance

with respect to switching loss and THD of the voltage at the output of the inverter is

assessed. The analysis is performed over the entire range of modulation index and for

both balanced and unbalanced load.

39
3.4 MODULATION SCHEMES

3.4.1 Symmetric sequence: Scheme1

The sequence of vectors applied in this scheme is shown in Fig. 3.11 for the case

when the reference vector is in tetrahedron 1. This scheme is expected to have low THD,

as in three-leg voltage source inverter, because of the symmetry in the waveforms. The

number of commutations in one sampling period is eight.

p p p p n p p p p p p p p n p p p p
p p n n n n n p p p p n n n n n p p
p n n n n n n n p p n n n n n n n p
p p p n n n p p p p p p n n n p p p
p
a
n
b p
n
p
c
n

p
f
n
d 0 d 1 d 2 d 3 d 0 d 3 d 2 d 1 d 0 d 0 d 1 d 2 d 3 d 0 d 3 d 2 d 1 d 0
4 2 2 2 2 2 2 2 4 4 2 2 2 2 2 2 2 4
Ts Ts

Fig. 3.11. Phase gating signals in scheme1.

3.4.2 Highest Current Not-Switched Sequence: Scheme2

This scheme is based on the fact that the switching losses are approximately

proportional to the magnitude of the current being switched and hence it would be

advantageous to avoid switching the inverter leg with the highest instantaneous current.

This is possible in most cases, because all adjacent SSV’s in a given tetrahedron differ in

the state of switches in only one leg. Hence, by using only one zero vector, nnnn or pppp

within a given tetrahedron, one of the legs does not have to be switched at all, as shown in

Fig. 3.12.

40
 However, since the choice of the non-zero SSVs is made based on the desired

output voltage vector and the phase and magnitude of the current is determined by the

load, it is not always possible to avoid switching the phase carrying the highest current. In

such a case the phase carrying the second highest current is not switched but the switching

loss savings are reduced. The splitting of active vectors about the zero vector as shown

below results in a significant reduction in the THD. The number of commutations in one

cycle is six.

p p p p p p p p p p p p p p
p p n n n p p p p n n n p p
p n n n n n p p n n n n n p
p p p n p p p p p p n p p p
p
a
n

b p
n

c p
n

p
f
n
d0 d1 d2 d2 d1 d0 d0 d1 d2 d2 d1 d0
d3 d3
4 2 2 2 2 4 4 2 2 2 2 4
Ts Ts

Fig. 3.12. Phase gating signals in scheme 2.

3.4.3 Alternating Zero Vector Sequence : Scheme3

In this scheme the zero vectors (pppp, nnnn) are used alternatively in adjacent

switching cycles so that the effective switching frequency is halved, as shown in Fig. 3.13.

However, the sampling period is still Ts, same as in the other schemes. The number of

commutations in one Ts is four and hence the switching losses are expected to reduce.

Current THD is significantly higher due to the existence of the harmonics at half the

sampling frequency.

41
 pnnn pnnp ppnp pppp ppnp pnnp pnnn nnnn
p
a n
p
b n
p
c n

p
f n
d3 d2 d1 d0 d1 d2 d3 d0
Ts Ts

Fig. 3.13. Phase gating signals in scheme3.

3. 5 ANALYSIS

3.5.1 Performance Comparison for Balanced Loads:

3.5.1.1 Total Harmonic Distortion:

The modulation schemes are analyzed for their harmonic performance using the

algorithm developed in the previous chapter for a three-leg inverter where the Fourier

components of the output voltage are calculated by summing up the Fourier components of

the individual pulses. The harmonics of the line currents are calculated by using the load

impedance information. This procedure is illustrated here for scheme1.

The neutral point potential (Vf) can be 0 or Vg, depending on the SSV’s. Hence the

phase voltages (Vaf, Vbf, Vcf - voltages between the inverter output and the neutral point)

can be accurately calculated as shown in Table 3.2 for tetrahedron 1.

Decomposition of the phase voltage switching waveform for scheme1 into sum of

pulses with period To as explained in chapter 2 is shown in Fig. 3.14 where a typical phase

42
voltage is decomposed in the kth switching interval from beginning of the phase voltage

period, where

fs
0 ≤ k ≤ -1 ….(3.4)
fo

Comparing each of the component pulses with Fig. 2.13 one can find that for the

pulse in Fig. 3.14(b)

d3  d d d 
dm = , Tm =  k − 1 + 0 + 1 + 2 .Ts ,Vm = Vg
2  4 2 2
…(3.5)

for the pulse in Fig. 3.14(c)

d3  1 d 
dm = , Tm =  k − 1 + + 0 .Ts ,Vm = Vg
2  2 4
…..(3.6)

Vg Vg Vg

0 0 0
d3/2 d3/2 d3/2 0.5+d0/4 d3/2

(k-1)Ts kTs (k-1)Ts d0/4+d1/2+d2/2 kTs (k-1)Ts kTs

(a) (b) (c)

Fig. 3.14. Phase voltage decomposition in one sampling period.

The duty cycles d1, d2, d3 and d0 are calculated as explained in section 3.2 and the

Fourier components of these pulses are obtained from equations (2.7) and (2.8).

Table 3.2. Output voltage pulse in tetrahedron1: Scheme1

SSV’s pppp ppnp pnnp pnnn nnnn pnnn pnnp ppnp pppp
Duty cycle d0/4 d1/2 d2/2 d3/2 d0/2 d3/2 d2/2 d1/2 d0/4
Va Vg Vg Vg Vg 0 Vg Vg Vg Vg
Vf Vg Vg Vg 0 0 0 Vg Vg Vg
Vaf 0 0 0 Vg 0 Vg 0 0 0

43
Fig. 3.15 shows the variation of THD (of phase voltage and phase current) with

modulation index for all the schemes. The results are similar to the three-leg inverter.

THD of phase voltage

0 0.866
Modulation index
Modulation index

(a)
THD of phase current

0 Modulation index 0.866

Modulation index

(b)

Fig. 3.15. Total harmonic distortion of (a) Phase voltage ,( b) phase current (fs/fo = 36).

3.5.1.2 Switching loss

The switching losses are assumed to be proportional to the product of the voltage

across the switch and the current through the switch at the instant of switching. Since the

voltage across the switch is the bus voltage, it is considered to be a constant. Thus the

losses are proportional to the current during switching.

44
 Under balanced load conditions the neutral leg carries only the high frequency

ripple as shown in Fig. 3.21(a). Hence the switching losses are expected to be similar to

the three leg inverters. Losses for schemes 1 and 3 are independent of the load whereas

for scheme 2 the losses depend on the load power factor and its loss performance has

been optimized as described in section 3.5.2

Fig. 3.16 shows the relative variation of switching losses with load power factor

for the three schemes.

Relative switching loss
R elative sw itching loss

L oad pow er factor

Load power factor angle

Fig.3.16. Relative switching losses as a function of load power factor angle.

3.5.2 Performance Comparison for Unbalanced Load

3.5.2.1 Total Harmonic Distortion

Depending on the load and load power factor angle (lpf) there are several cases of

unbalance that could be studied. Two cases are presented here.

(1) Load power factor angle unbalance: Here each of the three phases are assumed

to be carrying full load current, however the lpf of ‘phase a’ is assumed to vary from − 90°

to 90° . Fig. 3.17 shows the variation of THD of ‘phase a’ voltage when the lpf is leading

and lagging. The curves are not smooth because the THD was calculated at discrete points.

45
 THD of phase voltage
0 90o
Load power factor angle

(a)
THD of phase voltage

0 90o
Load power factor angle

(b)

Fig. 3.17 Variation of THD of phase voltage with load power factor
(a) leading, b) lagging

(2) Load power unbalance : In this case the lpf is assumed to be unity, however the

load power taken by ‘phase a’ is assumed to vary from 100 % to 10 %. Fig. 3.18 shows the

variation of THD of ‘phase a’ voltage with load power. It can be observed from the figure

that the THD increases with decrease in load power but variation is very small.

46
 THD of phase voltage
100% 10%
Load power

Fig. 3.18 Variation of THD of phase voltage with load power

3.5.2.2 Switching Losses

Load power factor angle unbalance: Here though the load currents are all of the same

magnitude, the currents through the filter inductors and hence the switches are dependent

on the load power factor. Fig. 3.19 shows the variation of total switching losses, of all the

switches, with load power factor. This shows that with increasing load power factor angle

unbalance the switching losses invariably tend to increase. The extent to which they

increase, however, is dependent on the exact power factor angle and also whether it is

leading or lagging.
Relative switching loss

Load power factor angle

(a)

47
 Relative switching loss Load power factor angle

(b)

Fig. 3.19 Relative switching loss for

(a) Leading load power factors
(b) Lagging load power factors

3.6 SIMULATION AND EXPERIMENTAL RESULTS

A 150 kW inverter was simulated for both balanced and unbalanced load
conditions. The parameters used were La = 1.25 mH, Lf = 0, C = 210 uF, Vg = 850 V, fo =
60 Hz, fs = 2160 Hz. The phase current waveform and its spectrum for each of the schemes
for balanced load conditions are shown in Fig. 3.20
The simulated phase currents, output voltages and the current through the neutral
leg for balanced and unbalanced load conditions are shown in Fig. 3.21. Scheme 1 was
used for Fig. 3.21. The load was assumed to be 255 A peak for the balanced case. For the
unbalanced case the load currents were assumed to be 255∠0 ° A, 127.5∠60 ° A, and

63.75∠0° A for the three phases ‘a’, ‘b’, and ‘c’ respectively.
Based on the analysis and simulation, scheme2 was implemented on a prototype
inverter and the results are as shown in Fig. 3.22.

48
 Scheme1

Scheme2

Scheme3

(a) (b)
Fig. 3.20 a) Phase currents and b) Spectrum of phase currents for the three space vector
modulation schemes.

Line Currents

Output Voltages

Neutral Current

Fig. 3.21. Line currents, output voltages and current through neutral leg for
a) Balanced load, b) Unbalanced Load.

49
20V/div
20V/div

(a)

20dB/div
20db/div fs

(b)

Fig.
3.22. Experimental output voltage and spectrum of output voltage for scheme 2.

( Vg = 75V, fs/fo = 40)

50
3.7 PERFORMANCE SUMMARY

This chapter analyzed the most important modulation schemes for both balanced

and unbalanced load conditions for a four-leg inverter. The analysis was performed over

the entire range of modulation index and over the entire range of load power factor for the

balanced load conditions. Two typical unbalance conditions - load power factor angle and

load magnitude, were studied for harmonic distortion and switching losses. Table 3.3

summarizes the results of the analysis. The analysis clearly brings out the trade off’s to be

observed between the THD and switching losses i.e., a scheme with low THD usually has

high losses. The study of unbalanced load conditions reveals that both THD and losses

increase. Overall scheme 1 should be used at low switching frequencies where the

switching loss is small. At high switching frequencies scheme 2 is recommended

Table 3.3. Relative performance of various modulation schemes (four-leg)

Modulation Schemes Scheme-1 Scheme-2. Highest Scheme-3. Alternating

Symmetric Current not Switched Zero Vector
No. of commutations in Ts 8 6 4
No. of switching states in Ts* 10 7 4
Dominant Harmonic fs fs fs/2
Balanced Load
Relative Losses 1 0.5-0.63** 0.5
THD at low mod. Index Least
THD at high mod. Index Least Highest
Unbalanced Load
Relative Losses-lpf 1-1.41 0.5-0.95 0.5-0.7
(leading 00-900)
Relative Losses-lpf 1-1.58 0.5-0.95 0.5-0.79
(lagging 00-900)
THD at leading lpf*** Least Highest
THD at lagging lpf*** Least Highest
THD at varying loads*** Least Highest
* Important in the design of digital modulator.
** Depending on load power factor.
*** Exact values are dependent on modulation index

51