Behavioral analysis and dimensioning of UMTS

transmitters baseband blocks

Nicola Ghittori1 , Andrea Vigna1 , Piero Malcovati2 Stefano D’Amico, Andrea Baschirotto
1
Department of Electronics, 2 Department of Electrical Engineering Department of Innovation Engineering
University of Pavia University of Lecce
Pavia, Italy Lecce, Italy
Email: nicola.ghittori,andrea.vigna,piero.malcovati@unipv.it Email: stefano.damico,andrea.baschirotto@unile.it

BPSK symbol OVSF

DPDCH1
Abstract— In this paper we present the design trade-offs for mapper spreader
G

dimensioning the baseband blocks (DAC and reconstruction DPDCH3 BPSK symbol OVSF
G
Root Raised
Cosine Digital
spreader Filter
filter) of a direct conversion transmitter for the UMTS standard. mapper

A Matlab model performs a time domain analysis to evaluate DPDCH5

BPSK symbol
mapper
OVSF
spreader
G
I BIT STREAM
the impact of each baseband block non-ideality on the overall
transmitter performance. The proposed approach has been used DPDCH2 BPSK symbol
mapper
OVSF
spreader
G
Q BIT STREAM

to design a 0.13 µm CMOS test-chip implementing the DAC + fil-

Re-Im to UPLINK Compl to
Compl Scrambler Re-Im

ter blocks. BPSK symbol OVSF Root Raised

DPCCH mapper spreader
G
Cosine Digital
Filter

I. I NTRODUCTION
Fig. 1. Model of UMTS digital modulator.
Recent trends in telecommunication research are devoted
to obtain a fully-integrated transceiver for third generation cos(wt)
standards, such as UMTS. In particular the direct conversion I BIT
antenna
STREAM
architecture is the one that offers the best possibilities of BASE BAND DAC Reconstruction
filter X
DIGITAL PA
a complete integration, due to the absence of intermediate PROCESSOR DAC Reconstruction
+
filter
X
Q BIT
frequency band-pass filters [1]. To develop a transistor im- STREAM
plementation of the blocks constituting such transceivers a sin(wt)
preliminary study of the overall architecture is necessary, in
order to achieve a dimensioning fulfilling the requirements of Fig. 2. Model of direct conversion transmitter.
the standard.
In this paper we focus on two analog baseband blocks
(digital-to-analog converter and reconstruction filter) of an and allows their correct distinction at the receiver. When the
UMTS direct conversion transmitter. In particular, the dimen- six DPDCHs are transmitted together, the spreading factor SF
sioning of the design parameters of such blocks is obtained for each of them is 4, while for the DPCCH is always set to
through behavioral simulations and verified by a test-chip 256. The chip sequences obtained are multiplied by a constant
realized in a 0.13 µm CMOS technology, with 1.2 V supply gain G (we assume that for all the data channel G = 1 and for
voltage. the control channel G = 0.6) and then summed up to obtain the
total I chip-stream and Q chip-stream. The two components are
II. M ODEL OF UMTS TRANSMITTER then converted into a complex chip-stream which is scrambled
The investigation on the design trade-offs of the baseband with a scrambling sequence in order to distinguish the various
blocks has been performed with time domain analysis of a UEs which are transmitting together. The complex sequence
direct conversion UMTS transmitter. Time domain analysis has is again separated into a real and imaginary part and filtered
been preferred to frequency domain one as it allows a more with a root raised cosine digital filter with a roll-off factor of
accurate description of the non-idealities of the blocks, at the 0.22. The frequency of the resulting bit-stream is increased by
expense of more computational time. A model of the transmit- means of a digital interpolator filter before reaching the analog
ter, from digital modulator to antenna, has been developed in part of the transmitter.
the Matlab environment. The scheme of the user equipment A typical architecture of a direct conversion transmitter is
(UE) digital modulator, as indicated by the UMTS standard reported in Fig. 2 [3]. A digital-to-analog converter followed
[2], is reported in Fig. 1. Six different dedicated physical by a reconstruction filter for each channel transforms the
data channels (DPDCH1-6) are transmitted together with a chip-stream into an analog signal. The waveforms are upcon-
dedicated physical control channel (DPCCH). The application verted at radio-frequency with two mixers and summed before
of orthogonal spreading codes increases the frequency of the reaching the power amplifier and the antenna.
informative sequences to the chip-rate (equal to 3.84 MHz) Each of the transmitter analog blocks has been modeled

0-7803-8834-8/05/$20.00 ©2005 IEEE. 388


IN 2 3
+ ax ax
1 2
ax
3 20
non-linearity transfer saturation
effects function limits
white noise
Fig. 3. Matlab model of analog blocks.
in Matlab taking into account four sources of non-idealities:
noise, distortion, an eventual transfer function and the satura-
tion effect coming from the available supply voltage (for our
design 1.2 V). The resulting model is depicted in Fig. 3. Noise
is modeled as a random Gaussian signal summed at the block
input, while distortion is modeled in terms of IIP2 and IIP3,
assuming the presence of a polynomial input-output relation
of the type:
y = a1 x + a2 x2 + a3 x3 . (1)
To further improve the effectiveness of the description, in the
digital-to-analog converter model we take into account also
the effect of parameters mismatch and of the decoding scheme
used (i.e. binary, segmented or thermometric).
III. D ESIGN TRADE - OFFS
As indicated by the standard, the quality of the trans-
mitted signal is specified evaluating the Error Vector Mag-
nitude (EVM) at the antenna. An ideal receiver performs
the demodulation of the transmitted signal, obtaining, after
the descrambling, a constellation of points in the complex
plane representing the received symbols. Each point of the
constellation (indicated as R) is compared with the ideal one
Z (i.e. the one coming from an ideal transmitter). The EVM
(expressed as a percentage) can be calculated as follows:

margin we however fixed the value of Nbit to 8.
 N
 2
1 |R − Z|
EVM =   N 2
· 100%, (2)
1 |Z|
where N is the number of symbols received. The EVM has
to be less than 17.5%. Moreover the power of the transmitted
signal has to be sufficiently low out of band, as specified by
the mask indicated in the standard, to avoid interference with
adjacent channels.
The number of bits Nbit used to quantize the digital signal
coming from the root raised cosine filter determines the level
of noise in the band of the UMTS signal. In Fig. 4 the EVM
as a function of the number of bits in the DAC is reported.
All the other blocks are supposed ideal, while the frequency of
the DAC is the lowest allowable, i.e. two times the chip-rate.
We note that increasing the number of bits to a value greater
than 8 does not improve the EVM (the saturation to a value
of 5.5% is due to the sinc effect introduced in the frequency
domain by the DAC zero order hold). So a quantization noise
corresponding to 8 bits in the signal bandwidth ensures that
the impact of the DAC resolution in the transmitter chain is
minimized.
22
OUT
EVM = 17.5%
18
Error Vector Magnitude [%]
16
14
12
10
8
6
4
4 6 8 10 12 14
Number of bits
Fig. 4. EVM as a function of DAC number of bits.
This level of quantization noise can be obtained with differ-
ent combinations of DAC resolution and sampling frequency.
Frequency planning affects also the digital interpolator filter
before the DAC and the reconstruction filter following the
DAC. An high sampling frequency increases the complexity
of the first block, a low sampling frequency makes difficult
the design of the analog filter. With a sampling frequency Fs
of 38.4 MHz (i.e. 10 times the chip-rate) an elliptic multirate
digital filter can be used between the digital signal processor
and the DAC to perform the up-sample of 5, while an analog
fourth-order Bessel low-pass filter can be used to suppress
the images of the signal around the integer multiples of Fs
well below the transmit mask. Moreover a value of Fs equal
to 38.4 MHz sets the oversampling ratio to about 10, giving
1.5 additional bits of resolution in the signal bandwidth with
respect to the original DAC resolution. To take a robust design
Digital-to-analog converters for telecommunication applica-
tions are usually realized with a current steering architecture as
it ensures the desired conversion frequency. Since we are sum-
ming nominally equal currents to obtain the analog values, we
have to take into account the effect of current source mismatch.
Each current source is modeled as a random Gaussian value
with mean value equal to I and relative standard deviation
equal to σrel . Fig. 5 sketches the EVM as a function of σrel .
A full thermometric architecture has been supposed. A relative
standard deviation of 2% is necessary to eliminate the effect
of mismatch on the transmitter. Moreover this value of σrel
allows us to obtain an INL/DNL less than 0.5 LSB [4]. Once
we have fixed the relative standard deviation, the area W L
of the unit current source can be derived by the mismatch
Pelgrom model [5]:
  
1 4A2
σrel = A2β + 2Vt , (3)
WL Vov
where Aβ , AVt are technology dependent parameters and Vov
is the overdrive voltage of the unit current source, which
is limited by the supply voltage. So at this early stage of
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 5.5 14

5 V = 300 mV
12
V = 350 mV
4.5

Error vector magnitude [%]

Error vector magnitude [%]

V = 400 mV
10
4
V = 450 mV
3.5
8

3
6
2.5

2 4

1.5
2
1 −2 −4 −3 −2
10 10
−1 10 10 10
Relative standard deviation In−band noise voltage [Vrms]

Fig. 5. EVM as a function of current source relative standard deviation. Fig. 6. EVM as a function of DAC output thermal noise.

20

design, and only with behavioral analysis, we can already EVM = 17.5%
18
know the area occupied by the digital-to-analog converters. 16
The choice of a full thermometric architecture mentioned V = 300 mV

Error vector magnitude [%]

14 V = 350 mV
before has been made on the basis of comparisons between V = 400 mV
the various decoding schemes. In fact, the binary or segmented 12 V = 450 mV

architecture, being less linear than the full thermometric one, 10

requires more matching on the unit current sources. Therefore, 8
with the thermometric scheme the area needed for the array
6
of unit current sources is reduced. The overhead due to the
digital decoder is negligible, thanks to the reduced number of 4

bits. Moreover, note that as in the model the current sources 2

mismatch generation is statistically independent between the
DAC of the I branch and the DAC of the Q branch, we are also
taking into account the effect of the two channels mismatch.
The next specification to be found is the thermal noise for
each block. Note that a noise source summed with the signal
at the DAC output can also be considered as the equivalent
input-referred noise source of the filter block. The admittable
value of noise power in the band of the signal at the DAC
output is found through simulation, for various values of signal
amplitude. This noise power budget will be evenly splitted
between the DAC and the filter during the circuit design. From
Fig. 6 we have that in order to minimize the effect of thermal
noise on the demodulation of the signal in all the cases, the
in-band noise voltage has to be less than 100 µVrms , which
means 70 µVrms as output-referred DAC noise voltage and
70 µVrms as input-referred filter noise voltage. The maximum
value of thermal noise allowable at the DAC output allows
the correct dimensioning of the unit current value I [6], while
the filter input noise has a great impact on the choice of the
resistors that implement the desired Bessel transfer function.
Third order and second order linearity of the reconstruction
filter are evaluated in terms of IIP3 and IIP2. The minimum
allowable values of such parameters depend on the signal
amplitude at the input of the filter and on the filter gain (both
are constrained by the available supply voltage). An extended
signal amplitude will push the requirements for IIP3 and IIP2
to high values. In Fig. 7 EVM as a function of the filter IIP3
0
5 10 15 20 25 30
IIP3 [dBm]
Fig. 7. EVM as a function of the filter IIP3, for different values of input
signal amplitude.
is reported, for different values of input signal amplitude and
with a filter gain equal to 8 dB. Similar analysis have been
performed with different values of filter gain. A design target
that can minimize the effect of IIP3 on the overall transmitter
in all the cases is 20 dBm. Carrying out the behavioral study
in the same way (Fig. 8), we can derive a design value for
the IIP2 of 50 dBm. The required large value of IIP2 can be
achieved using for the filter a fully differential architecture.
IV. CMOS IMPLEMENTATION
The specifications obtained with the previous behavioral
analysis are summarized in Table I and Table II. Matlab
simulation of the model including all the non-idealities con-
sidered before leads to an EVM of 1.5%. A test-chip of the
DAC and reconstruction filter has been realized in 0.13 µm
CMOS technology, with 1.2 V supply voltage. The circuital
details of the architecture and the chip microphotograph are
reported in [3]. A sequence of 8-bit digital words simulating
a chip-stream is obtained with Matlab and applied to the
test-chip through a pattern generator. The resulting measured
spectrum is reported in Fig. 9. The waveform at the filter

390
 50 0

45 V = 300 mV
V = 350 mV −10
40 V = 450 mV
Error vector magnitude [%]

Power spectral density [dBr]

V = 400 mV
35
−20
30

25 −30

20 EVM = 17.5%
−40
15

10
−50
5

0 −60
10 20 30 40 50 60 0 2 4 6 8 10
IIP2 [dBm]
Frequency [MHz]

Fig. 8. EVM as a function of the filter IIP2, for different values of input Fig. 9. Measured spectrum of an UMTS transmitted signal.
signal amplitude.

TABLE I
DAC SPECIFICATIONS

Parameter Value
Number of bits 8
Sampling frequency 38.4 MHz
Unit current source relative standard deviation 2%
Output-referred noise voltage 70 µVrms

Fig. 10. Measured filter output.

output is then re-imported in Matlab through a digitizing

oscilloscope and processed through an ideal receiver model
which performs the demodulation. An example of filter output
is reported in Fig. 10. The obtained EVM is 4%, which is
larger than the modeled one due to real implementation effects
and limited oscilloscope resolution, but which however lets
a robust design margin for the successive transmitter blocks.
This result validates the behavioral study carried out in the
previous paragraph.
V. C ONCLUSION
The procedure of dimensioning the baseband blocks of
an UMTS direct conversion transmitter is presented. The
minimum requirements needed to fulfill the specification of
the standard are obtained for various design parameters. A
transistor implementation of the DAC + filter block has been
realized on the basis of these architecture study. The effective-
ness of the procedure is proved by direct measurements.
ACKNOWLEDGMENT
This research has been partially supported by the Italian
National Program FIRB, Contract n◦ RBNE01F582.
R EFERENCES
[1] B. Razavi, ”Design consideration on direct-conversion receivers”, IEEE
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June 1997.
[2] 3rd Generation Partnership Program TS 34.121 V3.11.0.
[3] ”Enabling technologies for wireless reconfigurable terminals”, Italian
National Program FIRB, web-site http://ims.unipv.it/firb/.
[4] Y. Cong and R. L. Geiger, ”Formulation of INL and DNL yield estimation
in current steering D/A converters”, Proc. of ISCAS, vol. 3, pp 149-152,
May 2002.
[5] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, ”Matching
properties of MOS transistor”, IEEE J. Solid-State Circuits, vol. 24, pp.
1433-1439, Oct. 1989.
[6] A. Baschirotto, N. Ghittori, A. Vigna, and P. Malcovati, ”Design trade-offs
for a 10 bit, 80 MHz current steering digital-to-analog converter”, Proc.
of 2nd IEEE NEWCAS, pp 249-252, June 2004.

TABLE II
F ILTER SPECIFICATIONS

Parameter Value
Gain 8 dB
IIP3 20 dBm
IIP2 50 dBm
Input-referred noise voltage 70 µVrms

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