The Antenna Effect: Problem and

Solutions

John Liobe

8/5/2004 1
 Presentation Outline
• Mechanism of antenna condition
• Evolution of the definition of the Antenna
Ratio
• Design solutions to antenna violations
• Antenna Rule Checks in some common
DRCs
• Summary

8/5/2004 2
 Presentation Outline
• Mechanism of antenna condition
- Define “antenna”
- Describe plasma etching
- Examples
• Evolution of the definition of the Antenna Ratio
• Design solutions to antenna violations
• Antenna Rule Checks in some common DRCs
• Summary

8/5/2004 3
 Plasma Induced Damage (PID) =
Antenna Effect
• Occurs during manufacturing process
• Antennae are floating conduction layers
without shielding layer of oxide [16]
-effects poly and metal layers
• The random discharge of the floating node
could permanently damage the transistor

8/5/2004 4
 Thin Gate Oxide Damage
• Oxide tunneling current (F-N)
introduces more trap states [6]
• e- tunnel through the oxide-
semiconductor barrier
• e- gather energy and do damage
(break bonds) as they proceed
- Due to high electric fields
• Affects gate oxide breakdown
and transistor threshold voltages
• Defects enhance this effect
• Mechanism is not well
understood

8/5/2004 5
 Damage Characteristics
• Different kinds of
indicators for amount of
oxide damage
-QBD, breakdown
field, and Vth
• PID is proportional to
total charge that passes
through oxide [13]
• Oxide breakdown is very
sensitive to stress
polarity [24]

8/5/2004 6
 Plasma Etching
• Chips are usually
processed from the bulk
up
• Current processes have >
8 layers of interconnect
• Reactive Ion Etching
(RIE)
-standard method for
etching thin films in VLSI
manufacturing
• Antenna failures are
different for aluminum
and copper processes [4]

8/5/2004 7
 Example of Antenna Effect

8/5/2004 Adapted from [2] 8

Another Example of Antenna Effect

8/5/2004 Adapted from [1] 9

 Presentation Outline
• Mechanism of antenna condition
• Evolution of the definition of the
Antenna Ratio
- Plasma-based manufacturing processes
- Layout dependencies
- New antenna model
• Design solutions to antenna violations
• Antenna Rule Checks in some common DRCs
• Summary
8/5/2004 10
 Three Types of Plasma-based
Manufacturing Processes [7]

• Conductor layer pattern etching processes

-Amount of accumulated charge is proportional to
perimeter length
• Ashing processes
-Amount of accumulated charge is proportional to area
• Contact etching processes
-Amount of accumulated charge is proportional to area
of via

8/5/2004 11
 Classical Definition of Antenna
Ratio (AR)

• Ratio of total area and/or perimeter of

conducting layer attached to gate to gate area

Total Exposed Floating Conductor Area and Perimeter

AR = [15]
Total Gate Area

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 Extent of the Antenna Effect
• Classical theory predicts amount of degradation
is directly proportional to the AR.
- charging effect is identical for each metal
layer
• However, AR was found to have little or no
dependence on antenna effect [12].
• There are also layout dependencies that need to
be considered.

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 Layout Dependency of Charging
Damage
• Extent of charging damage is a function of
the geometry that is connected to the gate
- dense-line antennae are more susceptible
to PID
-electron shading effect
• RIE lag
-etch rate differences
• Plasma ashing and oxide deposition
8/5/2004 14
 RIE Lag

8/5/2004 Adapted from [14] 15

 New Model of Antenna Effect
• Etch time factor needs to be taken into account
Q
AR = [14]
A gate
-Q is the total accumulated injected charge into the gate oxide during the etching time
• Better predictor of antenna effect:
α J 2π ( P + p )
v g = v g max +
c ω (A + αa) [11]

-A is the area of the conducting layer with capacitance C exposed to plasma of current density J
-a is the area of the gate with capacitance a exposed to plasma of current density j
-α is the capacitance ratio
-P is the perimeter of the antenna capacitor
-p is the perimeter of the gate capacitor
-w is the angular frequency of the plasma power source

8/5/2004 16
Observations of PID Based on New
Model
• PID has little to no dependence on AR.
• Ratio of antenna capacitance to gate
capacitance is good indicator of PID.
• PID depends upon the frequency of the
plasma power source.
• For oxides <4nm, PID is not particularly
sensitive to stress current
• Increasing dielectric constant of gate
without increasing J can decrease PID.
8/5/2004 17
 Presentation Outline
• Mechanism of antenna condition
• Evolution of the definition of the Antenna Ratio
• Design solutions to antenna violations
-Description of each solution
-Comparison of solutions
• Antenna Rule Checks in some common DRCs
• Summary

8/5/2004 18
 Design Solutions to Reduce
Antenna Effect
Router Options
• Break signal wires
and route to upper
metal layers by
jumper insertion
• All metal being etched
is not connected to a
gate until the last
metal layer is etched

8/5/2004 19
 Design Solutions to Reduce
Antenna Effect (cont.)
Dummy transistors
• Addition of extra
gates will reduce the
capacitance ratio
• Problem of “Reverse “
Antenna Effect [5]
• PFETs more
susceptible than
NFETs

8/5/2004 20
 Design Solutions to Reduce
Antenna Effect (cont.)
Embedded Protection
Diode
• Connect reverse-
biased diodes to the
gate of transistor
• During normal circuit
operation, the diode
does not affect
functionality

8/5/2004 21
 Design Solutions to Reduce
Antenna Effect (cont.)
Diode Insertion after
placement and route
• Connected of diodes only
to those layers with
antenna violations
• One diode can be used to
protect all input ports that
are connected to the
same output ports

Cost = α * L + β * N [1]

8/5/2004 22
 Comparison of Proposed Solutions
Performance Process Antenna
Area Overhead Routing Obstruction
Degradation Sensitivity Reduction
Router
Options
Worst Severe √ Severe Good

Dummy
Best None None N/A Minimal
Transistors
Embedded
Protection
Diode
Worse Minimal √ Minimal Better
Insertion
Diode
Insertion after
Placement
Better Minimal √ Minimal Best
and Route

8/5/2004 23
 Presentation Outline
• Mechanism of antenna condition
• Evolution of the definition of the Antenna Ratio
• Design solutions to antenna violations
• Antenna Rule Checks in some common
DRCs
- Description of antenna rules
- Discussion of deficiencies in rules
• Summary

8/5/2004 24
 Design Rules for Some Current
Technologies – TSMC 0.18um [21]
• Metal antenna ratio is not cumulative
• Maximum drawn ratio of field poly perimeter area to the active poly
gate area connected directly to it 200.
• When the protection diode is not used, the maximum ratio of each
metal (for M1 to M5) perimeter area to the active Poly gate area
400.
• Antenna Ratio = 2[(L+W1)*t]/W2*l
-L: floating metal length connected to gate
-W1: floating metal width connected to gate
-t: metal thickness
-W2: connected transistor channel width
-l: connected transistor channel length

8/5/2004 25
 Design Rules for Some Current
Technologies (cont.) – IBM 0.13um [20]
• Antenna ratio is not cumulative
• Poly antennae larger than 100 are NOT
ALLOWED
• Floating gate devices with metal antennae
larger than 150 are NOT ALLOWED
• Every N-well is required to be tied down by
a N+ diode

8/5/2004 26
 Summary
• PID can have little-no dependence on AR
• Ratio of gate capacitance to the antenna
capacitance is a more important PID determinant
• PFETs can be more susceptible to PID than
NFETs
• Dynamic diode insertion after placement and
route is best technique to reduce antenna effect
• Modern CAD tools do not incorporate true
measure of antenna effect
8/5/2004 27
 Outlook
• Antenna effect will only become worse!
• Risk of yield and reliability excursions still must
by reduced by robust design
- Until PID phenomenon is completely
understood and eliminated
• The best solution for repairing antenna violations
is by hand
- Automated methods have serious drawbacks
- Fastest and most accurate manual
implementation is with useful information
8/5/2004 28
 References
• [1] L.-D. Huang et al., “A Polynomial Time-Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem,”
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 1, pp. 141-147, January
2001.
• [2] H. Shirota, T. Sadakane, M. Terai, and K. Okazaki, “A New Router for Reducing “Antenna Effect” in ASIC Design,”
Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 27.5.1-27.5.4, May 1998.
• [3] P.H. Chen, S. Malkani, C.-M. Peng, and J. Lin, “Fixing Antenna Problem by Dynamic Diode Dropping and Jumper
Insertion,” Proceedings of the IEEE International Symposium on Quality Electronic Design, pp. 275-283, March 2000.
• [4] A.T. Krishnan, S. Krishnan, and P. Nicollian, “Impact of Gate Area on Plasma Charging Damage: The “Reverse”
Antenna Effect,” International Electron Devices Meeting, pp. 20.6.1-20.6.4, December 2002.
• [5] J.F. Chen et al., “Reverse Antenna Effect Due to Process-Induced Quasi-Breakdown of Gate Oxide,” IEEE
International Reliability Workshop, pp. 94-97, October 1996.
• [6] Z. Wang, A. Scarpa, C. Salm, and F. Kuper. “Relation between Plasma Process-Induced Failure Fraction and
Antenna Ratio,” Proceeding of the International Symposium on Plasma Process-Induced Damage, pp. 16-19, May
2001.
• [7] W. Maly et al., “Design-Manufacturing Interface: Part II – Applications,” Proceedings of the Design, Automation, and
Test in Europe, pp. 557-562, February 1998.
• [8] R. Otten, P. Camposano, and P. Groeneveld, “Design Automation for Deepsubmicron: Present and Future,”
Proceedings of the Design, Automation, and Test in Europe, pp. 650-657, March 2002.
• [9] S. Krishnan, A. Amerasekera, S. Rangan, and S. Aur, “Antenna Device Reliability for ULSI Processing,” Proceedings
of the International Electron Devices Meeting, pp. 21.5.1-21.5.4, December 1998.
• [10] H.T. Heineken et al., “CAD at the Design-Manufacturing Interface,” Proceedings of the Design Automation
Conference, pp. 321-326, June 1997.
• [11] D.P. Verret, A. Krishnan, and S. Krishnan, “A New Look at the Antenna Effect,” IEEE Transactions on Electron
Devices, Vol. 49, No. 7, pp. 1274-1282, July 2002.
• [12] G.S. Hwang and K.P. Giapis, “On the Dependence of Plasma-Induced Charging Damage on Antenna Area,”
Proceedings of the International Symposium on Plasma-Induced Damage, pp. 21-23, May 1999.
• [13] K. Hashimoto, “New Phenomena of Charge Damage in Plasma Etching: Heavy Damage Only through Dense-Line
Antenna,” Japanese Journal of Applied Physics, Vol. 32, No. 12B, pp. 6109-6113, December 1993.
• [14] P. Simon, J.-M. Luchies, and W. Maly, “Antenna Ratio Definition for VLSI Circuits,” Proceedings of the International
Symposium on Plasma Process-Induced Damage, pp. 16-20, May 1999.

8/5/2004 29
 References (cont.)
• [15] Z. Chen and I. Koren, “Layer Reassignment for Antenna Effect Minimization in 3-Layer Channel Routing,”
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 77-85,
November 1996.
• [16] W. Maly, C. Ouyang, S. Ghosh, and S. Maturi, “Detection of an Antenna Effect in VLSI Designs,” Proceedings of
the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 86-94, November 1996.
• [17] M. Mardiguian, EMI troubleshooting techniques, McGraw-Hill Publishers, 1999.
• [18] K. Kano, Semiconductor Devices, Prentice-Hall, 1998.
• [19] http://www.mosis.org/Technical/Designrules/guidelines.html
• [20] IBM CMS8SFG Design Manual, 11/25/02.
• [21] TSMC 0.18um Design Manual, Document number TA-10A5-4001, pp. 67-68.
• [22] http://www.silvaco.com/applicactions/archive/2002/mar2002/mar02_a2/mar02_a2.html
• [23] J. Ferguon. “Design-for-Yield,” IEE Electronics Systems and Software, pp. 15-16, June/July 2003.
• [24] H.-C. Lin et al., “Characterization of Plasma Charging Damage in Ultrathin Gate Oxides,” IEEE International
Reliability Physics Symposium, pp. 312-317, April 1998.

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