2011 Sixth IEEE International Symposium on Electronic Design, Test and Application

Automatic Yield
Y Management Systtem for
Semicoonductor Production Teest
Huiyuan Cheng Melanie Po-Leen Ooi Ye Chow Kuang
School of Engineering School of Engineering School of Engineering
S
Monash University, Malaysia Monash University, Malaysia Monnash University, Malaysia
hche61@student.monash.edu melanie.ooi@monash.edu kuanng.ye.chow@monash.edu

Eric Sim Bryan Cheah Serge Demidenko

School of Engineering
Monash University, Malaysia
kjsim4@student.monash.edu
Centre of Technology
Global Yield Enhancement Team R
RMIT University, Vietnam
Freescale Semiconductor serge.demidenko@rmit.edu.vn
bryancheah@freescale.com

Abstract— Recurring defect cluster patterns on semiconductor

wafers can be linked to imperfectness/ffaults in specific
manufacturing processes or alternatively - to failure or
malfunctioning of production equipment (in n our research we
assume that defects associated with deficien ncies/errors in the
circuit design are not present). By identifyingg these patterns as
they occur, a fast and effective process moniitoring and control
mechanism can be achieved, shortening the tiime-to-yield period
and reducing the loss in revenue due to avooidable yield drop.
Identifying these patterns manually could be a too complex and
time consuming task. This research presents an automatic yield
management system to extract and identify deffect clusters as well
as perform yield analysis in a high-volume semmiconductor devise
manufacturing.
Keywords-semiconductor wafer technology, yield management,
defect clusters, yield analysis
I. INTRODUCTION
Modern semiconductor industry is facing a mounting
pressure to lower the cost of the produced integrated circuits
(IC) while further advancing their parameteers and increasing
functionality [1]. As a result it has become very essential for
the IC manufacturers to achieve a higgh manufacturing
throughput without compromising quality annd reliability of the
final products. Unfortunately, in majority of cases new devices
or products tend to have a low manufacturiing yield. Thus in
order to maintain the product’s profitability in a long run, it is
crucial that a steep yield ramp would bee achieved in the
shortest time possible [2]. High yield ramping can be gained
through the effective manufacturing processs monitoring and
good utilization of engineering resources.
One of the indicators of possible processp faults or
equipment degradation is an observed increease in the defect
population in the final product. For fabricatted semiconductor
wafers, this is normally manifested throough presence of
consistent and specific defect patterns. Figgure 1 shows six
commonly observed defect patterns on thhe semiconductor
wafers [3].
Figure 1. Defect cluster patterns: a) Bulls-Eye, b) Blob, c) Line, d) Edge,
e) Hat,, f) Ring
Each of these defect clusterr patterns can be loosely tied to
possible specific manufacturinng process or equipment issues.
For instance, the Bulls-eye deefect pattern can be caused by
contamination of a nozzle empployed to apply the photoresist
coating on the wafer surface.
By identifying such defect patterns
p as and when they occur,
a specific malfunctioning equiipment or faulty process can be
quickly pin-pointed and fixed. f However, the defect
identification, classification annd cause back-tracking analysis
can be complex and time consuuming. Therefore it is essential
to develop and engage automaation tools for as many routine
tasks as possible in the yield learning
l and yield management
area [4]. Some of the autoomation solutions have been
introduced in the industry in thhe recent decade. One example
is Atmel’s adoption of the KL LA-Tencor's Klarity system [5],
which reduced yield learning time from several months to a
few weeks.
This research proposes ann automatic yield management
system that performs wafer-levvel defect analysis through data
mining. It provides com mputer-aided detection and
recognition/classification of defect patterns on fabricated
wafers using raw manufacturring test data and performs an
automatic yield analysis for thee relevant wafer lot.

978-0-7695-4306-2/11 $26.00 © 2011 IEEE 260

254
DOI 10.1109/DELTA.2011.53
 II. SYSTEM ARCHITECTU
URE
The proposed system includes three main m components
(subsystems) as shown in Figure 2. These subsystems
s can be
used standalone if necessary, or to be employyed in conjunction
to correlate the manufacturing yield with defect
d cluster data
for further analysis.
Figure 2. System Architecture
A. Subsystem 1: SDC
This subsystem utilizes the Segmentatioon with Detection
and Cluster Extraction (SDC) algorithm described in [3].
Figure 3 shows the main stages of the algorithm. It performs
cluster segmentation using image processingg methods and uses
joint-count statistics to detect any non-ranndom failures (or
local defect patterns) on the wafer. Finnally, the cluster
extraction combines the segmentation and detection
d results to
obtain the final defect cluster data.
Figure 3. SDC System
Random failures manifest as a salt-and-pepper noise on the
wafer map - Figure 4(a). They may cause inaaccuracy in cluster
detection and classification. The SDC system extracts the
defect clusters while simultaneously remooving the random
failure patterns, which could distort the classsification process.
Figure 4(b) shows an example of the local deefect pattern wafer
map after application of SDC. The SD DC algorithm is
characterized by detection accuracy exceedinng 90% [3].
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261
Figure 4. Application of SDC system m. The original wafer map with random
failures (a) and afterr SDC application (b)
B. Subsystem 2: Classificationn
Classification can be achieeved through various methods.
One of them is associated wiith the use of Artificial Neural
Networks. This method has beeen shown to be accurate for this
classification task [6]. Unfortunnately it generates classification
rules that are not transparent tot the user. This is undesirable
for implementation in the semiconductor device
manufacturing, particularly in production
p of integrated circuits
aimed for mission critical appplications as it would fail any
quality audits conducted by end-client
e companies or safety
enforcement/standardization boodies.
The proposed system emplloys decision tree classification
method [7]. Decision trees are widely used in decision making
based on data mining and macchine learning. Their generated
rules are fully transparent to the user allowing for a
monitoring and control overr classification. The gradient
boosting algorithm can be usedd with decision trees to improve
the classification accuracy significantly [8]. Previous
investigation showed that thhe Alternating Decision Tree
(ADTree) was the most prom mising classifier for fabricated
semiconductor wafers [9].
Figure 5 shows the classification system. Prior to any
actual classification, the decisiion tree has to be built based on
a training set. This comes froom a defect pattern simulator,
which produces a training sett of all possible orientation of
defect clusters and their respecctive defect type. The rules are
generated based on the featurees from the training set, which
are extracted using the Handppicked (HP) Feature Extractor
and Rotational Moment Invariaant (RMI) Feature Extractor.
Figure 5 The Claassification System
RMI has been used as a classsical tool for object recognition
in the past 40 years [10]. It waas shown in [9] that RMI could
be successfully employed to distinguish betweenb different III. PROTOTYPEE IMPLEMENTATION
defect patterns. The features generatedd by RMI are
complemented by HP extracted ones. Handdpicked features in The decision to transfer a new semiconductor product from
[9] were geometrical descriptors of the defectd clusters as an introductory stage to the high volume manufacturing is
understood by a human classifier. Examples of these are mean dependent on various importannt factors including achievement
radius and the major axis length of the extraccted cluster. of the required yield levels. Huge loss of revenue can be
incurred if yield ramping is peerformed at an insufficient pace.
The efficiency of ADTree used in the claassification system In fact in today’s semiconducctor industry an initial yield (at
has been further expanded by employing dataa representation in product introduction) and the yield ramp rate have replaced
the complex number domain [11]. By representing the the final yield (at full capacity production) as key drivers of IC
handpicked features using complex numbeers, two different profitability. In many cases yield
y ramp rate can actually be
features can be compared at a time. This alllows the classifier more important to profit margin m than the high-volume
to consider the correlation between the attributes when production yield.
generating the classification rules.
The majority of yield improvement techniques employed
in the industry rely upon availaability of high volume of defect
With the classification rules generated,, the local defect
data. However in some cases these
t data may not be used in a
pattern wafer maps from the SDC subsystem m can be classified.
full extend or could even be b somewhat redundant. Thus
Note that certain defect cluster patterns coould present some
improvement in the use of thhe existing test data and early
ambiguity in their classification. For instannce, a line defect
simulation in the production ramp
r are required to obtain an
pattern located close to the wafer edge can allso be classified as
objective and comprehensive evaluation
e of the existing yield
a hat defect pattern - see Figure 1 c) and Figgure 1 e). Thus for
and its trend. The proposedd automatic yield management
each defect class, the classification results arre presented along
system is addressing this need.
with their confidence score levels. Table I shows
s an example
of classification stored as a comma-separaated-values (CSV) Three different mass-produuction devices (named as just
file. Lot ID AAA shows an ambiguous case c whereby two Device A, B and C for the sake of confidentiality) were
possible classes are reported for the sam me defect cluster identified for experimental triaal of the proposed system over a
pattern. The class with a higher confidence level is presented period of 3 months. The main characteristics
c of the devices are
as the first possible one. Final decision is done by the yield shown below in Table II.
engineer based on the scores provided. TABLE II. CHARACTERISTICS OFF THE DEVICES USED IN THE RESEARCH
TABLE I. EXAMPLE OF CLASSIFICATION RESULTSS STORED IN CSV FILE
Device Feature Size (nm) Die/Wafer
D Average Yield
Lot ID Wafer ID Possible Confidence Possible Confidence A 130 402 60-80%
Class 1 for Class 1 C
Class 2 for Class 2 B 250 984 Above 80%
AAA XXX Edge 50% Line 30% C 90 384 Below 60%
BBB YYY Blob 80% - -
When implementing the syystem on Device B, the analysis
shows a stable high yield (Figure
( 7) corresponding to a
C. Subsystem 3: Yield Analysis
matured production process, where
w major systematic causes of
defects have been already rectified.
r However, it can be
The yield analysis system correlates the yield of a
observed that there are periodic yield drops (see shaded
particular wafer lot to its classification resultts (Figure 6).
regions I, II, III and IV) parrticularly when there is a high
occurrence of the Blob defect cluster
c patterns (in regions I, III
and IV). Because the yield droop here is periodic in nature, it
can be suggested that there may be process or equipment
degradation causing it. Thus it would be strongly desirable for
the manufacturing engineers to t look at the condition of the
equipment and parameters of thet processes and to revise their
maintenance and process moonitoring strategy if required.
Conversely although the edge defect clusters are consistently
Figure 6. Yield Analysis Tool
recurring throughout the obserrvation period, they have a very
little correlation with the yielld. Solving these defect issues
The relationship between defect cluster typees and wafer yield would have a negligible effect on the yield.
is presented in graphical form for easy interppretation. Figure 7 Figure 8 shows the yield analysis
a results on Device A. It
shows the results of the yield analysis for onee of the real-world can be seen that the manuufacturing yield fell down by
mass-produced semiconductor devices (nam med here as Device approximately 10% over a signnificant period of time (refer to
B due to confidentiality). There is a noticeaable yield drop in the shaded region). This waas caused by the considerable
the shaded region I where a high percentagee of blob and edge increase in the number of the Line
L defect cluster patterns.
defect patterns were detected.

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262
 Device B Lot Level Yield Analysis
I II
Yield
Lot ID
Figure 7. Results of implementation of the automatic yield management system on Device B
Apparently in some wafer lots practically all the produced
wafers had Line defect clusters. The Line defect cluster
patterns are typically caused by incorrect mechanical handling
of the wafers. This can be resolved through the machine
recalibration or replacement. In this particular case it can be
clearly seen that if the proposed automatic yield management
system would be incorporated at an earlier stage, the problem
could have been detected much earlier (after all, the yield
analysis and evaluation can be performed in real time).
Figure 9 shows that Device C has consistently low yield
compared to Devices A and B. Thus, it is a prime target for
yield improvement. During the more than-3 month period of
observation and data analysis, the reported yield management
tool identified an unusually high occurrence of Edge defect
cluster patterns for Device C. In addition, there was also a
moderately high number of the Blob defect cluster patterns
found. It was recommended that the engineers closely examine
the processes and equipment related to the wafer edge
exclusion (WEE) region, such as speed of revolution during
application of the photoresist layer, etching process (a
common cause of blob defect cluster patterns), etc.
Note that Figure 9 was produced based on the wafer probe
test results only. Thus the dies at the edges could have
Device A Lot Level Yield Analysis
Yield
Lot ID
Figure 8. Results of implementation of the automatic yield management system on Device A
Mean Yield
Lot Yield
Blob
III IV Edge
reliability issues during the earlier stages, e.g., burn-in. The
analysis could be further extended to include the final test,
burn-in, customer returns, etc., data to decide if the WEE
region should be extended.
IV. CONCLUSION
This paper describes a proposed automatic yield
management system. The system automates the repetitive
tasks required in yield analysis such as defect cluster
detection, recognition and correlation to manufacturing yield.
It produces a highly consistent analysis in real-time, allowing
for fast and high quality process monitoring and control. The
effectiveness of the presented system has been confirmed
during the 3-month experimental trial with application to the
high volume manufacturing program for three different IC
types. The experiments showed that the propose system could
be very efficient in identifying and resolving a wide spectrum
of defect classification - and yield-related issues.
ACKNOWLEDGMENT
The authors would like to express their gratitude to Freescale
Semiconductor for the valuable technical and specialist
support provided by their teams in Malaysia and US.
Mean Yield
Lot Yield
Line
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 Device C Lot Level Yield Analysis

Mean Yield
Lot Yield
Blob
Edge
Yield

Lot ID
Figure 9. Results of implementation of the automatic yield management system on Device C

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