DIGITAL ELECTRONICS-II

Diploma, (Hr.)
PAPER 4

Time : 3 Hrs M.M. : 100

SECTION-A
Note : Attempt any ten questions. (102=20)

Q.1(a) Name the three output states of tristate logic.

Ans. The three output states are :
1. Low state (State 0)
2. High state (State 1)
3. High Impedance state.
Q.1(b) Name any 2 types of Analog to Digital converter.
Ans.1. Single slope A/D converter.
2. Simultaneous A/D converter.
3. Successive Approximation A/D converter.
Q.1(c) What do you mean by figure of merit.
Ans. Figure of Merit is relation between the power dissipation and speed of
operation (propagation delay) of a gate. Figure of Merit = Propagation Delay 
Power Dissipation.
Q.1(d) What do you mean by CAM ?
Ans. CAM stands for content Addressable Memory. In a CAM, the memory can
be accessed by data content. It is also called Associative Memory.
Q.1(e) What is the difference between PLA and PAL ?
Ans. In PLA-both AND and OR circuits are programmable whereas in PAL only
AND array is programmable whereas OR array is fixed.
Q.1(f) Write the rules for Binary Multiplication.
Ans. 00 =0
01 =0
10 =0
1  1 = 1.

62
Digital Electronics-II 63

Q.1(g) Draw the block diagram for one stage of ALU.

Ans.

Fig. : One Stage of ALU

Q.1(h) Name the logic family with the minimum power dissipation per
gate ?
Ans. CMOS Family (Complementary metal oxide semiconductor logic) has
minimum power dissipation pergate.
Q.1(i) Write any 2advantages of TTL family.
Ans.1. High Speed.
2. Low Power Consumption.
3. Good Drive capabilities.
Q.1. (j) What is the modulus of a decade counter ?
Ans. Decade counter counts form 0 to 9,  10 different states, hence named as
MOD-10.
Q.1(k) What do you mean by power dissipation ?
Ans. This is the amount of power dissipated in an IC. It is determined by
current ICC that it draws from VCC supply and is given by VCC  ICC. It is solidified in
milliwatts.
Q.1(l) What are the applications of D/A converter.
Ans.1. For testing analog circuits.
2. Signal Reconstruction.
3. Control of physical variable like temperature of oven/furnace, speed of
motor.
4. Graphic display on CRT.
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SECTION-B

Note : Attempt any five questions. (56=30)

Q.2. Obtain a 2048  8 memory by using 256  8 memory chips.
Ans. The required word capacity = 2048
The available word capacity = 256
2048
So, number of chips required = = 8 chips.
256
So, 8 chips are combined to obtain a 2048  8 memory. In this way, we require a
3 line to 8 line decoder for selecting one out of the eight chips at a time. The
connections of the 256  8 memory chips are shown below :

Q.3. Explain the types of sequential circuits ?

Ans. The sequential circuits are classified into two types.
1. Synchronous sequential circuit
2. Asynchronous sequential circuit
1. Synchronous sequential circuit : The synchronous sequential circuits
use hardware devices like flip flop for memory & are cycled by a special single
synchronizing input waveform called system clock. This clock is the command signal
which causes the memory element to read & store the code at its inputs.
In synchronous sequential circuits, we do not depend upon unknown delays in
the feedback path to give the memory function. The transfer of information from
Digital Electronics-II 65

outputs to memory is done only at preassigned discrete instant of time in a

systematic manner. Synchronization of the clock pulses are obtained by deriving
them from a common clock signal. The clock pulses in a synchronous sequential
circuit are used in such a way that all memory elements are affected only at the
arrival of the clock pulse. The main advantage of using synchronous sequential
circuits are that these circuits remove the race condition which is the major
drawback of a asynchronous sequential circuits. The design of synchronous
sequential circuits are simple & reliability of operation very high.
2. Asynchronous Sequential Circuits : The asynchronous sequential
circuits are the combinational logic circuits with direct feedback & are cycled by
transition of each input & strictly provide propagation delay for memory. IN
asynchronous sequential circuits, the inputs & outputs do not change at pre-
assigned times because the inherent delays are not controlled. This leads to race
condition which is found in asynchronous sequential circuits. Moreover, the design of
these sequential circuits are tedious & the reliability of these circuits are poor.
Q.4. Explain R/2R Ladder D/A converter ?
Ans. R/2R LADDER D/A CONVERTOR : To overcome the drawback of
binary weighted D/A convertor of requirement of number of resistor, a ladder
network are employed Ladder network uses only two resistor R and 2R for any bit
data conversion. A four bit R/2R ladder digital to analog convertor shown in figure.

As this circuit uses only two resistor R and 2R and connected in such a manner
that it form a ladder that is why this type of circuit called R/2R ladder D/A
convertor.
The working of the circuit is explain by giving High signal to one of the data
Input and other data input are at Low level.
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Let D0 = Low, D1 = Low, D2 = Low and D3 = High

By applying above signal the circuit shown in figure become as figure.

Fig. : For Data Input 1000

Equivalent resistance at terminal A as

2R||2R 

RAeq =   2R  R  R = 2 R 2R   R  2R  R
2R   

= 2 R 2R   R  2R
Now the circuit shown in figure a reduces as shown in figure.

Now the output voltage due to +5V signal

 0  5V  5V
=  Rf   2R =  5V
 2R  2R
Hence for signal 1000 the analog output voltage is –5V.
Now let D0 = Low, D1 = Low, D2 = High and D3 = Low
Digital Electronics-II 67

i.e. Data input to network is 0100. By applying these data signal the circuit
shown in fig 8 become as shown in figure.

The equivalent resistance at terminal A of figure is

 2 R 2R   R 2R 
RAeq =   R

RAeq = 2 R 2R   R
RAeq= R + R = 2R
Now the circuit shown in figure reduces as shown in figure.

To find out current flowing through feed back resistance Rf the circuit up to B
of figure is simplified using Thevenins theorem as shown in figure.
Vth = RAeq  I
5
I =
4R
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5
Vth =  2R  2.5V
4R
Rth = 2 R 2R  R
By applying thevenin equivalent to figure the circuit become as shown in
figure.

From the circuit as shown in figure, we can calculate output voltage easily. The
current flowing through the feedback resistance Rf is
0  2.5 2.5
I =  A
2R 2R
and output voltage of the circuit is
25
VOutput =  R f = 2.5V As Rf = 2R
2R
Hence for signal 0100 the analog voltage is –2.5V as the output voltage become
half when the input data signal reduces to next lower significance bit similarly for
data input 0010. The output voltage is = – 1.25 and for data input 0001 the output
voltage is = – 0.625V
Q.5. Explain arithmetic unit of ALU ?
Ans. One of an arithmetic circuit that gives the operations shown above is
shown in Fig. The full-adder circuit represents one state of the parallel-adder. The
two selection lines S1 and S0 control the data path between the B terminal and one
input of the full-adder circuit. When S1S0 = 00, the controlled input of the full-adder
is always 0. When S1S0 = 01, the input receives the value of Bp When S1S0 = 10, the
Digital Electronics-II 69

input receives the complement value of B1. With S1S0 = 11, the input is always equal
to 1. These conditions can be verified by driving the truth table of the selection logic.

Fig. : One Stage of Arithmetic Circuit

Table for Arithmetic Circuit
Function Select
Output Remarks
Si So C1
0 0 0 F=A (e) Transfer A
0 0 1 F=A+1 (f) Increment A
0 1 0 F=A+B (a) Addition
0 1 1 F=A+B+1 (b) Addition with carry
1 0 0 F=A+B (c) A plus 1's complement of B
1 0 1 F=A+B+1 (d) Subtraction
1 1 0 F=A–1 (g) Decrement A
1 1 1 F=A (h) Transfer A
The arithmetic circuit can be partitioned into stages, one for each pair of bits of
the input operands. For operands with n bits, the arithmetic circuit consist of n
identical stages. Figure. shows the block diagram of an arithmetic circuit partitioned
into n stages. Each stage is identical to the circuit shown in Fig.

Fig. : Arithmetic Circuit Consists of n different stages

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Q.6. Explain interfacing of TTL to CMOS.

Ans. Interfacing TTL to CMOS : While TTL gate is driving CMOS, the
interfacing is not simple as CMOS to TTL. For interfacing CMOS with TTL following
condition must be satisfied.
VOH (TTL)  VIH (CMOS)
VOL (TTL)  VIL (CMOS)
IOH (TTL)  IIH (CMO)
IOL (TTl)  IIL (CMOS)
The condition VOH (TTL) must be equal to or greater than VIH (CMOS) but by
considering the table of parameter this condition is not satisfied because VOH (TTL)
= 2.4 whereas VIH (CMOS) is 3.5. Thus the output voltage of TTL is not sufficient to
drive CMOS in the high state. On the low state the voltage are compatible.
For properly interfacing a TTL to CMOS IC using the same + 5 V supply, a pull
up resistor is required. This resistor is used to ensure that logic high is of sufficient
voltage amplitude to operate CMOS IC properly. This is because logic level voltage is
greater for CMOS than for TTL logic high. The figure show the interfacing a TTL
input with CMOS using pull up resistor.

Q.7. Explain FPGA in detail ?

Ans. When we require a large number of inputs & outputs for a circuit, an
alternative architectures have been developed which is known as field
programmable gate array. So, FPGA is a device which contains a large number of
equivalent gates on a single IC chip. The logic densities of FPGAs are very high than
the PLDs. In a single FPGA device, there are ten thousand to a few hundred of
thousand gates are fabricated on a chip. In FPGA device, there are logic blocks for
implementation of digital circuits lent they do not use the AND-OR arrays for the
operation.
Digital Electronics-II 71

The FPGAs are developed in 1984 by the Xilinx Corporation of America. These
FPGA devices are composed of a number of configurable logic blocks (CLBs). The
diagram of a FPGA device is shown above.
The above diagram shows a FPGA device which contains 64 CLBs arranged in a
8  8 matrix. There are four inputs (A, B, C, D) are applied to each CLB which can
implement a logic function up to four variables. So, each CLB consists of four inputs
& a clock input & two outputs P & Q. The above diagram also contains a 58 number
of input/output blocks. Each IOB consists of a single input & three state output.
These IOBs are configured with flip flops & can be accessed by the CLB for non
input/output functions. The input/output blocks provides us the interface between
the internal logic circuit & the external pins of the device. So, in a summarized
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manner, we can say that FPGA is a programmable logic device which contains a very
large number of equivalent gates on a single IC chip.

SECTION-C
Note : Attempt all questions. (510=50)
Q.8. Describe the IC for ALU in detail.
Ans. I.C. for ALU : There are several complex ICs available in the TTL and
CMOS families that can perform one or more types of operations.
IC 74181 is a basic ALU in TM 7400 series. It is capable of adding, subtracting,
incrementing, decrementing and performing shift operations and logical operations.
The ICs 74LS381 and 74HC381 are called arithmetic logic Units/function
generators. They can perform eight different binary arithmetic and logic operations
on two 4-bit Inputs.
The block diagram of IC 74181 is shown in figure. which is used to perform
different arithmetic and logical operations.

Fig. : Block Diagram of IC 74181

Digital Electronics-II 73

Fig.
Circuit Diagram Of 74181 : The logical diagram of I.C. 74181 is shown in
figure. This I.C belongs TTL series family operated by + 5 supply. This I.C. is
capable to perform 16 different operation, depending upon the select line S0 , S1 , S2 ,
S3. The perform Arithmetic or logical function depend upon the mode control (M). If
M is at high level then performs logic operation and if M is at low level then it
perform arithmetic operation. This I.C. accept 4 bit two data bit namely A3 , A2 , A1 ,
A0 and B3 B2 B1 B and give 4 bit data output F3 , F2, F1 , F0. There is another two
terminal namedC1n (carrey input) and Cn + 4 (carry output) used by cascading ALU
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I.C. Carrey input (Cin) also effect the operation of Arithmetic and logic function.
Functional table of ALU with operation of carrey input shown in table as.
Table 1 : Function table at I.C. 74181
Active High Data
M=H
M=L
Select Input Logic
Arithmetic Functions
Functions
S3 S2 S1 S0 Cn = H (no carry) Cn = L (with carry)
L L L L F= A F=A F = A Plus 1
L L L H F = AB F=A+B F = (A + B) Plus 1
L L H L F = AB F=A+ B F =  A  B Plus 1

L L H H F=0 F = Minus 1 F = zero

(2's complement)
L H L L F = AB F = A Plus A B F = A Plus A B Plus 1
L H L H F= B F = (A + B) Plus A B F = (A + B) Plus A B Plus 1
L H H L F=AB F = A Minus B Minus 1 F = A Minus B
L H H H F = AB F = A B Minus 1 F = AB
H L L L F= A +B F = A Plus AB F = A Plus AB Plus 1
H L L H F = AB F = A Plus B F = A Plus B Plus 1

H L H L F=B F =  A  B PLus AB F =  A  B PLus AB Plus 1

H L H H F = AB F = AB Minus 1 F = AB
H H L L F=1 F = A Plus A F = A Plus A Plus 1
H H L H F=A+ B F = (A + B) Plus A F = (A + B) Plus A Plus 1
H H H L F=A+B F =  A  B Plus A F =  A  B Plus A Plus 1

H H H H F=A F = A Minus 1 F=A

Q.9. Design a mod 6 counter by using J-K flip flops.
Ans. First of all find the number of flip flops required to design the mod-6
counter by using the relation.
n  2n
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n
6 2
So, no. of required flip flops = 3.
State diagram of the mod-6 counter is given by

Now make the excitation table by using the state diagram.

A B C JA KA JB KB JC KC

0 0 0 0 1 0 0 1 0
0 0 1 0 0 1 0 0 1
0 1 0 0 0 0 0 1 0
0 1 1 1 0 0 1 0 1
1 0 0 0 0 0 0 1 0
1 0 1 0 0 1 0 0 1

Now make the K-map & reduce the expression.

AB
C 00 01 11 10
0 0 0 0 0
0 2 6 4
1 0 1 0 0
1 3 7 5
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J A = BC

AB
C 00 01 11 10
0 1 0 0 0
0 2 06 4

1 0 0 0 0
1 3 7 5

KA  A .

AB
C 00 01 11 10
0 0 0 0 0

1 1 0 0 1

JB  C

AB 00 01 11 10
C
0 0 0 0 0

1 0 1 0 0

KB  C

AB 00 01 11 10
C
0 1 1 0 1

1 0 0 0 0

JC  1
Digital Electronics-II 77

AB 00 01 11 10
C
0 0 0 0 0

1 1 1 0 1

KC 1

Now draw the circuit as follows :–

Q.10. Write a note on :

1. CCD
2. FPGA
Ans. 1. Charge Coupled device (CCD) memory : The CCD memories are
used for storing digital informations. These memories are invented by the Bell
Telephone Laboratories of U.S.A. The CCD memories consist of an array of MOS
capacitors operating as a dynamic shift register. The CCD memories operation
involve the following steps :–
1. In the first step, the digital information is converted into charge.
2. Then the charge is transferred from one stage to other stage of a dynamic
shift register in a sequential manner.
3. The last step consists of the conversion of the charge into digital signal.
During the charge transfer process, a small amount of charge is lost at each
step. So, the refreshing is required so that the charge is re-circulated around the
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shift register. The CCD memories are simple & low cost devices. The CCD memories
are used where the serially accessed memory is required.
The figure shows a block diagram of ACCD memory.

This is a 16384  1 bit serial memory which is organised as a sixty four

independent recirculating shift registers. Each shift register is of 256 bits. We can
access any one of the 64 registers by applying the appropriate six bit code at the
address input buffer. The data in the shift registers are simultaneously shifted by
using the four phase clock inputs from 0 to 4. After the shift operation, each of the
64 registers can be selected for an input/output operation by applying the
appropriate six bit code at the address input buffer.
2. FPGA : When we require a large number of inputs & outputs for a circuit,
an alternative architectures have been developed which is known as field
programmable gate array. So, FPGA is a device which contains a large number of
equivalent gates on a single IC chip. The logic densities of FPGAs are very high than
the PLDs. In a single FPGA device, there are ten thousand to a few hundred of
thousand gates are fabricated on a chip. In FPGA device, there are logic blocks for
implementation of digital circuits lent they do not use the AND-OR arrays for the
operation.
Digital Electronics-II 79

The FPGAs are developed in 1984 by the Xilinx Corporation of America. These
FPGA devices are composed of a number of configurable logic blocks (CLBs). The
diagram of a FPGA device is shown above.
The above diagram shows a FPGA device which contains 64 CLBs arranged in a
8  8 matrix. There are four inputs (A, B, C, D) are applied to each CLB which can
implement a logic function up to four variables. So, each CLB consists of four inputs
& a clock input & two outputs P & Q. The above diagram also contains a 58 number
of input/output blocks. Each IOB consists of a single input & three state output.
These IOBs are configured with flip flops & can be accessed by the CLB for non
input/output functions. The input/output blocks provides us the interface between
the internal logic circuit & the external pins of the device. So, in a summarized
manner, we can say that FPGA is a programmable logic device which contains a very
large number of equivalent gates on a single IC chip.
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Q.11. Explain Stair step Ramp Type Analog to digital convertor.

Ans. This convertor consists counter, comparator, digital to analog convertor,
AND gate with Lach at which we get output. The logic circuit diagrame of stair step
ramp type A/D convertor shown in figure.

Fig. : Stair Step Ramp Type A/D Convertor

<

In this circuit comparator compare analog input signal which is to be converted

in to digital signal and the output of digital to analog convertor. And the input of D/A
converter is derived by the counter. The number of clocks counted by the counter
depends upon the output of comparator.
Working : At starting counter is assume to be at Reset State i.e. the input to
D/A converter is zero. The voltage which is to be converted in to digital is applied at
the non inverting terminal of the comparator. And the output of D/A converter is
given to the inverting terminal of the comparator. At this time comparator compare
the two voltage produce High at its output. This high enable the gate N1 so the train
of clock is applied at the clock input of the counter and it tends to increases its
binary sequence by one step on each successive clock. As binary sequence of counter
is increase so the output D/A converter is also increases step by step on every clock
pulse. Hence stair step type voltage is produced at the output of D/A convertor. Stair
step voltage is shown in fig.
Digital Electronics-II 81

Fig. : Stair Step Voltage

Now this stair step voltage is compare with the analog input by comparator.
The comparator given low state output when stair step reference voltage become
equal to the analog input voltage. This low state signal disable the gate N1 and the
clock input to the counter is stopped at the same time control logic generate the
signal to the counter and Latch. Due to this the output of counter appeared at the
output of latch and counter come to is reset position. Now the circuit is ready for
next conversion. The output of latch is equivalent to the analog input.
In stair step reference voltage, convertor when a sample of conversion is
completed the stair step reference voltage come to its Reset position because at this
time counter output is zero. On every completion of conversion the stair step
reference voltage become zero. So the conversion time of this convertor is high and
conversion time increase with increases the analog input.
Q.12. Explain TTL inverter in detail.
Ans. TTL Inverter : The logic circuit diagram of Inverter gate using TTL is
shown in figure.

Fig. : TTL Inverter Gate

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In basic TTL inverter circuit the transistor T1 is the input coupling capacitor T2
is called phase shifter and transistor T3 and T4 make the output circuit. The
arrangement of transistor T3 and T4 make the totem pole configuration.
The totem pole configuration is same as Push Pull Output ; however, it
is the terminology commonly used when referring to a TTL device. The
major difference between it and Push Pull arrangement is the amount of
current that it can sink or source. The totem pole output is going to
sink/source less current than a Push Pull output. The other major
difference is the output voltage between the two. The totem pole have a 5V
dc signal only whereas Push Pull will follow the input voltage.
Operation of TTL Inverter : When the input is high, the base emitter
junction of transistor T1 is reversed biased and base collector junction is forward
biased. This allow the flow of current from R1 to base of transistor T2, make it in to
saturation. Due to the conduction of transistor T2 the transistor T4 come in to cut off
state and transistor T3 come in to saturation state. As the output is taken at the
collector of T3 so the output of the circuit is nearly to saturation voltage i.e. at
ground level. It means that for high input the output is low.
Similarly for low input signal, the base emitter junction of transistor T1 is in
forward bias whereas collector base junction is in reverse bias state hence current
will flow from resistance R1 to input terminal no current will flow to the base of
transistor T2, So it is in off state. Hence collector at transistor Q2 is at high state and
emitter at low state. This will turned ON the transistor T4 and turned off transistor
T3. Due to the off state of T3 all the supply voltage appeared at the output i.e.
output become high.
Hence the operation of inverter circuit is verified also truth table is
implemented as :
Input Output
Low High
High Low