2010 28th IEEE VLSI Test Symposium
An ADC/DAC Loopback Testing Methodology by DAC Output Offsetting and
Scaling
Xuan-Lun Huang and Jiun-Lang Huang
Graduate Institute of Electronics Engineering
Department of Electrical Engineering
National Taiwan University, Taipei 10617, Taiwan
Abstract—This paper presents a loopback methodology for
static linearity testing of an ADC/DAC pair; the key idea is
to raise the effective ADC and DAC resolution by scaling the
DAC output. First, during ADC testing, we scale down the
DAC output to achieve the needed test stimulus resolution and
adjust the DAC output offset to cover the ADC full-scale range.
Then, for DAC testing, we raise the effective ADC resolution by
scaling up the DAC output. Both simulation and measurement
results are presented to validate the proposed technique.
Keywords-mixed-signal testing, loopback testing, design-for-
test, ADC/DAC testing, segmented current-steering DAC.
I. I NTRODUCTION
Analog-to-digital and digital-to-analog data converters
(ADCs and DACs) are essential building blocks in modern
communication and multimedia devices. To catch up with
the rapid data volume growth, the development of high-speed
and high-resolution data conversion techniques has never
stopped. While meeting the data bandwidth requirement,
these high-end converters also pose serious challenges to
manufacturing testing because data converter testing mostly
consists of specification-based functional testing.
Since mixed-signal System-on-Chips (SoCs) often contain
both ADC and DAC, the loopback testing methodology that
directs the DAC output to the ADC input (through some ana-
log signal processing path) so that they can test each other
becomes a promising solution to ATE (automatic test equip-
ment) cost reduction. While attractive, the loopback testing
methodology is limited by the achievable test resolution and
the potential fault masking problem. Over the years, several
techniques have been developed to address these issues.
In [1], the authors presented a loopback testing scheme that
utilizes spectral predictors and a simple analog filter on an
external load board to estimate the dynamic performance of
data converters. Based on [1], Park et al. developed a parallel
loopback testing approach in [2]. These methods require
intensive computation to derive the dynamic performance
parameters. For static linearity testing, [3] proposed to first
estimate the ADC linearity based on the noise distribution.
Then, the characterized ADC is employed to test the DAC.
This work was partially supported by the National Science Council of
Taiwan, R.O.C., under Grant No. NSC 98-2220-E-002-006-.
978-1-4244-6650-4/10/$26.00 ©2010 IEEE
[4] proposed another noise-based loopback testing scheme.
It characterizes the DAC performance with the spectral
prediction technique [1], utilizes a digital equalizer to com-
pensate for the DAC nonlinearity, and measures the ADC
performance by the traditional histogram method. To ensure
test accuracy, these noise-based approaches demand a large
number of samples; this elongates the test time.
In this paper, we propose a static ADC/DAC loopback
testing methodology for cases that utilize the segmented
current-steering DAC (SCS DAC). The key idea is to raise
the effective ADC and DAC resolution by properly scaling
the current-steering DAC output. During ADC testing, the
SCS DAC output is scaled down and offset by a set of
DC values so as to produce the ADC histogram testing
stimulus. As for DAC testing, the effective ADC resolution
is improved by scaling up the DAC output. Then, the ADC is
utilized to test one current source in the SCS DAC at a time.
From the results, the DAC I/O (input/output) transfer curve
can be constructed assuming that the current summation is
ideal.
The contributions and advantages of the proposed loop-
back testing methodology are as follows.
1) We propose to achieve the needed test resolution for
static ADC and DAC testing, including DNL (differ-
ential non-linearity) and INL (integral non-linearity),
by simply scaling the DAC output. For SCS DAC, this
can be easily realized by adjusting the load resistance
value.
2) The proposed technique is robust. The scaling factors
and the set of offset voltages need not be very accurate.
Both simulation and measurements on off-the-shelf
ADC/DAC show that the proposed technique achieves
almost identical results to the conventional method. The
limitation is that the DAC must be of the segmented
current-steering architecture.
The rest of this paper is organized as follows. In Sec-
tion II, we briefly introduce the basic structure and operation
principle of the SCS DAC. In Section III, we illustrate the
proposed technique in detail. Simulation and experimental
results are given in Section IV and Section V respectively,
and we conclude this paper in Section VI.
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II. S EGMENTED C URRENT-S TEERING DAC
  
The segmented current-steering (SCS) DAC is very pop-
ular for high-performance applications. Internally, an N -
bit SCS DAC is divided into two segments: the unary-
weighted segment for the NM SB more significant bits and
the binary-weighted segment for the NLSB less significant
bits. (N = NM SB + NLSB .) The SCS DAC architecture
combines the advantages of the unary and binary-weighted
architecture—the former relieves the output glitch problem;
the latter reduces the circuit size.
Take the 6-bit SCS DAC in Fig. 1 for example. It has
NM SB = 2 and NLSB = 4; thus, it uses 2NM SB − 1 =
3 unary-weighted (I6 , I5 , and I4 ) and 4 binary-weighted
(I3 , I2 , I1 , and I0 ) current sources that are related by
 N
2 LSB · I0 if i > 3
Ii =
2i · I0 otherwise
While one can use D3 to D0 to directly control the binary-
weighted current sources I3 to I0 , a binary-to-thermometer
decoder is needed to generate the control signals to the
unary-weighted current sources (I6 , I5 , and I4 ) from D4
and D3 . The total output current (IDAC ) is directed
to the load resister (RL ) to produce the output voltage
(VDAC = IDAC · RL ).
It is worth noting that one can control the SCS DAC’s
full scale range (FSR) by adjusting RL ; this forms the basis
of the proposed ADC/DAC loopback testing technique.
III. T HE P ROPOSED ADC/DAC L OOPBACK T ESTING
T ECHNIQUE
The proposed technique takes advantage of the fact that
one can adjust the SCS DAC’s load resistance to change
its full scale range (FSR). When testing ADC, we use the
SCS DAC to generate the ramp stimulus and derive the
ADC non-linearity via the linear histogram approach. The
proposed technique achieves the required ramp resolution by
scaling down the DAC FSR; this raises the effective DAC
resolution because there will be more DAC output voltages
that fall inside each ADC code step. To compensate for the
reduced DAC FSR, we add a set of offset voltages to the
DAC generated ramps so as to cover the ADC FSR. As for
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Figure 3. The gain control block.
DAC testing, we use the ADC to test one current source
at a time by measuring the produced output voltage. Note
that this requires modification to the binary-to-thermometer
decoder. To achieve the required measurement resolution,
the proposed technique scales up the DAC output.
(1)
In the following, we will describe the hardware that sup-
ports the proposed loopback methodology and the loopback
testing flow. For ease of illustration, we make the following
assumptions.
• The ADC and DAC have the same FSR.
• The ADC and DAC have the same number of bits.
Note that, in general, one can apply the proposed technique
to other cases easily.
A. The loopback testing architecture
Fig. 2 depicts the proposed loopback testing architecture.
The DAC under test is a current-output SCS DAC; it has a
test enable signal (T E) which allows turning on each current
source individually during DAC testing. The ADC under
test, on the other hand, can be of any architecture and needs
no modification.
The loopback path consists of the “gain control” and
“offset control” blocks. The gain control block is a simple
resistor network as shown in Fig. 3 where RDAC > RL >
RADC ; it generates scaled DAC outputs. During normal
operation, φ1 is closed; this directs the DAC output current
IDAC to the normal load resistor RL and produces output
voltage VDAC = IDAC · RL . During ADC testing, φ2 is
closed and RADC is used to scale down VDAC ; during DAC
testing, φ3 is closed and RDAC is used to scale up VDAC .
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the offset voltages are properly selected so that adjacent
Figure 5. Covering ADC FSR with multiple segments.
The offset control block (Fig. 4) adds DC offset VOS to
the DAC output. Using a set of properly selected DC offset
values, this allows the down-scaled DAC outputs to cover
the ADC’s FSR. As shown in Fig. 5, without DC offset, the
DAC generated ramp, SEG1 , only covers a small portion
of the ADC FSR. By using multiple ramps with different
offset voltages, the ADC FSR can be covered. Note that
these DC offset voltages do not have to be very accurate as
long as the ADC FSR is fully covered and there is sufficient
overlap between adjacent segments to compensate for noise
and offset voltage deviations. In Fig. 4, the offset voltage is
from the DAC and stored in the sample-and-hold (S/H) unit.
In practice, one may use an external DC source if readily
available.
B. ADC testing
Fig. 6 depicts the proposed ADC testing flow. First, the
gain control block (Fig. 3) selects RADC which is α times
smaller than RL ; this scales down the DAC output by α.
Then, the flow enters the partial histogram collection loop.
In the i-th iteration, the offset voltage VOS i is applied to
the offset control block. Then, we sweep the DAC input
code and collect the corresponding ADC code hits, i.e., the
number of times each code appears. Note that the DAC
output only covers the range from VOS i to VOS i + F SR α ,
denoted by SEGi ; thus, the histogram obtained in iteration
i is a partial histogram, denoted by Histi , that charac-
terizes the ADC behavior within input range SEGi . The
noise, if present, causes the ADC output code to deviate
from its ideal value; this affects the accuracy of obtained
partial histograms, especially for the codes that are close
to the segment boundaries. Furthermore, the offset voltages
may deviate from their specified values. To tolerate these,
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Figure 6. The proposed ADC loopback testing flow.
segments overlap sufficiently. To ensure test quality, in the
“truncate Histi ” stage, the code hits that are more likely to
be affected by noise are removed from the partial histogram
Histi . Finally, the partial histograms are combined to obtain
the full ADC histogram Histf ull from which the ADC DNL
and INL can be derived.
1) Choice of α: The choice of α determines the ADC
test resolution. Recall that we assume the ADC and DAC are
both N -bit and have the same FSR (for ease of illustration).
If one uses the DAC to generate the test ramp without down-
scaling, i.e., α = 1, the average code hit would be merely
one, which is apparently insufficient. Using the down-scaled
DAC output, one improves the final average code hit by α. In
practice, α should be slightly larger than the desired average
code hit when a perfect ramp is applied; the reason is to
compensate for the non-linearity associated with the DAC
itself.
2) Truncating partial histograms: The presence of noise
affect the accuracy of partial histograms, especially for the
codes closer to the segment boundaries. Assume that the
standard deviation of noise is σnoise and let 3 · σnoise
correspond to δ LSB. (δ can be approximated by applying
a DC voltage to the ADC and analyzing the output code
distribution after a sufficiently large number of samples.)
Consider partial histogram Histi and let maxi and mini
be the maximum and minimum codes in Histi that have
non-zero code hits. The codes greater than maxi − 2δ or
less than mini + 2δ are removed from Histi .
3) Choice of offset voltages: Apparently, SEGi ’s with
respect to the selected offset voltages must cover the ADC
FSR. In reality, there must be sufficient overlap between
adjacent SEGi ’s to tolerate imprecise offset voltages and
noise. Assuming that we use t (t > α) evenly spaced seg-
ments to cover the ADC FSR, the overlap between adjacent
SEGi ’s is:
F SR F SR
Voverlap = − (2)
α t
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Figure 7. The proposed DAC loopback testing flow.
To compensate for the offset voltage deviations (with a
maximum of VOS dev ) and the noise (with a standard
deviation of σnoise ), t is selected to satisfy the following
condition.
F SR F SR
− > VOS dev + 6 · σnoise + 1LSB
α t
Clearly, Voverlap must exceed VOS dev to tolerate the offset
voltage deviations. The reason of adding the 6·σnoise term is
according to the partial histogram truncation process which
removes 2δ codes from both ends of each partial histogram.
Finally, the additional 1 LSB term ensures that one can
derive the full histogram by combining the truncated partial
histograms.
C. DAC testing
The proposed loopback testing technique utilizes the ADC
to test the DAC by measuring the output voltage produced by
each current source. Fig. 7 illustrates the DAC testing flow.
First, the gain control block selects RDAC which is β times
larger than RL ; this scales up the DAC output by β. Then,
the flow enters the current source testing loop. Each time,
exactly one current source Ii is connected to RDAC . The
corresponding scaled output voltage VDAC i = Ii ·RDAC is
measured by the ADC and stored. For an N -bit SCS DAC
that has NM SB unary-weighted more significant bits and
NLSB binary-weighted less significant bits, this loop repeats
NLSB + 2NM SB − 1 times. Once all the current sources are
measured, one can construct the full DAC I/O transfer curve
(assuming that the summation is ideal) from which the DAC
DNL and INL can be derived.
1) Choice of β: Intuitively, by increasing β, the relative
quantization error caused by the ADC becomes smaller;
however, β is limited by the ADC FSR. When the largest
current source, i.e., a unary-weighted one, is tested, the re-
sulting output voltage must be within ADC FSR. According
to (1), we have
2NLSB · I0 · RDAC ≤ F SR
loaded with RL , we have
 N 
2 − 1 · I0 · RL = F SR (5)
β≤ ≈ 2NM SB (6)
Note that (6) also implies that the achievable test accuracy
of this DAC testing scheme is limited by the segmented
current-steering DAC architecture.
2) DAC design for testability: To realize the DAC test
flow, the binary-to-thermometer decoder is re-designed so
that when the T E (test enable) input is high, one can turn
on the unary-weighted current source under test by properly
setting the NM SB more significant bits.
D. Discussions
While we can raise the effective ADC/DAC test resolution
by scaling down/up the DAC output, the achievable test
(3) accuracy is ultimately limited by the non-linearity associated
with the ADC and DAC.
Let EN OBDAC be the DAC’s effective number of
bits. The effective ADC test resolution is approximately
EN OBDAC + log2 α. If the DAC is highly non-linear, one
can increase α to maintain the required test accuracy at
the cost of elongated test time (because more segments are
needed to cover the ADC FSR). The analysis is similar for
DAC testing. However, since β is upper bounded, the desired
DAC test resolution is not always attainable.
IV. S IMULATION R ESULTS
We first perform numerical simulations to validate the
proposed technique. The FSR of the DAC output and the
ADC input are both 2 V. The ADC under test is a 12-bit
one-bit/stage pipelined ADC. In each stage, the capacitor
mismatch is randomly set to be within 0.3% and the com-
parator offset is randomly assigned between -3 and +3 mV.
The DAC under test is a 12-bit segmented current-steering
DAC with NM SB = 6 and NLSB = 6; the deviation of each
current source is randomly assigned and bounded by 1%.
During testing, both scaling factors α and β are set to sixty.
Note that, “zero” noise is assumed during the simulation to
demonstrate the maximum achievable test accuracy.
A. ADC testing simulation results
The ADC is first tested by a perfect 20-bit DAC. The
measured INL and DNL are shown in the left-hand side
(LHS) plots of Fig. 8; the maximum DNL and INL are
2.60 and 3.05 LSB, respectively. Note that these results are
considered as the ideal values. Then, the proposed ADC
loopback testing technique is applied. The measured INL
and DNL are shown in the right-hand side (RHS) plots of
(4) Fig. 8; the measured maximum DNL and INL are 2.61 and
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 3 3 1 1

Estimated DAC DNL

Estimated ADC DNL

Actual DAC DNL

Actual ADC DNL
2 2 0.5 0.5

1 1 0 0

0 0 0.5 0.5

1 1 1 1
1000 2000 3000 4000 1000 2000 3000 4000 1000 2000 3000 4000 1000 2000 3000 4000
Code Code Code Code

4 4 1 1

Estimated DAC INL

Estimated ADC INL

Actual DAC INL

Actual ADC INL

2 2 0 0

0 0 1 1

2 2 2 2
1000 2000 3000 4000 1000 2000 3000 4000 1000 2000 3000 4000 1000 2000 3000 4000
Code Code Code Code

Figure 8. The ADC testing simulation results. Figure 10. The DAC testing simulation results.
ADC DNL Estimation Error

DAC DNL Estimation Error

0.04 0.04

0.02
0.02
0
0
0.02

0.04 0.02
500 1000 1500 2000 2500 3000 3500 4000 500 1000 1500 2000 2500 3000 3500 4000
Code Code

0.05
ADC INL Estimation Error

DAC INL Estimation Error

0.04

0.02
0
0
0.05
0.02

0.1 0.04
500 1000 1500 2000 2500 3000 3500 4000 500 1000 1500 2000 2500 3000 3500 4000
Code Code

Figure 9. The simulated ADC test errors. Figure 11. The simulated DAC test errors.

3.07 LSB, respectively. From Fig. 8, it is easy to see that SCS DACs to realize the DAC test flow. Secondly, this
the INL/DNL values obtained by the proposed technique are facilitates very flexible fault injection to the DAC. In the
almost identical to the ideal values. Finally, the INL/DNL experiments, each current source in the emulated DAC is
measurement errors are shown in Fig. 9; the errors are all randomly perturbed by within 2% of its nominal value. The
less than 0.06 LSB. ADC and DAC have the same FSR of 2 V and are both
operated at a sampling rate of 100 KHz.
B. DAC testing simulation results The scaling factor α is set to 25, and β is set to 60; this is
The DAC testing simulation results are shown in Fig. 10. achieved by setting RL , RADC and RDAC in Fig. 3 to 100
On the LHS of the figure are the actual DNL and INL plots Ω, 4 Ω and 6 KΩ, respectively. The offset control circuit is
of the DAC; the peak DNL and INL are -0.62 and -1.92 LSB, implemented by an opamp-based adder; the required offset
respectively. On the RHS of the figure are DNL and INL voltage is provided by NI DAQ (USB-6259). The noise is
plots obtained by the proposed technique; the peak DNL and measured by applying a DC value to the ADC and observe
INL are -0.63 and -1.93 LSB, respectively. The measurement the output code distribution; the measured noise standard
errors are shown in Fig. 9 and are all within 0.04 LSB of deviation is about 0.25 LSB.
the actual values.
A. ADC testing experimental results
V. E XPERIMENTAL R ESULTS We first characterize the ADC under test (ADS825) with
Experiments on commercial ICs are also performed to the 14-bit DAC (THS5671A). The LHS plots in Fig. 12 show
further validate the proposed technique. The ADC under the measured DNL and INL. The peak DNL and INL values
test is a 10-bit pipelined ADC (ADS825 from TI). On the are 0.73 and -2.54 LSB, respectively.
other hand, the DAC under test is emulated using a 14-bit The proposed loopback ADC testing technique is then
current-output DAC (THS5671A from TI); it is a 10-bit SCS applied. Note that (1) the 10-bit DAC is emulated with a
DAC with NM SB = 6 and NLSB = 4. The reasons to use 14-bit one and is fault-injected, and (2) the offset voltages
an emulated DAC are as follows. First, we are unable to are generated by NI DAQ (USB-6259). The measurement
modify the binary-to-thermometer decoder of commercial results are shown in RHS plots of Fig. 12. The peak values

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 1 1 1 1

Estimated DAC DNL

Estimated ADC DNL

Actual DAC DNL

Actual ADC DNL 0.5 0.5 0.5 0.5

0 0 0 0

0.5 0.5 0.5 0.5

1 1 1 1
200 400 600 800 1000 200 400 600 800 1000 200 400 600 800 1000 200 400 600 800 1000
Code Code Code Code

3 3 4 4

Estimated DAC INL

Estimated ADC INL
2 2

Actual DAC INL

Actual ADC INL

1 1 2 2
0 0
1 1 0 0
2 2
3 3 2 2
200 400 600 800 1000 200 400 600 800 1000 200 400 600 800 1000 200 400 600 800 1000
Code Code Code Code

Figure 12. The ADC testing experimental results. Figure 14. The DAC testing experimental results.

DAC DNL Estimation Error

0.2
ADC DNL Estimation Error

0.2
0.1
0.1
0
0
0.1
0.1
0.2
0.2 100 200 300 400 500 600 700 800 900 1000
100 200 300 400 500 600 700 800 900 1000 Code
Code

DAC INL Estimation Error

0.4
0.4
ADC INL Estimation Error

0.2
0.2
0
0
0.2
0.2
0.4
0.4 100 200 300 400 500 600 700 800 900 1000
100 200 300 400 500 600 700 800 900 1000 Code
Code

Figure 15. The DAC testing errors.

Figure 13. The ADC testing errors.

VI. C ONCLUSION
of the estimated DNL and INL are 0.80 and -2.53 LSB, This paper presents a low-cost yet efficient static loopback
which are very close to the actual values. testing technique for an ADC/DAC pair when the DAC is
The estimation errors are shown in Fig. 13; the maximum a segmented current-steering one. The proposed technique
DNL and INL measurement errors are 0.19 and 0.36 LSB, is a promising solution to SoCs with both ADC and DAC
respectively. due to its simplicity and low DfT hardware requirement.
Experimental results based on commercial ICs show that
very high test accuracy can be achieved even in the presence
B. DAC testing experimental results
of noise. In the future, we will investigate the potential fault
The actual performance of the emulated 10-bit DAC masking issue and develop techniques to avoid or recognize
under test is first measured by NI DAQ which has a 16- its occurrence.
bit resolution. The LHS plots of Fig. 14 show the measured R EFERENCES
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4, there are a total of 4 + 26 − 1 = 67 emulated current
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